CN218602421U - Lead frame and packaging structure - Google Patents

Lead frame and packaging structure Download PDF

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Publication number
CN218602421U
CN218602421U CN202220817953.7U CN202220817953U CN218602421U CN 218602421 U CN218602421 U CN 218602421U CN 202220817953 U CN202220817953 U CN 202220817953U CN 218602421 U CN218602421 U CN 218602421U
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China
Prior art keywords
chip
lead frame
resistance
module
island
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Active
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CN202220817953.7U
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Chinese (zh)
Inventor
王雄星
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Shanghai Xinggan Semiconductor Co ltd
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Shanghai Xinggan Semiconductor Co ltd
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Priority to CN202220817953.7U priority Critical patent/CN218602421U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model provides a lead frame and packaging structure, the lead frame includes: the resistance module is arranged in a serpentine structure and has a preset resistance value; the chip carrying island is used for carrying a chip; and the pins are used for being electrically connected with the resistance module and the chip on the chip-loading island. The utility model discloses a set up the resistance module that has predetermined resistance value in the lead frame, it is low with the yield to have avoided the uniformity that extra welding resistance leads to, has improved semiconductor packaging structure's precision and reliability, reduces the technology degree of difficulty.

Description

Lead frame and packaging structure
Technical Field
The utility model relates to a semiconductor field especially relates to a lead frame and packaging structure.
Background
In the semiconductor packaging structure in the prior art, a high-precision resistor is usually arranged inside a packaging body, and the packaging process is complex. Paste dress high accuracy resistance and need special high accuracy SMT (surface mounting technology) equipment, equipment required precision is high, need brush tin cream to the part that bears before pasting in advance, simultaneously, in order to guarantee the uniformity and the accurate position of brushing tin cream, glue thick control and need develop special steel mesh and the scraper that the cooperation was used. After the glue is brushed, the high-precision resistor is brushed by using SMT equipment, and then the high-precision resistor and the bearing part are firmly welded together through reflow soldering and high-temperature welding.
In the packaging method in the prior art, when a high-precision resistor is welded, due to the fact that poor welding identification is difficult to control, problems such as empty welding, insufficient welding, resistor dislocation, resistor bridging, tin balls, tin slag, pollution foreign matters, scratching and the like are prone to occurring, and welding consistency and welding yield are low.
How to improve the precision and reliability of a semiconductor packaging structure and reduce the process difficulty becomes a technical problem to be solved urgently.
Disclosure of Invention
The utility model aims to solve the technical problem that a lead frame and packaging structure are provided to improve semiconductor packaging structure's precision and reliability, reduce the technology degree of difficulty.
The utility model provides a lead frame, include: the resistance module is arranged in a snake-shaped structure and has a preset resistance value; the slide glass island is used for bearing a chip; and the pins are used for being electrically connected with the resistance module and the chip on the chip-loading island.
Optionally, the lead frame is made of a metal copper material.
Optionally, the serpentine structure of the resistor module is pre-designed according to a certain impedance value, so as to fix the resistance value of the lead frame.
Optionally, the lead frame is of an integral structure, and the resistor module is prepared by adopting a chemical etching process.
Optionally, a part of the pins are directly connected with the resistor module, and a part of the pins are electrically connected with the chip through a lead.
The utility model provides a packaging structure, include: the lead frame comprises a snake-shaped structure, a resistance module with a preset resistance value, a chip carrying island for bearing a chip and a plurality of pins; and the chip is borne on the chip carrying island and is electrically connected with part of pins of the lead frame.
The utility model discloses a set up the resistance module that has predetermined resistance value in the lead frame, it is low with the yield to have avoided the uniformity that extra welding resistance leads to, has improved semiconductor packaging structure's precision and reliability, reduces the technology degree of difficulty.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a lead frame according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a package structure according to an embodiment of the present invention;
fig. 3 is a schematic step diagram of a packaging method according to an embodiment of the present invention;
fig. 4A-4D are partial process flow diagrams of a packaging method according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative work belong to the protection scope of the present invention.
Please refer to fig. 1, which is a schematic structural diagram of a lead frame according to an embodiment of the present invention. As shown in fig. 1, the lead frame according to the present embodiment includes: the resistor module 101 is arranged in a serpentine structure, and has a preset resistance value; the chip carrying island 102 is used for carrying a chip; and a plurality of pins 103, the pins 103 for electrical connection with the resistive module 101 and a chip (not shown) on the chip island 102.
Specifically, the lead frame is made of a metal copper material.
Further, the serpentine structure of the resistor module 101 is pre-designed according to a certain impedance value, so as to fix the resistance value of the lead frame. The resistance value is designed by considering the resistivity of the copper material and the shape of the resistor module 101. Namely, the resistance of the resistance module 101 is large when the width of the serpentine structure is large; the resistance of the resistance module 101 is large when the serpentine width is small. The resistance of the resistance module 101 is large when the serpentine structure is bent more; the resistance of the resistance module 101 is small when the serpentine structure is bent.
Further, the lead frame is an integrated structure, and the resistor module 101 is manufactured by a chemical etching process. Specifically, a part of the leads 104 is directly connected to the resistor module 101, and a part of the leads 105 is electrically connected to a chip (not shown) through a wire.
Because the resistance module of predetermined resistance value has been adopted, the utility model provides a lead frame need not to weld high accuracy resistance again. The problems of empty soldering, insufficient soldering, resistor dislocation, resistor bridging, solder balls, tin slag, polluted foreign matters, scratching and the like caused by difficult recognition and control of poor soldering are avoided, and the problems of low soldering consistency and low soldering yield are solved.
The utility model discloses a set up the resistance module that has predetermined resistance value in the lead frame, it is low with the yield to have avoided the uniformity that extra welding resistance leads to, has improved semiconductor packaging structure's precision and reliability, reduces the technology degree of difficulty.
Based on the same utility model discloses think, the utility model also provides an encapsulation construction.
Please refer to fig. 2, which is a schematic structural diagram of a package structure according to an embodiment of the present invention. The utility model provides a packaging structure includes: the lead frame adopts any one of the lead frames, and comprises a serpentine structure, a resistance module 101 with a preset resistance value, a chip-carrying island 102 for bearing a chip 201, and a plurality of pins 103; and the chip 201 is borne on the chip island 102 and is electrically connected with part of the pins 105 of the lead frame.
Specifically, the lead frame is made of a metal copper material. An insulating glue layer 201 is arranged between the chip 201 and the chip carrying island 102, and a packaging shell 204 coats the chip 201, the resistor module 101 and the chip carrying island 102. Part of the pins 104 are directly connected with the resistor module 101, and part of the pins 105 are electrically connected with the chip 201 through leads 203.
The resistance module can be matched with a chip with a built-in current detection circuit and used for detecting the potential condition, the function of detecting multi-path current is realized, the size of the packaging structure is reduced, and the cost is reduced.
Based on the same utility model, the utility model also provides an encapsulation method. Please refer to FIG. 3, FIGS. 4A-4D, and FIG. 2. Fig. 3 is a schematic step diagram of a packaging method according to an embodiment of the present invention; fig. 4A-4D are partial process flow diagrams of a packaging method according to an embodiment of the present invention.
Referring to fig. 3, a packaging method according to an embodiment of the present invention includes the following steps: step S31, providing a chip; step S32, providing a lead frame, including: the resistance module is arranged in a snake-shaped structure and has a preset resistance value; the chip carrying island is used for carrying a chip; the pins are used for being electrically connected with the resistance module and the chip on the slide island; and step S33, bearing the chip on the chip bearing island of the lead frame, and correspondingly and electrically connecting the chip with the partial pins.
Referring to fig. 3 and 4A, in step S31, a chip 201 is provided.
Referring to fig. 3 and 4B, in step S32, a lead frame is provided, which includes: the resistor module 101 is arranged in a serpentine structure, and has a preset resistance value; the chip carrying island 102 is used for carrying a chip; and a plurality of pins 103, the pins 103 being for electrical connection with the resistive module 101 and the chip on the chip island 102. Specifically, the lead frame is made of a metal copper material.
Further, referring to fig. 4C, an insulating glue layer 201 is disposed between the chip and the slide island 102, which is an optional step.
Referring to fig. 3 and 4D, in step S33, the chip 201 is loaded on the carrier island 102 of the lead frame and electrically connected to the partial leads 105 correspondingly. Wherein, part of the pins 104 are directly connected with the resistor module 101, and part of the pins 105 are electrically connected with the chip 201 through leads 203.
Further, referring to fig. 2, the package is completed by using a package housing 204. The package housing 204 encapsulates the chip 201, the resistor module 101, and the chip island 102.
The utility model discloses a set up the resistance module that has predetermined resistance value in the lead frame, it is low with the yield to have avoided the uniformity that extra welding resistance leads to, has improved semiconductor packaging structure's precision and reliability, reduces the technology degree of difficulty. Meanwhile, the resistance module can be matched with a chip with a built-in current detection circuit to detect the potential condition, so that the function of detecting multi-path current is realized, the size of the packaging structure is reduced, and the cost is reduced.
It should be noted that, in the present specification, each specific embodiment is described in a related manner, and the same and similar parts among the specific embodiments may be referred to each other, and each embodiment focuses on the difference from the other embodiments. In particular, for the embodiment of the packaging method, since it is substantially similar to the embodiment of the lead frame and the package structure, the description is simple, and for the relevant points, reference may be made to partial description of the embodiment of the lead frame and the package structure.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims (6)

1. A lead frame, comprising:
the resistance module is arranged in a serpentine structure, the serpentine structure is bent, the resistance of the resistance module is high when the serpentine structure is bent more, the resistance of the resistance module is low when the serpentine structure is bent less, and the resistance module has a preset resistance value;
the chip carrying island is used for carrying a chip; and
and the pins are used for being electrically connected with the resistance module and the chip on the chip-loading island.
2. Lead frame according to claim 1, characterized in that the lead frame is made of a metallic copper material.
3. Lead frame according to claim 1, characterized in that the serpentine configuration of the resistive module is pre-designed with a certain resistance value to fix the resistance value of the lead frame.
4. The lead frame according to claim 1, wherein the lead frame is a unitary structure, and the resistor module is manufactured by a chemical etching process.
5. The lead frame of claim 1, wherein a portion of the leads are directly connected to the resistive module and a portion of the leads are electrically connected to the chip by wires.
6. A package structure, comprising:
a lead frame according to any one of claims 1 to 5, the lead frame comprising a serpentine structure, a resistor module having a predetermined resistance, a chip-carrying island for carrying a chip, and a plurality of leads;
and the chip is borne on the chip carrying island and is electrically connected with part of pins of the lead frame.
CN202220817953.7U 2022-04-01 2022-04-01 Lead frame and packaging structure Active CN218602421U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220817953.7U CN218602421U (en) 2022-04-01 2022-04-01 Lead frame and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220817953.7U CN218602421U (en) 2022-04-01 2022-04-01 Lead frame and packaging structure

Publications (1)

Publication Number Publication Date
CN218602421U true CN218602421U (en) 2023-03-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202220817953.7U Active CN218602421U (en) 2022-04-01 2022-04-01 Lead frame and packaging structure

Country Status (1)

Country Link
CN (1) CN218602421U (en)

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