CN218514113U - Switch control circuit, battery management system, battery pack and electric equipment - Google Patents

Abstract

The embodiment of the application provides a switch control circuit, a battery management system, a battery pack and electric equipment. The switch control circuit includes: the circuit comprises a power switch, a control module, a first resistor, a second resistor and a first switch; the power switch comprises an output pin, an input pin and an enabling pin, the input pin is used for being electrically connected with the voltage output end, the first resistor is electrically connected between the output pin and the first switch, and the second resistor is electrically connected between the first end of the first switch and the second end of the first switch, is connected in series with the first resistor and is electrically connected between the output pin and the ground; the control module is electrically connected to a power switch via an enable pin, the power switch being configured to be responsive to a control signal of the control module to form a voltage signal at an output pin.

Description

Switch control circuit, battery management system, battery pack and electric equipment

Technical Field

The embodiment of the application relates to the technical field of circuits, in particular to a switch control circuit, a battery management system, a battery pack and electric equipment.

Background

At present, semiconductor switching devices represented by MOS transistors are widely used in discharge circuits of batteries, and play an important role in stabilizing discharge of batteries.

Therefore, in order to ensure that the discharge circuit can be used normally, it is necessary to control the semiconductor switching device to be turned on and off while the semiconductor switching device is in use.

SUMMERY OF THE UTILITY MODEL

In order to solve the above problem, embodiments of the present application provide a switch control circuit, a battery management system, a battery pack, and an electric device, so as to at least partially solve the above problem.

According to an aspect of the present application, there is provided a switch control circuit including: the circuit comprises a power switch, a control module, a first resistor, a second resistor and a first switch; the power switch comprises an output pin, an input pin and an enabling pin, the input pin is used for being electrically connected with the voltage output end, the first resistor is electrically connected between the output pin and the first switch, and the second resistor is electrically connected between the first end of the first switch and the second end of the first switch, is connected in series with the first resistor and is electrically connected between the output pin and the ground; the control module is electrically connected to a power switch via an enable pin, the power switch being configured to be responsive to a control signal of the control module to form a voltage signal at the output pin.

Optionally, the control module comprises: the first control unit comprises a first signal terminal, the second switch is electrically connected between the first signal terminal and the power switch, the third resistor and the fourth resistor are connected between the first signal terminal and the ground in series, and the third resistor is also electrically connected between the first end of the second switch and the second end of the second switch; alternatively, the control module includes: the second control unit comprises a second signal terminal, the third switch is electrically connected between the second signal terminal and the power switch, the fifth resistor and the sixth resistor are connected between the second signal terminal and the ground in series, and the sixth resistor is further electrically connected between a first end of the third switch and a second end of the third switch.

Optionally, the control module comprises: the first control unit comprises a first signal terminal, the second switch is electrically connected between the first signal terminal and the power switch, and the third resistor is electrically connected between the first end of the second switch and the second end of the second switch; and, the control module includes: the second control unit comprises a second signal terminal, the fifth resistor and the sixth resistor are connected between the second signal terminal and the ground in series, the sixth resistor is further electrically connected between the first end of the third switch and the second end of the third switch, the third switch is electrically connected between the fourth resistor and the fifth resistor, the first end of the fourth resistor is electrically connected to the third resistor and the first end of the second switch respectively, and the second end of the fourth resistor is electrically connected to the third switch.

Optionally, the power switch further comprises an output discharging pin; the switch control circuit further comprises a seventh resistor, and the seventh resistor is electrically connected between the output discharge pin and the output pin.

Optionally, the power switch further comprises a first pin; the switch control circuit further comprises a first capacitor electrically connected between the first pin and the ground.

Optionally, the switch control circuit comprises a plurality of first switches and a plurality of eighth resistors; the first switch and the eighth resistor form a branch circuit, each branch circuit is connected in parallel, and each branch circuit is electrically connected between the first resistor and the ground.

Optionally, the switch control circuit further includes a ninth resistor, a first end of the ninth resistor is electrically connected to the enable pin, and a second end of the ninth resistor is grounded.

Optionally, the switch control circuit further comprises: the first end of the second capacitor and the first end of the third capacitor are electrically connected and then electrically connected with the input pin, and the second end of the second capacitor and the second end of the third capacitor are electrically connected and then grounded; the voltage output end is electrically connected with the anode of the first diode, and the cathode of the first diode is electrically connected with the first end of the second capacitor.

According to a second aspect of the present application, there is provided a battery management system comprising: the switch control circuit of any one of the aspects as provided in the first aspect.

According to a third aspect of the present application, a battery pack is provided, wherein the battery pack comprises a battery module and the battery management system as provided in the second aspect.

According to a third aspect of the present application, there is provided an electric device comprising: the battery pack as provided in the third aspect.

Due to the fact that the power switch exists in the switch control circuit of the embodiment of the application, the power switch can respond to the control signal of the control module to form the voltage signal at the output pin. It can be understood that, the switching power supply may respond to the first control signal of the control module, so that the input pin and the output pin of the switching power supply are turned on to form a voltage signal for driving the first switch at the output pin, at this time, the voltage output terminal and the first resistor are turned on, and the voltage output terminal applies a voltage to the first switch through the output pin of the power supply switch, so that the first switch meets a turn-on condition to drive the first switch to be turned on; the switch power supply can respond to a second control signal of the control module, so that the input pin and the output pin of the switch power supply are disconnected, and the voltage output end is disconnected with the first switch through the power switch to achieve the turn-off of the first switch. Therefore, when the first switch is used for a discharging MOS (metal oxide semiconductor) tube of a battery pack discharging circuit, the power switch can be controlled through the control module so as to enable the first switch to be switched on or switched off.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in the embodiments of the present application, and other drawings can be obtained by those skilled in the art according to these drawings.

Fig. 1 shows a schematic circuit diagram of an exemplary switch control circuit according to the present application.

Fig. 2 shows a circuit schematic of another exemplary switch control circuit according to the present application.

Fig. 3 illustrates a circuit schematic diagram of yet another exemplary switch control circuit according to the present application.

Fig. 4 shows a schematic circuit diagram of a further exemplary switch control circuit according to the present application.

Fig. 5 shows a schematic diagram of a chip internal circuit structure when the power switch is a TPS22810 chip.

Fig. 6 shows a schematic diagram of an exemplary battery management system according to the application.

Fig. 7 shows a schematic diagram of an exemplary battery pack according to the present application.

FIG. 8 illustrates a schematic diagram of an exemplary powered device according to the present application.

Detailed Description

In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application shall fall within the scope of protection of the embodiments in the present application.

According to a first aspect of the present application, referring to fig. 1-4, the present application provides a switch control circuit 100, the switch control circuit 100 comprising: the circuit comprises a power switch 10, a control module 10, a first resistor R1, a second resistor R2 and a first switch Q1; the power switch 10 includes an output pin VOUT, an input pin VIN and an enable pin EN, the input pin VIN is used for being electrically connected with the voltage output terminal VCC, the first resistor R1 is electrically connected between the output pin VOUT and the first switch Q1, the second resistor R2 is electrically connected between the first end of the first switch Q1 and the second end of the first switch Q1, and forms a series connection with the first resistor R1 and is electrically connected between the output pin VOUT and the ground; the control module 20 is electrically connected to the power switch 10 through an enable pin EN, and the power switch 10 is configured to be able to respond to a control signal of the control module 10 to form a voltage signal at an output pin.

Due to the fact that the power switch exists in the switch control circuit of the embodiment of the application, the power switch can respond to the control signal of the control module to form the voltage signal at the output pin. It can be understood that, the switching power supply may respond to the first control signal of the control module, so that the input pin and the output pin of the switching power supply are turned on to form a voltage signal for driving the first switch at the output pin, at this time, the voltage output terminal and the first resistor are turned on, and the voltage output terminal applies a voltage to the first switch through the output pin of the power supply switch, so that the first switch meets a turn-on condition to drive the first switch to be turned on; the switching power supply can respond to a second control signal of the control module, so that the input pin and the output pin of the switching power supply are disconnected, and the voltage output end is electrically connected with the first switch through the disconnection of the power switch, so that the first switch is turned off. Therefore, when the first switch is used for a discharging MOS (metal oxide semiconductor) tube of a battery pack discharging circuit, the power switch can be controlled through the control module so as to enable the first switch to be switched on or switched off.

In addition, since the power switch 10 in the embodiment of the present application has one output pin VOUT and one input pin VIN, the power switch 10 can be controlled effectively without wasting pin resources of the power switch 10. The utility model provides a switch control circuit is when PCB layout wiring design, can design the mounted position of switch 10 in the proximity of first switch Q1 (for example for discharge circuit's discharge MOS pipe), can save the space of layout wiring when PCB design like this, and make switch control circuit except that first switch Q1 and switch 10 other electronic component's layout wiring more nimble, and because can reduce the circuit length between first switch Q1 and the switch 10 in step when PCB layout wiring design, consequently can realize the charge when first switch Q1 switches off more fast and release, accelerate the turn-off speed of first switch Q1.

The following detailed description of the switch control circuit 100 in the present application should be understood that the following description is not intended to limit the present application in any way.

The first switch Q1 in the present application may be a MOS transistor, for example, a discharge MOS transistor for a battery pack discharge circuit. It is understood that the first switch Q1 may also be a relay, an IGBT or other switches. In some alternative embodiments, the first switch Q1 is an NMOS transistor, and correspondingly, the first terminal of the first switch Q1 may be a gate of the first switch Q1, and the second terminal of the first switch Q1 may be a source of the first switch Q1. The second resistor R2 serves as a bias resistor of the first switch Q1.

The voltage output terminal VCC in this application may be a voltage output terminal of an external power supply, and the voltage output terminal VCC may output a power supply voltage to the switch control circuit 100. The magnitude of the power supply voltage output by the voltage output terminal VCC is not limited here, and the requirement can be satisfied. Illustratively, may be +12V, +20V, etc. Hereinafter, for the convenience of describing the present embodiment, the +12V is taken as an example.

In this application, the power switch 10 may be a switch chip, which can be turned on after receiving the control signal sent by the control module 20, that is, a conductive connection is formed between the input pin and the output pin of the power switch 10. In this embodiment, the electrical connection between the input pin VIN and the output pin VOUT is on, that is, the power switch 10 is on, and the electrical connection between the input pin VIN and the output pin VOUT is off, that is, the power switch 10 is off.

The control signal may be used for enabling the power switch 10, the power switch 10 may include an enable pin EN, an input pin VIN, and an output pin VOUT, wherein the control module 20 is electrically connected to the enable pin EN, the voltage output terminal VCC is electrically connected to the input pin VIN, the first resistor R1 is electrically connected to the output pin VOUT, after the control module 20 sends a control signal to the enable pin EN, the power switch 10 is enabled according to the control signal, the power switch 10 is enabled to conduct the electrical connection between the input pin VIN and the output pin VOUT, so that the voltage input terminal VCC applies a voltage to the first switch Q1 through the power switch 10 and the first resistor R1, thereby implementing the conduction of the first switch Q1.

For example, the control signal sent by the control module 20 may be a high level signal, and the power switch 10 is turned on after receiving the high level signal sent by the control module 20, and is continuously turned on when the high level signal is maintained, so as to turn on the electrical connection between the voltage output terminal VCC and the first resistor R1; when the high level signal disappears, the power switch 10 is turned off to disconnect the electrical connection between the voltage output terminal VCC and the first resistor R1.

When the power switch 10 is a switch chip, the chip type and specific model of the power switch 10 are not particularly limited in this application. For example, the power switch 10 may be a single-channel load switch chip, and since the single-channel load switch chip has one input pin and one output pin, when controlling the on and off of the first switch Q1, the waste of pin resources such as other input pins and output pins does not occur. Illustratively, the single channel load switch chip may include a TPS22810 chip. In an example switch control circuit, the power switch 10 may be a TPS22810DBVR chip.

In the present application, the control module 20 of the switch control circuit 100 may include any circuit structure as long as the requirement of sending the control signal to the power switch 10 is satisfied. Referring to fig. 1, in some alternative implementations, the control module 20 includes: the first control unit MCU comprises a first signal terminal 21, the second switch Q2 is electrically connected between the first signal terminal 21 and the power switch 10, the third resistor R3 and the fourth resistor R4 are connected in series between the first signal terminal 21 and the ground, and the third resistor R3 is also electrically connected between the first end of the second switch Q2 and the second end of the second switch Q2; alternatively, as shown in fig. 2, the control module 20 includes: a second control unit AFE (Analog Front End), a third switch Q3, a fifth resistor R5, and a sixth resistor R6, wherein the second control unit AFE includes a second signal terminal 22, the third switch Q3 is electrically connected between the second signal terminal 22 and the power switch 10, the fifth resistor R5 and the sixth resistor R6 are connected in series between the second signal terminal 22 and the ground, and the sixth resistor R6 is further electrically connected between a first End of the third switch Q3 and a second End of the third switch Q3.

In this application, the first control unit MCU may be an MCU main control unit of a Battery Management System (BMS), and the second control unit AFE may be a control unit in a front-end acquisition circuit of the Battery Management System. The first signal terminal 21 is a control signal output terminal of the first control unit MCU, and the second signal terminal 22 is a control signal output terminal of the second control unit AFE. Through the circuit structure, the switch control circuit in the application can meet different requirements of battery discharge.

Referring to the circuit shown in fig. 1, it shows a case where the control module 20 includes a first control unit MCU, a second switch Q2, a third resistor R3, and a fourth resistor R4. Optionally, in this embodiment, the second switch Q2 is a PMOS transistor, the first terminal of the second switch Q2 is a gate of the second switch Q2, and the second terminal of the second switch Q2 is a source of the second switch Q2. Specifically, the first signal terminal 21 is electrically connected to the source of the second switch Q2, the gate of the second switch Q2 is electrically connected to the first end of the fourth resistor R4, the first end of the third resistor R3 is electrically connected to the first signal terminal 21, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, the drain of the second switch Q2 is electrically connected to the power switch 10, and the second end of the fourth resistor R4 is grounded.

Specifically, the second switch Q2 is a PMOS transistor, the first control unit MCU outputs a control signal to a source of the second switch Q2 (i.e., a second end of the second switch Q2) through the first signal terminal 21, the control signal is a high level signal, a gate of the second switch Q2 (i.e., a first end of the second switch Q2) is grounded through the fourth resistor R4, so that the second switch Q2 is turned on, and the control signal reaches the power switch 10 (e.g., the power switch 10 is a TPS22810 chip, the control signal reaches the enable pin EN of the power switch 10), and the power switch 10 is turned on in response to the high level control signal, so as to turn on the electrical connection between the voltage output terminal VCC and the first resistor R1. When the first control unit MCU outputs a low level signal, the second switch Q2 is turned off, and the power switch 10 is turned off to disconnect the electrical connection between the voltage output terminal VCC and the first resistor R1.

The fourth resistor R4 can divide the voltage to prevent the voltage of the second switch Q2 from exceeding the withstand voltage of the second switch Q2, and plays a role of limiting the current, and the third resistor R3 serves as a bias resistor of the second switch Q2.

Such an optional circuit structure can be applied to a discharge circuit that can be controlled by an MCU main control unit (i.e., a first control unit MCU) of the battery management system, and can enable the switch control circuit 100 to better control the on and off of the first switch Q1, thereby better satisfying the discharge requirement of the battery pack.

Referring to the circuit shown in fig. 2, it shows a case where the control module 20 includes a second control unit AFE, a third switch Q3, a fifth resistor R5, and a sixth resistor R6. Optionally, in this embodiment, the third switch Q3 is an NMOS transistor, the first terminal of the third switch Q3 is a gate of the third switch Q3, and the second terminal of the third switch Q3 is a source of the third switch Q3. Specifically, the second signal terminal 22 is electrically connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is electrically connected to the gate of the third switch Q3, a first end of the sixth resistor R6 is electrically connected to a second end of the fifth resistor R5, a second end of the sixth resistor R6 is grounded, the source of the third switch Q3 is grounded, and the drain of the third switch Q3 is electrically connected to the power switch 10.

Specifically, the third switch Q3 is an NMOS transistor, and the second control unit AFE outputs a control signal to the gate of the third switch Q3 (i.e., the first end of the third switch Q3) through the second signal terminal 22, where the control signal is a high-level signal, and the source of the third switch Q3 (i.e., the second end of the third switch Q3) is grounded, so that the third switch Q3 is turned on, so that the control signal reaches the power switch 10 (for example, the power switch 10 is a TPS22810 chip, and the control signal reaches the enable pin EN of the power switch 10), and the power switch 10 is turned on in response to the high-level control signal to turn on the electrical connection between the voltage output terminal VCC and the first resistor R1. When the second control unit AFE outputs a low level signal, the third switch Q3 is turned off, and the power switch 10 is turned off to disconnect the electrical connection between the voltage output terminal VCC and the first resistor R1.

The fifth resistor R5 and the sixth resistor R6 can divide the voltage to prevent the voltage of the third switch Q3 from exceeding the withstand voltage of the third switch Q3, the fifth resistor R5, the parasitic inductor and the parasitic inductor form an RLC circuit to reduce oscillation due to LC resonance of the parasitic inductor in the third switch Q3 and the parasitic capacitor in the circuit, and the sixth resistor R6 is used as a bias resistor of the third switch Q3.

Such an optional circuit structure can be applied to a discharge circuit that can be controlled by a control unit (i.e., the second control unit AFE) in a front-end acquisition circuit of the battery management system, and can enable the switch control circuit 100 to better control the on and off of the first switch Q1, thereby better meeting the discharge requirement of the battery pack.

Referring to the circuit shown in fig. 3, it shows a case where the control module 20 includes a first control unit MCU and a second switch Q2, and a second control unit AFE and a third switch Q3. Optionally, the control module 20 comprises: the power supply comprises a first control unit MCU, a second switch Q2, a third resistor R3 and a fourth resistor R4, wherein the first control unit MCU comprises a first signal terminal 21, the second switch Q2 is electrically connected between the first signal terminal 21 and a power switch 10, and the third resistor R3 is electrically connected between a first end of the second switch Q2 and a second end of the second switch Q2; and, the control module 20 includes: the second control unit AFE includes a second signal terminal 22, a fifth resistor R5 and a sixth resistor R6 connected in series between the second signal terminal 22 and ground, the sixth resistor R6 is further electrically connected between a first end of the third switch Q3 and a second end of the third switch Q3, the third switch Q3 is electrically connected between the fourth resistor R2 and the fifth resistor R5, a second end of the fourth resistor R4 is electrically connected to the third switch Q3, and a first end of the fourth resistor R4 is electrically connected to the third resistor R1 and a first end of the second switch Q2, respectively.

Optionally, the second switch Q2 is a PMOS transistor, a first end of the second switch Q2 is a gate of the second switch Q2, and a second end of the second switch Q2 is a source of the second switch Q2; the third switch Q3 is an NMOS transistor, a first end of the third switch Q3 is a gate of the third switch Q3, and a second end of the third switch Q3 is a source of the third switch Q3. Specifically, the first signal terminal 21 is electrically connected to the source of the second switch Q2, the gate of the second switch Q2 is electrically connected to the first end of the fourth resistor R4, the first end of the third resistor R3 is electrically connected to the first signal terminal 21, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, and the drain of the second switch Q2 is electrically connected to the power switch 10; the second signal terminal 22 is electrically connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is electrically connected to the gate of the third switch Q3, a first end of the sixth resistor R6 is electrically connected to a second end of the fifth resistor R5, a second end of the sixth resistor R6 is grounded, the source of the third switch Q3 is grounded, and the drain of the third switch Q3 is electrically connected to a second end of the fourth resistor R4.

Specifically, in this circuit structure, when the first control unit MCU outputs a high level signal to the source of the second switch Q2 (i.e., the first end of the second switch Q2) through the first signal terminal 21, and the second control unit 22 simultaneously outputs a high level signal to the gate of the third switch Q3 (i.e., the first end of the third switch Q3) through the second signal terminal 22, the second switch Q2 is turned on, the third switch Q3 is turned on, so that a high level control signal reaches the power switch 10 (for example, the power switch 10 is a TPS22810 chip, and the control signal reaches the enable pin EN of the power switch 10), and the power switch 10 is turned on in response to the high level control signal to electrically connect the voltage output terminal VCC with the first resistor R1. When at least one of the first control unit MCU and the second control unit AFE outputs a low level signal, the second switch Q2 is turned off, the third switch Q3 is turned off, and the power switch 10 is turned off to disconnect the electrical connection between the voltage output terminal VCC and the first resistor R1.

The fourth resistor R4 can divide voltage to prevent the voltage of the second switch Q2 from exceeding the withstand voltage value of the second switch Q2 and play a role in limiting current, and the third resistor R3 is used as a bias resistor of the second switch Q2; the fifth resistor R5 and the sixth resistor R6 can divide the voltage to prevent the voltage of the third switch Q3 from exceeding the withstand voltage of the third switch Q3, the fifth resistor R5, the parasitic inductor and the parasitic inductor form an RLC circuit to reduce oscillation due to LC resonance of the parasitic inductor in the third switch Q3 and the parasitic capacitor in the circuit, and the sixth resistor R6 is used as a bias resistor of the third switch Q3.

It is easy to see that, in this circuit structure, the second switch Q2, the third resistor R3, the fourth resistor R4, the third switch Q3, the fifth resistor R5, and the sixth resistor R6 form an and circuit, and only the first control unit MCU and the second control unit AFE output high level signals at the same time, and finally, a high level control signal arrives at the power switch 10, otherwise, the power switch 10 cannot receive the high level control signal of the control module 20. In this embodiment, the first control unit MCU and the second control unit AFE are used simultaneously to control the enabling of the switching power supply 10, so that it can be prevented that the first switch Q1 cannot be turned off or on due to the failure of the first control unit MCU or the single failure of the second control unit AFE.

Such an optional circuit structure can be applied to a discharge circuit which can be controlled by both an MCU main control unit (i.e., a first control unit MCU) of a battery management system and a control unit (i.e., a second control unit AFE) in a front-end acquisition circuit, so that the switch control circuit 100 can better control the on and off of the first switch Q1, and the requirement of battery pack discharge can be better met.

In addition, in this optional circuit structure, when the circuit is used, under the condition of no abnormality, the first control unit MCU may be used to transmit the control signal to control the on and off of the first switch Q1 by the switch control circuit 100, and when the first control unit MCU has a fault or other abnormal conditions occur, the second control unit AFE may be used to control the off of the first switch Q1. For example, the first control unit MCU may have a fault and always outputs a high level signal, and at this time, the second control unit AFE may output a low level signal to turn off the second switch Q2, the control signal of the control module 20 is a low level signal, the power switch 10 is turned off, and further, the electrical connection between the voltage output terminal VCC and the first resistor R1 is disconnected, and the first switch Q1 is turned off. For another example, the second control unit AFE may send the high level signal in some optional cases based on an instruction of the first control unit MCU, and when the first control unit MCU fails to communicate with the second control unit AFE, the first control unit MCU cannot give an instruction to the second control unit AFE, and the second control unit AFE does not send the high level signal in such a case, and then the first switch Q1 is kept off. For another example, since the second control unit AFE is a control unit in the front-end acquisition circuit of the battery management system, it may detect the voltage of the battery pack during discharging, and when the detected voltage is less than a threshold (for example, when the detected voltage exceeds the threshold, it represents that the battery pack has an over-discharge phenomenon), the second control unit AFE directly outputs a low level signal to turn off the second switch Q2 regardless of the action of the first control unit MCU, so as to turn off the first switch Q1. It is to be understood that these are by way of illustration only and are not to be construed as limitations in the present application.

In some alternative embodiments, as shown with reference to fig. 1, 2, 3 or 4, the power switch 10 further includes an output discharge pin QOD; the switch control circuit 100 further includes a seventh resistor R7, and the seventh resistor R7 is electrically connected between the output discharging pin QOD and the output pin VOUT.

Specifically, a first end of the seventh resistor R7 is electrically connected to the output discharge pin QOD, and a second end of the seventh resistor R7 is electrically connected to the output pin VOUT.

Specifically, the power switch 10 of the embodiment of the present application may be a single-channel load switch chip, such as a TPS22810 chip, which has a Quick Output Discharge (QOD) function. The power switch 10 is a TPS22810 chip, and has an input pin VIN, an output pin VOUT, an output discharge pin QOD, an enable pin EN, a ground pin GND, and the like.

When the power switch 10 is a TPS22810 chip, due to its internal circuit, the turn-off speed of the first switch Q1 can be adjusted by adjusting the resistance of the seventh resistor R7 connected between its output discharging pin QOD and output pin VOUT. When the resistance of the seventh resistor R7 is smaller, the first switch Q1 is turned off faster. Based on this, the present embodiment can further satisfy the requirement that the switch control circuit 100 controls the first switch Q1 to turn off. The resistance of the seventh resistor R7 is much smaller than that of the second resistor R2, for example, the resistance of the seventh resistor R7 may range from several hundred ohms to one thousand ohms, and the resistance of the second resistor R2 may be in the order of mega ohms.

For example, the first switch Q1 is an NMOS transistor, and after the power switch 10 is turned off, the voltage applied between the gate and the source of the first switch Q1 by the voltage output terminal VCC disappears, but since a parasitic capacitor exists inside the first switch Q1, charges are stored in the parasitic capacitor, and when the first switch Q1 is turned off, the charges in the parasitic capacitor are discharged, and then the first switch Q1 is turned off. When the first switch Q1 is turned off, the charge draining circuit includes two circuits: one is that charge is discharged from the second resistor R2 to ground; second, the charges are discharged from the first resistor R1 and the seventh resistor R7 through the power switch 10 (for example, a TPS22810 chip). In this application, the turn-off speed of the first switch Q1 can be adjusted by adjusting the resistance of the seventh resistor R7, wherein the smaller the resistance of the seventh resistor R7 is, the faster the turn-off speed of the first switch Q1 is.

The basic principle of the TPS22810 chip can be understood with reference to the chip handbook and other prior arts, and will not be described herein.

In some alternative embodiments, referring to fig. 1, 2, 3 or 4, the power switch 10 further includes a first pin CT; the switch control circuit further comprises a first capacitor C1, and the first capacitor C1 is electrically connected between the first pin CT and the ground.

Specifically, a first end of the first capacitor C1 is electrically connected to the first pin CT, and a second end of the first capacitor C1 is grounded.

Still, the power switch 10 in the present application is described as a single-channel load switch chip TPS22810, and specifically, the single-channel load switch chip TPS22810 includes an enable pin EN, a ground pin GND, and the like in addition to an input pin VIN, an output pin VOUT, and an output discharge pin QOD, and further includes a first pin CT for configuring the on-speed of the power switch 10. The first end of the first capacitor C1 may be electrically connected to the first pin CT of the power switch 10, and the second end of the first capacitor C1 is grounded, so that the on-speed of the power switch 10 may be adjusted by changing the size of the first capacitor C1, and the on-speed of the first switch Q1 is changed, thereby further meeting the requirement of the switch control circuit for controlling the on-state of the first switch Q1. As the first capacitor C1 is smaller, the conduction speed of the power switch 10 is faster, and further the conduction speed of the first switch Q1 is faster. Based on this, the present embodiment can further satisfy the requirement that the switch control circuit 100 controls the first switch Q1 to be turned on.

In some alternative embodiments, referring to fig. 4, the switch control circuit 100 further includes: and a first end of the eighth resistor R8 is connected with the second end of the first resistor R1, and a second end of the eighth resistor R8 is connected with the first end of the first switch Q1.

Specifically, referring to fig. 4, the first switch Q1 is an NMOS transistor, a first end of the first switch Q1 is a gate of the first switch Q1, the gate of the first switch Q1 is electrically connected to a second end of the eighth resistor R8, and a source of the first switch Q1 is grounded.

The eighth resistor R8 may also prevent the first switch Q1 from oscillating, thereby protecting the first switch Q1 from breakdown and reducing the gate charging peak current of the first switch Q1.

Referring to fig. 4, the switch control circuit 100 includes a plurality of first switches Q1 and a plurality of eighth resistors R8; the first switch Q1 and the eighth resistor R8 form a branch circuit, and each branch circuit is connected in parallel, and each branch circuit is electrically connected between the first resistor R1 and ground.

Specifically, the first switch Q1 is an NMOS transistor, and there is a case where branches formed by 4 first switches Q1 and the eighth resistor R8 are connected in parallel in fig. 4. The eighth resistor R8 may function to synchronously turn on the plurality of parallel first switches. It can be understood that, usually, on a circuit board, the positions of the first switches Q1 are different, and referring to fig. 4, if an eighth resistor R8 is not provided between the second end of the first resistor R1 and each first switch Q1, the impedance of each wire connected between the second end of the first resistor R1 and the gate of each first switch Q1 is in milliohm level, the current flowing through each first switch Q1 may be greatly different, so that the first switches Q1 cannot be synchronously turned on, and the first switch Q1 turned on first cannot bear a large current and is broken down. If the eighth resistor R8 is disposed between the second end of the first resistor R1 and each first switch Q1, and the resistance of the eighth resistor R8 may be within 100 Ω, for example, 47 Ω or 51 Ω, the impedance of each wire connected between the second end of the first resistor R1 and the gate of each first switch Q1 may be negligible relative to the eighth resistor, so as to ensure that the currents flowing through each first switch Q1 are substantially the same, and further, each first switch Q1 is turned on substantially synchronously. It should be understood that the circuit structure of fig. 4 is only used as an example and is not used to limit the embodiments of the present application.

For example, in some exemplary embodiments, each first switch Q1 and one eighth resistor R8 may form a branch, different first switches Q1 and different eighth resistors R8 form branches, the branches are connected in parallel, and each branch is electrically connected between the first resistor R1 and ground.

In this embodiment, the second resistor R2 serves as a bias resistor of the first switch Q1. Since the parasitic inductance in the first switch Q1 and the parasitic capacitance in the circuit generate LC resonance, the first resistor R1 forms an RLC circuit with the parasitic inductance and the parasitic inductance to reduce oscillation.

In some optional embodiments, referring to fig. 1, fig. 2, fig. 3, or fig. 4, the switch control circuit 100 further includes a ninth resistor R9, a first end of the ninth resistor R9 is electrically connected to the enable pin EN, and a second end of the ninth resistor R9 is grounded.

Specifically, referring to fig. 3 for explanation, when the power switch 10 is a single-channel load switch chip TPS22810, the ninth resistor R9 in this application is used as a pull-down resistor, and after the second switch Q2 of the control module 20 is turned off, the level of the enable pin EN of the power switch 10 may be pulled down to a low level, so as to prevent the enable pin EN of the power switch 10 from being in a floating state after the second switch Q2 of the control module 20 is turned off.

In some optional embodiments, referring to fig. 1, fig. 2, fig. 3, or fig. 4, the switch control circuit 100 further includes: the first diode D1, the second capacitor C2 and the third capacitor C3, the first end of the second capacitor C2 and the first end of the third capacitor C3 are electrically connected and then electrically connected to the input pin VIN, and the second end of the second capacitor C2 and the second end of the third capacitor C3 are electrically connected and then grounded; the voltage output terminal VCC is electrically connected to the anode of the first diode D1, and the cathode of the first diode D1 is electrically connected to the first end of the second capacitor C2.

Specifically, the first diode D1 may be used as an anti-reflection diode, the power supply voltage output by the voltage output terminal VCC is a positive voltage (for example, + 12V), and the power supply voltage may be stored and stabilized through the first diode D1, the second capacitor C2 and the third capacitor C3, so that the drop of the power supply voltage (for example, + 12V) when the first switch Q1 (for example, an NMOS transistor) is driven after the power switch 10 is turned on is reduced, and the power supply voltage input to the second capacitor C2 and the third capacitor C3 cannot be reversely input to the voltage output terminal VCC through the first diode D1, which is favorable for protecting an external power supply; in addition, under the energy storage and voltage stabilization effects of the second capacitor C2 and the third capacitor C3, the voltage at the input pin VIN of the power switch 10 does not rise or fall instantaneously, which can prevent the switch control circuit from being turned off by mistake due to the instantaneous drop of the power voltage output by the voltage output terminal VCC, and further ensure the stability of the switch control circuit 100 for switching the first switch Q1.

In some alternative embodiments, referring to fig. 1, 2, 3 or 4, the switch control circuit 100 further comprises: and the control module 20 is electrically connected with the enable pin EN through the filtering module. The filter module is configured to filter the control signal of the control module 20.

Specifically, referring to fig. 3, the filtering module includes a tenth resistor R10 and a fourth capacitor C4, a first end of the tenth resistor R10 is electrically connected to a drain of the second switch Q2, when the power switch 10 is a single-channel load switch chip TPS22810, a second end of the tenth resistor R10 is connected to an enable pin EN of the power switch 10, a first end of the fourth capacitor C4 is electrically connected to a second end of the tenth resistor R10, and a second end of the fourth capacitor C4 is grounded.

In the following, an exemplary switch control circuit 100 in the embodiment of the present application is further described with reference to fig. 3, and it should be understood that the following disclosure is not intended to limit the embodiment of the present application in any way.

Referring to fig. 3, the switch control circuit 100 includes a power switch 10, a control module 20, a first resistor R1, a second resistor R2, and a first switch Q1, where the first switch Q1 is an NMOS transistor, the power switch 10 includes a single-channel load switch chip TPS22810, and a source of the first switch Q1 (i.e., a second end of the first switch Q1) is grounded;

the power switch 10 comprises an input pin VIN, an output pin VOUT, an output discharge pin QOD, an enable pin EN, a first pin CT and a grounding pin GND, wherein the grounding pin GND is grounded;

the switch control circuit 100 further includes a first diode D1, a second capacitor C2, and a third capacitor C3, wherein a first end of the second capacitor C2 and a first end of the third capacitor C3 are electrically connected to an input pin VIN of the power switch 10, and a second end of the second capacitor C2 and a second end of the third capacitor C3 are electrically connected to ground; the voltage output end VCC is electrically connected with the anode of the first diode D1, and the cathode of the first diode D1 is electrically connected with the first end of the second capacitor C2;

the switch control circuit 100 further includes a ninth resistor R9, a first end of the ninth resistor R9 is electrically connected to the enable pin EN of the power switch 10, and a second end of the ninth resistor R9 is grounded;

the switch control circuit 100 further includes a filtering module, where the filtering module includes a tenth resistor R10 and a fourth capacitor C4, a second end of the tenth resistor R10 is connected to an enable pin EN of the power switch 10, a first end of the fourth capacitor C4 is electrically connected to a second end of the tenth resistor R10, and a second end of the fourth capacitor C4 is grounded;

the control module 20 includes a first control unit MCU and a second switch Q2 and a second control unit AFE and a third switch Q3; the control module 20 further includes: a third resistor R3 and a fourth resistor R4; the second switch Q2 is a PMOS transistor, the first signal terminal 21 is electrically connected to a source of the second switch Q2 (i.e., the second end of the second switch Q2), a gate of the second switch Q2 (i.e., the first end of the second switch Q2) is electrically connected to the first end of the fourth resistor R4, the first end of the third resistor R3 is electrically connected to the first signal terminal 21, the second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4, and a drain of the second switch Q2 is electrically connected to the first end of the tenth resistor R10, so as to be electrically connected to the enable pin EN of the power switch 10 through the filter module; the control module 20 further includes: a fifth resistor R5 and a sixth resistor R6; the third switch Q3 is an NMOS transistor, the second signal terminal 22 is electrically connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is electrically connected to a gate of the third switch Q3 (i.e., the first end of the third switch Q3), a first end of the sixth resistor R6 is electrically connected to a second end of the fifth resistor R5, a second end of the sixth resistor R6 is grounded, a source of the third switch Q3 (i.e., the second end of the third switch Q3) is grounded, and a drain of the third switch Q3 is electrically connected to a second end of the fourth resistor R4;

the switch control circuit 100 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the first pin CT of the power switch 10, and a second end of the first capacitor C1 is grounded;

the switch control circuit 100 further includes a seventh resistor R7; a first end of the seventh resistor R7 is electrically connected to the output discharging pin QOD of the power switch 10, a second end of the seventh resistor R7 is electrically connected to the output pin VOUT of the power switch 10, a first end of the first resistor R1 is electrically connected to the output pin VOUT of the power switch 10, a first end of the second resistor R2 is electrically connected to a second end of the first resistor R1, and a second end of the second resistor R2 is grounded; the second end of the first resistor R1 and the first end of the second resistor R2 are electrically connected to the gate of the first switch Q1 (i.e., the first end of the first switch Q1), respectively, and the source of the first switch Q1 (i.e., the second end of the first switch Q1) is grounded.

Referring to fig. 5 again, it shows a structure diagram of a circuit inside a chip when the power switch 10 is a TPS22810 chip, and it can be seen that a first MOS transistor Q4 exists between an output pin VOUT and an input pin VIN of the power switch 10, a second MOS transistor Q5 exists between an output discharge pin QOD and a ground pin GND of the power switch, and the first pin CT is electrically connected to a gate of the first MOS transistor Q4.

The operation of the switch control circuit 100 is briefly described below with reference to fig. 3 and 5:

the switch control circuit 100 controls the conduction of the first switch Q1:

referring to fig. 3, when the first control unit MCU and the second control unit AFE output a high level at the same time, the second switch Q2 is turned on, the third switch Q3 is turned on, and in this circuit structure, the drain of the second switch Q2 is used as the output end of the control module 20, the output end of the control module 20 outputs a control signal of a high level, and the control signal is filtered by the filter module composed of the tenth resistor R10 and the fourth capacitor C4 and then input to the enable pin EN of the power switch 10; the voltage output terminal VCC of the external power supply outputs the power supply voltage (taking +12V as an example), which is stored and stabilized by the first diode D1, the second capacitor C2 and the third capacitor C3, and then is connected to the input pin VIN of the power switch 10.

Referring to fig. 5, after the high-level control signal enters the enable pin EN, the power switch 10 is enabled through the logic control unit of the power switch 10, and then the high-level control signal acts on the gate of the first MOS transistor Q4, so that the first MOS transistor Q4 is turned on, and the electrical connection between the input pin VIN and the output pin VOUT of the power switch 10 is turned on, and the power voltage (+ 12V) is transmitted from the input pin VIN to the output pin VOUT.

Because the first MOS transistor Q4 in the power switch 10 has a parasitic capacitance, when the parasitic capacitance is fully charged, the first MOS transistor Q4 is turned on, so the first pin CT of the power switch 10 is connected to the first capacitor C1, which is equivalent to being connected in parallel with the parasitic capacitance of the first MOS transistor Q4, and the first capacitor C1 is equivalent to increasing the parasitic capacitance of the first MOS transistor Q4, therefore, the larger the capacitance value of the first capacitor C1 is, the longer the charging time required for turning on the first MOS transistor Q4 is, and therefore, by changing the size of the first capacitor C1, the turning-on speed of the power switch 10 can be adjusted, and further, the turning-on speed of the first switch Q1 is adjusted.

Referring to fig. 3, after the power voltage (+ 12V) is transmitted to the output pin VOUT, the power switch 10 turns on the electrical connection between the voltage output terminal VCC and the first resistor R1, and the power voltage (+ 12V) acts on the first switch Q1, so that the voltage between the gate and the source of the first switch Q1 satisfies the turn-on condition, and the first switch Q1 is turned on, thereby completing the control of the switch control circuit on the first switch Q1.

The switch control circuit 100 controls turning off of the first switch Q1:

referring to fig. 3, when at least one of the first control unit MCU and the second control unit AFE sends a low level signal to turn off the second switch Q2, since the enable pin EN of the power switch 10 is electrically connected to the ninth resistor R9 used as a pull-down resistor, the level of the enable pin EN is pulled down to a low level, and thus the ninth resistor R9 prevents the enable pin EN from being in a floating state.

As shown in fig. 5, since the level of the enable pin EN is a low level, after a low level signal passes through the logic control unit of the power switch 10, the first MOS transistor Q4 is turned off, and thus the electrical connection between the input pin VIN and the output pin VOUT of the power switch 10 is disconnected; the low level signal is inverted into a high level signal through the not gate F, so that the second MOS transistor Q5 is turned on, in addition, because the parasitic capacitor of the first MOS transistor Q4 stores charges, when the charges are discharged, the first MOS transistor Q4 is turned off, and therefore the charges stored in the parasitic capacitor of the first MOS transistor Q4 are discharged to the ground from the output pin VOUT through the seventh resistor R7, the output discharge pin QOD of the power switch 10, the turned-on second MOS transistor Q5, and the ground pin GND, so that the turn-off of the power switch 10 is realized, and therefore the turn-off speed of the power switch 10 can be adjusted by changing the resistance of the seventh resistor R7, and the smaller the resistance of the seventh resistor R7, the faster the turn-off speed of the power switch 10 is.

Referring to fig. 3 and 5, since each element and line in the peripheral circuit of the power switch 10 also have a certain parasitic capacitance, after the power switch 10 is turned off, the charges stored in the parasitic capacitance can be discharged to the ground through the first resistor R1, the seventh resistor R7, the output discharge pin QOD of the power switch 10, the conductive second MOS transistor Q5, and the ground pin GND. In the foregoing process, after the power switch 10 is turned off, the power switch 10 disconnects the electrical connection between the voltage output terminal VCC and the first resistor R1, in the turn-off process of the first switch Q1, specifically, when the first switch Q1 enters the turn-off state from the turn-on state, the charges stored in the parasitic capacitor inside the first switch Q1 are discharged to the ground through the second resistor R2, and simultaneously the charges are discharged to the ground through the first resistor R1, the seventh resistor R7, the output discharge pin QOD of the power switch 10, the turned-on second MOS transistor Q5, and the ground pin GND, after the charges are discharged, the turn-off of the first switch Q1 is realized, the turn-off speed of the first switch Q1 can be adjusted by changing the resistance of the seventh resistor R7, and the smaller the resistance of the seventh resistor R7 is, the faster the turn-off speed of the first switch Q1 is. Based on this, the switch control circuit completes the control of turning off the first switch Q1.

As can be seen from the above, the switch control circuit in the present application can achieve effective and flexible control over the turning on and off of the first switch Q1. It should be understood that the above-mentioned control process of the switch control circuit for turning on and off the first switch Q1 is only an example for easy understanding, and is not meant to limit the present application in any way.

It can be seen that, because the power switch exists in the switch control circuit of the embodiment of the present application, the power switch can respond to the control signal of the control module to form a voltage signal at the output pin. It can be understood that, the switching power supply may respond to the first control signal of the control module, so that the input pin and the output pin of the switching power supply are turned on to form a voltage signal for driving the first switch at the output pin, at this time, the voltage output terminal and the first resistor are turned on, and the voltage output terminal applies a voltage to the first switch through the output pin of the power supply switch, so that the first switch meets a turn-on condition to drive the first switch to be turned on; the switch power supply can respond to a second control signal of the control module, so that the input pin and the output pin of the switch power supply are disconnected, and the voltage output end is disconnected with the first switch through the power switch to achieve the turn-off of the first switch. Therefore, when the first switch is used for a discharging MOS (metal oxide semiconductor) tube of a battery pack discharging circuit, the power switch can be controlled through the control module so as to enable the first switch to be switched on or switched off.

In addition, because the power switch 10 in the embodiment of the present application has the output pin VOUT and the input pin VIN, the waste of the pin resources of the power switch 10 may not be caused on the premise of effectively controlling the first switch Q1, and in addition, when the switch control circuit of the present application is designed for PCB layout and wiring, the installation position of the power switch 10 may be designed in the vicinity of the first switch Q1 (for example, a discharge MOS transistor of a discharge circuit), so that the space for layout and wiring may be saved during PCB design, and the layout and wiring of other electronic components of the switch control circuit except the first switch Q1 and the power switch 10 may be more flexible, and because the line length between the first switch Q1 and the power switch 10 may be synchronously reduced during PCB layout and wiring, the charge leakage when the first switch Q1 is turned off may be realized more quickly, and the turn-off speed of the first switch Q1 is accelerated.

Referring to fig. 6, according to a second aspect of the present application, there is provided a battery management system 200 including: the switch control circuit 100 of any one of the aspects as provided in the first aspect.

Referring to fig. 7, according to a third aspect of the present application, a battery pack 300 is provided, wherein the battery pack 300 includes a battery module 310 and the battery management system 200 as provided in the second aspect.

Referring to fig. 8, according to a third aspect of the present application, there is provided an electric device 400, including: such as the battery pack 300 provided in the third aspect.

The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". It should be noted that the terms "first", "second", and the like in the present application are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence of the functions performed by the devices, modules or units. It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the present application. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present application.

Claims (11)

1. A switch control circuit, comprising: the circuit comprises a power switch (10), a control module (20), a first resistor (R1), a second resistor (R2) and a first switch (Q1);

the power switch (10) comprises an output pin (VOUT), an input pin (VIN) and an enable pin (EN), wherein the input pin (VIN) is used for being electrically connected with a voltage output end (VCC), the first resistor (R1) is electrically connected between the output pin (VOUT) and the first switch (Q1), and the second resistor (R2) is electrically connected between the first end of the first switch (Q1) and the second end of the first switch (Q1), is connected with the first resistor (R1) in series and is electrically connected between the output pin (VOUT) and the ground;

the control module (20) is electrically connected with the power switch (10) through the enable pin (EN), and the power switch (10) is configured to be capable of responding to a control signal of the control module (20) to form a voltage signal at the output pin (VOUT).

2. The switch control circuit of claim 1,

the control module (20) comprises: the power supply comprises a first control unit (MCU), a second switch (Q2), a third resistor (R3) and a fourth resistor (R4), wherein the first control unit (MCU) comprises a first signal terminal (21), the second switch (Q2) is electrically connected between the first signal terminal (21) and the power switch (10), the third resistor (R3) and the fourth resistor (R4) are connected between the first signal terminal (21) and the ground in series, and the third resistor (R3) is also electrically connected between a first end of the second switch (Q2) and a second end of the second switch (Q2);

alternatively, the first and second liquid crystal display panels may be,

the control module (20) comprises: the circuit comprises a second control unit (AFE), a third switch (Q3), a fifth resistor (R5) and a sixth resistor (R6), wherein the second control unit (AFE) comprises a second signal terminal (22), the third switch (Q3) is electrically connected between the second signal terminal (22) and the power switch (10), the fifth resistor (R5) and the sixth resistor (R6) are connected between the second signal terminal (22) and the ground in series, and the sixth resistor (R6) is further electrically connected between a first end of the third switch (Q3) and a second end of the third switch (Q3).

3. The switch control circuit of claim 1,

the control module (20) comprises: the power supply circuit comprises a first control unit (MCU), a second switch (Q2), a third resistor (R3) and a fourth resistor (R4), wherein the first control unit (MCU) comprises a first signal terminal (21), the second switch (Q2) is electrically connected between the first signal terminal (21) and the power switch (10), and the third resistor (R3) is electrically connected between a first end of the second switch (Q2) and a second end of the second switch (Q2);

and the number of the first and second groups,

the control module (20) comprises: a second control unit (AFE) including a second signal terminal (22), a third switch (Q3), a fifth resistor (R5), and a sixth resistor (R6), the fifth resistor (R5) and the sixth resistor (R6) being connected in series between the second signal terminal (22) and ground, the sixth resistor (R6) being further electrically connected between a first end of the third switch (Q3) and a second end of the third switch (Q3), the third switch (Q3) being electrically connected between the fourth resistor (R4) and the fifth resistor (R5), a first end of the fourth resistor (R4) being electrically connected to the third resistor (R3) and a first end of the second switch (Q2), respectively, a second end of the fourth resistor (R4) being electrically connected to the third switch (Q3).

4. The switch control circuit of claim 1,

the power switch (10) further comprises an output discharge pin (QOD);

the switch control circuit further comprises a seventh resistor (R7), and the seventh resistor (R7) is electrically connected between the output discharging pin (QOD) and the output pin (VOUT).

5. The switch control circuit of claim 1,

the power switch (10) further comprises a first pin (CT);

the switch control circuit further comprises a first capacitor (C1), and the first capacitor (C1) is electrically connected between the first pin (CT) and the ground.

6. The switch control circuit of claim 1,

the switch control circuit comprises a plurality of first switches (Q1) and a plurality of eighth resistors (R8);

the first switch (Q1) and the eighth resistor (R8) form a branch circuit, all the branch circuits are connected in parallel, and all the branch circuits are electrically connected between the first resistor (R1) and the ground.

7. The switch control circuit according to claim 1, further comprising a ninth resistor (R9), wherein a first end of the ninth resistor (R9) is electrically connected to the enable pin (EN), and a second end of the ninth resistor (R9) is grounded.

8. The switch control circuit of claim 1, further comprising: a first diode (D1), a second capacitor (C2) and a third capacitor (C3),

a first end of the second capacitor (C2) and a first end of the third capacitor (C3) are electrically connected and then electrically connected with the input pin (VIN), and a second end of the second capacitor (C2) and a second end of the third capacitor (C3) are electrically connected and then grounded;

the voltage output end (VCC) is electrically connected with the anode of the first diode (D1), and the cathode of the first diode (D1) is electrically connected with the first end of the second capacitor (C2).

9. A battery management system, comprising: the switch control circuit of any one of claims 1-8.

10. A battery pack, wherein the battery pack comprises a battery module and the battery management system of claim 9.

11. An electrical device, comprising: the battery pack according to claim 10.

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