CN218497400U - LDO voltage stabilizing circuit and electronic equipment - Google Patents
LDO voltage stabilizing circuit and electronic equipment Download PDFInfo
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- CN218497400U CN218497400U CN202223035423.6U CN202223035423U CN218497400U CN 218497400 U CN218497400 U CN 218497400U CN 202223035423 U CN202223035423 U CN 202223035423U CN 218497400 U CN218497400 U CN 218497400U
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Abstract
The utility model provides a LDO voltage stabilizing circuit and electronic equipment, wherein, LDO voltage stabilizing circuit includes power switch, reference circuit, feedback regulating circuit and fast recovery compensating circuit, when the output load does not change, LDO voltage stabilizing circuit output target output voltage promptly, this moment, the first compensating voltage of fast recovery compensating circuit output, first compensating voltage does not influence the target comparison voltage and the output voltage size of power switch's controlled end, when the output load changes, fast recovery compensating circuit output second compensating voltage, compensate the voltage of power switch's controlled end, make power switch's output voltage follow the voltage fast recovery of controlled end to target output voltage, guarantee rear end load circuit's operational reliability and security, and simultaneously, second compensating voltage follows abrupt change output voltage's size and corresponds the change, realize self-adaptation compensation and adjust, improve compensation compatibility and variety.
Description
Technical Field
The utility model belongs to the technical field of power electronics, especially, relate to a LDO voltage stabilizing circuit and electronic equipment.
Background
The LDO is a direct current linear voltage regulator with input voltage larger than output voltage, has the advantages of fast input and output response, low output noise, few external elements, convenient use, low price and the like, is widely applied to the fields of automobile electronic products, portable electronic equipment, communication equipment, industry and medical equipment, and the integration of LDO circuits is also an important development direction.
However, it is difficult to provide a large load capacitance in the conventional integrated LDO circuit, and as shown in fig. 1, when the output load changes, the LDO output voltage has a relatively obvious voltage increase or decrease change. When the LDO output voltage recovers slowly, it may cause the load circuit supplying power to malfunction or even fail.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a LDO voltage stabilizing circuit aims at solving the slow problem of output voltage recovery that traditional LDO voltage stabilizing circuit exists when the output load changes.
The utility model provides a first aspect provides an LDO voltage stabilizing circuit, include:
the input end and the output end of the power switch respectively form the input end and the output end of the LDO voltage stabilizing circuit, and the voltage of the output end and the voltage of the controlled end of the power switch are changed in a first preset change rule;
a reference circuit for outputting a reference voltage;
the feedback regulating circuit is connected with the power switch and the reference circuit respectively, and is used for sampling the voltage of the output end of the power switch, comparing the sampled voltage obtained by sampling with the reference voltage, and outputting a comparison voltage to the controlled end of the power switch so as to regulate the voltage of the output end of the power switch to reach a target output voltage in a feedback manner;
the fast recovery compensation circuit is connected with the power switch and is used for acquiring the voltage of the output end of the power switch so as to output a first compensation voltage to the controlled end of the power switch based on the target output voltage; and when the sudden change output voltage is obtained, the fast recovery compensation circuit outputs a second compensation voltage to the controlled end of the power switch based on the sudden change output voltage.
Optionally, the fast recovery compensation circuit comprises:
a first coupling circuit, a first end of which is connected to the output end of the power switch, the first coupling circuit being configured to couple and output a voltage at the output end of the power switch;
the input end of the bias circuit is connected with the second end of the first coupling circuit, and the bias circuit is used for biasing and outputting a first bias voltage when receiving the target output voltage; when the sudden change output voltage is received, the bias circuit biases to output a second bias voltage;
a first end of the compensation switch is connected with an input end of the power switch, a second end of the compensation switch is connected with a controlled end of the power switch, the controlled end of the compensation switch is connected with an output end of the bias circuit, and the compensation switch is used for outputting the first compensation voltage to the power switch when receiving the first bias voltage; and when the second bias voltage is received, the compensation switch outputs the second compensation voltage to the power switch.
Optionally, the first coupling circuit includes a first capacitor, and a first end and a second end of the first capacitor respectively form a first end and a second end of the first coupling circuit.
Optionally, the bias circuit comprises a first resistor and a second resistor;
the first end of the first resistor is connected with the input end of the power switch, the second end of the first resistor, the controlled end of the compensation switch, the second end of the first capacitor and the first end of the second resistor are connected in common, and the second end of the second resistor is grounded.
Optionally, the bias circuit comprises:
a first end of the current source is connected with the controlled end of the compensation switch, and a second end of the current source is grounded;
the first end of the first electronic switching tube is connected with the first end of the compensation switch, and the second end and the controlled end of the first electronic switching tube are connected with the first end of the current source;
the first electronic switch tube is a first PMOS tube or a first PNP triode, a source electrode of the first PMOS tube or an emitting electrode of the first PNP triode forms a first end of the first electronic switch tube, a grid electrode of the first PMOS tube or a base electrode of the first PNP triode forms a controlled end of the first electronic switch tube, and a drain electrode of the first PMOS tube or a collector electrode of the first PNP triode forms a second end of the first electronic switch tube.
Optionally, the compensation switch includes a second electronic switching tube, and the second electronic switching tube is a second PMOS tube or a second PNP triode;
the source electrode of the second PMOS tube or the emitting electrode of the second PNP triode forms the first end of the second electronic switch tube, the grid electrode of the second PMOS tube or the base electrode of the second PNP triode forms the controlled end of the second electronic switch tube, and the drain electrode of the second PMOS tube or the collector electrode of the second PNP triode forms the second end of the second electronic switch tube.
Optionally, the fast recovery compensation circuit comprises:
a first comparison circuit, an input end of which is connected to an output end of the power switch, the first comparison circuit being configured to compare a voltage at the output end of the power switch with a reference voltage, and to output the first compensation voltage when receiving the target output voltage, and to output the second compensation voltage when receiving the abrupt change output voltage;
and a first end of the second coupling circuit is connected with the output end of the first comparison circuit, a second end of the second coupling circuit is connected with the controlled end of the power switch, and the second coupling circuit is used for coupling and feeding back the first compensation voltage or the second compensation voltage to the power switch.
Optionally, the first comparison circuit comprises a first comparator;
the positive phase input end of the first comparator is used for inputting the reference voltage, the negative phase input end of the first comparator is connected with the output end of the power switch, and the output end of the first comparator is connected with the first end of the second coupling circuit.
Optionally, the second coupling circuit includes a second capacitor, and a first end and a second end of the second capacitor respectively form a first end and a second end of the second coupling circuit.
Optionally, the feedback adjustment circuit comprises:
the input end of the voltage sampling circuit is connected with the output end of the power switch, and the voltage sampling circuit is used for sampling the voltage of the output end of the power switch and outputting the sampled voltage;
and the second comparison circuit is used for comparing the sampling voltage with the reference voltage and outputting the comparison voltage to a controlled end of the power switch so as to feed back and regulate the voltage at the output end of the power switch to reach a target output voltage.
Optionally, the power switch includes an NMOS transistor or a third PMOS transistor;
the grid electrode of the NMOS tube or the grid electrode of the third PMOS tube forms a controlled end of the power switch;
the drain electrode of the NMOS tube or the source electrode of the third PMOS tube forms the input end of the power switch, and the source electrode of the NMOS tube or the drain electrode of the third PMOS tube forms the output end of the power switch.
Optionally, the second comparison circuit comprises a second comparator;
the positive phase input end of the second comparator is connected with the output end of the voltage sampling circuit, the negative phase input end of the second comparator is connected with the output end of the reference circuit, and the output end of the second comparator forms the output end of the second comparison circuit;
or the positive phase input end of the comparator is connected with the output end of the reference circuit, the negative phase input end of the second comparator is connected with the output end of the voltage sampling circuit, and the output end of the second comparator forms the output end of the second comparison circuit.
Optionally, the LDO voltage stabilizing circuit further includes:
and the compensation capacitor is connected with the power switch and is used for carrying out frequency compensation on the LDO voltage stabilizing circuit.
A second aspect of the embodiments of the present invention provides an electronic device, including an LDO voltage stabilizing circuit as described above.
Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: the LDO voltage stabilizing circuit is composed of a power switch, a reference circuit, a feedback regulating circuit and a fast recovery compensating circuit, when an output load is unchanged, namely the LDO voltage stabilizing circuit outputs a target output voltage, at the moment, the fast recovery compensating circuit outputs a first compensating voltage, the first compensating voltage does not influence the target comparison voltage and the output voltage of a controlled end of the power switch, when the output load is changed, the fast recovery compensating circuit outputs a second compensating voltage, the voltage of the controlled end of the power switch is compensated, the output voltage of the power switch is rapidly recovered to the target output voltage along with the voltage of the controlled end, the working reliability and safety of a rear-end load circuit are ensured, meanwhile, the second compensating voltage correspondingly changes along with the size of the abrupt change output voltage, self-adaptive compensation regulation is realized, and compensation compatibility and diversity are improved.
Drawings
FIG. 1 is a schematic diagram of an output waveform of a conventional LDO voltage regulator circuit;
fig. 2 is a schematic diagram of a first structure of an LDO voltage regulator circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a first output waveform of an LDO voltage regulator circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a second structure of an LDO voltage regulator circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a third structure of an LDO voltage stabilizing circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a fourth structure of an LDO voltage stabilizing circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a fifth structure of an LDO voltage stabilizing circuit according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a sixth structure of an LDO voltage stabilizing circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of a second output waveform of the LDO voltage stabilizing circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.
The utility model discloses the first aspect of the embodiment provides an LDO voltage stabilizing circuit for export stable operating voltage to rear end load circuit, as shown in FIG. 2, in this embodiment, LDO voltage stabilizing circuit includes:
the input end and the output end of the power switch 10 respectively form the input end and the output end of the LDO voltage stabilizing circuit, and the voltage of the output end and the voltage change of the controlled end of the power switch are changed in a first preset change rule;
a reference circuit 20, the reference circuit 20 being configured to output a reference voltage VREF1;
the feedback adjusting circuit 30 is respectively connected with the power switch 10 and the reference circuit 20, and the feedback adjusting circuit 30 is used for sampling the voltage of the output end of the power switch 10, comparing the sampled voltage with the reference voltage VREF1, and outputting the comparison voltage to the controlled end of the power switch 10 so as to feedback and adjust the voltage of the output end of the power switch 10 to reach the target output voltage;
the fast recovery compensation circuit 40 is connected to the power switch 10, and the fast recovery compensation circuit 40 is configured to obtain a voltage at an output end of the power switch 10 to output a first compensation voltage to a controlled end of the power switch 10 based on a target output voltage; and when the abrupt change output voltage is obtained, the fast recovery compensation circuit 40 outputs a second compensation voltage to the controlled end of the power switch 10 based on the abrupt change output voltage.
The first voltage difference value and the second voltage difference value are changed according to a second preset change rule, the first voltage difference value is a voltage difference value between the second compensation voltage and the first compensation voltage, the second voltage difference value is a voltage difference value between the sudden change output voltage and the target output voltage, and the first preset change rule and the second preset change rule are positive correlation change and negative correlation change.
In this embodiment, the input end of the power switch 10 is used for inputting a power supply, and the output voltage is adjusted according to the voltage received by the controlled end, the output end of the power switch 10 is also connected in parallel with a load capacitor CL, a first end of the load capacitor CL is connected with the output end of the power switch 10, and a second end of the load capacitor CL is grounded.
The reference circuit 20 provides a reference voltage VREF1 to the feedback regulating circuit 30, and the feedback regulating circuit 30 performs feedback regulation according to the magnitude of the output voltage of the power switch 10, compares the sampling voltage sampled from the output terminal of the power switch 10 with the reference circuit 20, and outputs a comparison voltage to the controlled terminal of the power switch 10, so that the output voltage of the power switch 10 is stabilized at a target output voltage, and correspondingly, the voltage of the controlled terminal of the power switch 10 is stabilized at the target comparison voltage.
For example, assuming that the first preset variation rule is positive correlation variation, that is, the output voltage of the power switch 10 and the voltage of the controlled terminal are positive correlation variation, for example, when the power switch is an NMOS transistor, the voltage of the controlled terminal and the voltage of the output terminal are positive correlation variation, the feedback adjustment circuit 30 may perform negative feedback adjustment based on the output voltage of the NMOS transistor, when the output voltage of the NMOS transistor becomes larger, the sampling voltage becomes larger, the difference between the reference voltage VREF1 and the sampling voltage becomes smaller, that is, the comparison voltage becomes smaller, and the output voltage of the NMOS transistor becomes smaller, whereas when the output voltage of the NMOS transistor becomes smaller, the sampling voltage becomes smaller, the difference between the reference voltage VREF1 and the sampling voltage becomes larger, that is, the comparison voltage becomes larger, and the output voltage of the NMOS transistor becomes larger, and the output voltage of the power switch 10 is gradually stabilized to the target output voltage through negative feedback adjustment.
Or, assuming that the first preset variation rule is negative correlation variation, that is, the output voltage of the power switch 10 and the voltage of the controlled terminal are negative correlation variation, for example, when the power switch is a PMOS transistor, the controlled terminal voltage and the voltage of the output terminal are negative correlation variation and are in nonlinear variation, the feedback adjusting circuit 30 may perform positive feedback adjustment based on the output voltage of the PMOS transistor, when the output voltage of the PMOS transistor becomes larger, the sampling voltage becomes larger, the difference between the sampling voltage and the reference voltage VREF1 becomes larger, that is, the comparison voltage becomes larger, and the output voltage of the PMOS transistor becomes smaller, whereas when the output voltage of the PMOS transistor becomes smaller, the sampling voltage becomes smaller, the difference between the sampling voltage and the reference voltage VREF1 becomes smaller, that is, the comparison voltage becomes smaller, the output voltage of the PMOS transistor becomes larger, and through the positive feedback adjustment, the output voltage of the power switch 10 gradually stabilizes to the target output voltage.
The specific positive and negative feedback adjustment manner and structure of the feedback adjustment circuit 30 may be designed correspondingly according to the type of the power switch 10, that is, when the voltage of the output end of the power switch 10 changes in a positive correlation with the voltage of the controlled end, the feedback adjustment circuit 30 performs negative feedback adjustment, and when the voltage of the output end of the power switch 10 changes in a negative correlation with the voltage of the controlled end, the feedback adjustment circuit 30 performs positive feedback adjustment.
As shown in the output waveform diagram of the LDO voltage regulator of fig. 3, when the LDO voltage regulator is outputting stably, the fast recovery compensation circuit 40 outputs a first compensation voltage to the controlled terminal of the power switch 10, wherein the sum of the first compensation voltage and the comparison voltage is equal to the target comparison voltage, the output voltage of the power switch 10 is still stabilized within the range of the target output voltage, the first compensation voltage is close to or equal to 0V, and the first compensation voltage does not affect the normal feedback regulation output of the LDO voltage regulator during voltage regulation output.
When the load current of the LDO voltage regulator circuit suddenly changes, the output voltage of the power switch 10 drops or rises to a sudden change output voltage, for example, the sudden change output voltage drops from the target output voltage 5V to 3V, at this time, the feedback regulating circuit 30 itself feedback regulates the magnitude of the comparison voltage output to the power switch 10 according to the output voltage of the power switch 10, meanwhile, the fast recovery compensating circuit 40 outputs a second compensation voltage to the controlled end of the power switch 10 based on the sudden change output voltage, and the total voltage of the second compensation voltage and the comparison voltage is output to the controlled end of the power switch 10, so that the output voltage of the power switch 10 quickly recovers to the target output voltage, and the working reliability and safety of the rear-end load circuit are ensured.
For example, if the voltage of the controlled terminal of the power switch 10 and the voltage of the output terminal are in positive correlation change, the first voltage difference and the second voltage difference are in negative correlation change, the first voltage difference is the voltage difference between the second compensation voltage and the first compensation voltage, and the second voltage difference is the voltage difference between the abrupt change output voltage and the target output voltage.
When the load current of the LDO voltage regulator circuit suddenly changes, the output voltage of the power switch 10 drops to a sudden change output voltage, at this time, the feedback regulator circuit 30 itself negatively feeds back the magnitude of the comparison voltage output to the power switch 10 according to the output voltage of the power switch 10, and at the same time, the fast recovery compensator circuit 40 triggers to output the second compensation voltage to the controlled end of the power switch 10, and the difference between the second compensation voltage and the first compensation voltage rises, and the sum of the voltages received at the controlled end of the power switch 10 rapidly increases, and the output voltage of the power switch 10 rapidly rises and recovers to the target output voltage, whereas, when the output voltage of the power switch 10 rises, the feedback regulator circuit 30 itself decreases the magnitude of the comparison voltage output to the power switch 10 according to the negative feedback of the output voltage of the power switch 10, and at the same time, the fast recovery compensator circuit 40 triggers to output the second compensation voltage to the controlled end of the power switch 10, and the difference between the second compensation voltage and the first compensation voltage drops, and the sum of the voltage received at the controlled end of the power switch 10 rapidly decreases, and the output voltage of the power switch 10 rapidly drops and recovers to the target output voltage.
Alternatively, if the voltage of the controlled terminal of the power switch 10 and the voltage of the output terminal are in negative correlation, the first voltage difference and the second voltage difference are in positive correlation.
That is, when the output voltage of the power switch 10 drops to the abrupt output voltage, the feedback adjusting circuit 30 itself drops the magnitude of the comparison voltage output to the power switch 10 according to the positive feedback of the output voltage of the power switch 10, and at the same time, the fast recovery compensating circuit 40 triggers to output the second compensation voltage to the controlled terminal of the power switch 10, the difference between the second compensation voltage and the first compensation voltage drops, the sum of the voltages received by the controlled terminal of the power switch 10 decreases rapidly, and the output voltage of the power switch 10 rises rapidly to recover to the target output voltage, whereas when the output voltage of the power switch 10 rises, the feedback adjusting circuit 30 itself increases the magnitude of the comparison voltage output to the power switch 10 according to the positive feedback of the output voltage of the power switch 10, and at the same time, the fast recovery compensating circuit 40 triggers to output the second compensation voltage to the controlled terminal of the power switch 10, and the difference between the second compensation voltage and the first compensation voltage rises rapidly, and the sum of the voltages received by the controlled terminal of the power switch 10 increases, and the output voltage of the power switch 10 drops rapidly to recover to the target output voltage.
The fast recovery compensation circuit 40 may be implemented by using a corresponding compensation switch, a feedback circuit, and the like, and the specific structure is not limited.
The power switch 10 may select a corresponding power switch tube, optionally, the power switch 10 includes a third electronic switch tube Q3, and the third electronic switch tube Q3 is an NMOS tube or a third PMOS tube;
the grid electrode of the NMOS tube or the grid electrode of the third PMOS tube forms a controlled end of the power switch 10;
the drain of the NMOS transistor or the source of the third PMOS transistor forms the input terminal of the power switch 10, and the source of the NMOS transistor or the drain of the third PMOS transistor forms the output terminal of the power switch 10.
In this embodiment, when the power switch 10 is an NMOS transistor, the controlled terminal voltage thereof changes in positive correlation with the voltage of the output terminal, at this time, corresponding to the type of the power switch 10, the feedback adjusting circuit 30 is in a negative feedback adjustment mode, that is, when the output voltage of the power switch 10 becomes larger, the sampling voltage becomes larger, the difference between the reference voltage VREF1 and the sampling voltage becomes smaller, that is, the comparison voltage becomes smaller, and the output voltage of the power switch 10 becomes smaller, whereas, when the output voltage of the power switch 10 becomes smaller, the sampling voltage becomes smaller, the difference between the reference voltage VREF1 and the sampling voltage becomes larger, that is, the comparison voltage becomes larger, the output voltage of the power switch 10 becomes larger, and the output voltage of the power switch 10 is gradually stabilized to the target output voltage through negative feedback adjustment.
Or, when the power switch 10 is a PMOS transistor, the controlled terminal voltage and the voltage at the output terminal thereof are in negative correlation change and are in nonlinear change, at this time, corresponding to the type of the power switch 10, the feedback adjusting circuit 30 is in a positive feedback adjusting mode, and adjusts the voltage at the controlled terminal of the power switch 10 in a positive direction according to the output voltage of the power switch 10, so as to recover and stabilize the output voltage of the power switch 10 to the target output voltage, that is, when the output voltage of the power switch 10 becomes larger, the sampling voltage becomes larger, the difference between the sampling voltage and the reference voltage VREF1 becomes larger, that is, the comparison voltage becomes larger, and the output voltage of the power switch 10 becomes smaller, whereas when the output voltage of the power switch 10 becomes smaller, the sampling voltage becomes smaller, the difference between the sampling voltage and the reference voltage VREF1 becomes smaller, that is, the output voltage of the power switch 10 becomes larger, and the output voltage of the power switch 10 is gradually stabilized to the target output voltage through positive feedback adjustment.
Further, as shown in fig. 5, the LDO voltage regulator circuit further includes:
and the compensation capacitor Cc is connected with the power switch 10 and used for performing frequency compensation on the LDO voltage stabilizing circuit, so that the interval of the primary and secondary poles is far, and the phase margin of the LDO voltage stabilizing circuit is further ensured.
The feedback adjusting circuit 30 selects a corresponding configuration corresponding to different types of load switches, as shown in fig. 4, and optionally, the feedback adjusting circuit 30 includes:
the voltage sampling circuit 31 is provided with an input end connected with the output end of the power switch 10, and the voltage sampling circuit 31 is used for sampling the voltage at the output end of the power switch 10 and outputting the sampled voltage;
and the second comparison circuit 32 is connected to the reference circuit 20 and the voltage sampling circuit 31, and the second comparison circuit 32 is configured to compare the sampled voltage with the reference voltage VREF1 and output the comparison voltage to the controlled terminal of the power switch 10, so as to feedback and regulate the voltage at the output terminal of the power switch 10 to reach the target output voltage.
In this embodiment, the second comparing circuit 32 correspondingly adjusts the input channels of the input sampling voltage and the reference voltage VREF1 according to the switch type of the power switch 10, and performs different voltage comparisons.
For example, when the power switch 10 is an NMOS transistor, the controlled terminal voltage thereof changes in positive correlation with the voltage of the output terminal, and at this time, corresponding to the type of the power switch 10, the second comparison circuit 32 is a negative feedback adjustment manner, and compares the reference voltage VREF1 with the sampling voltage, that is, when the output voltage of the power switch 10 increases, the sampling voltage increases, the difference between the reference voltage VREF1 and the sampling voltage decreases, that is, the comparison voltage decreases, and the output voltage of the power switch 10 decreases, whereas when the output voltage of the power switch 10 decreases, the sampling voltage decreases, the difference between the reference voltage VREF1 and the sampling voltage increases, that is, the comparison voltage increases, and the output voltage of the power switch 10 is gradually stabilized to the target output voltage through negative feedback adjustment.
Meanwhile, when the power switch 10 is a PMOS transistor, the controlled terminal voltage and the voltage of the output terminal thereof are in negative correlation change and are in nonlinear change, at this time, corresponding to the type of the power switch 10, the second comparison circuit 32 is a positive feedback adjustment circuit 30, the voltage of the controlled terminal of the power switch 10 is adjusted in the positive direction according to the output voltage of the power switch 10, and the difference value of the sampling voltage and the reference voltage VREF1 is compared, so that the output voltage of the power switch 10 is recovered and stabilized to the target output voltage, that is, when the output voltage of the power switch 10 is increased, the sampling voltage is increased, the difference value of the sampling voltage and the reference voltage VREF1 is increased, that is, the comparison voltage is increased, and the output voltage of the power switch 10 is decreased, whereas when the output voltage of the power switch 10 is decreased, the sampling voltage is decreased, that is, the comparison voltage is decreased, that is, the output voltage of the power switch 10 is increased, and through positive feedback adjustment, the output voltage of the power switch 10 is gradually stabilized to the target output voltage.
The voltage sampling circuit 31 may select a voltage-dividing resistor, a voltage follower, and the like, optionally, as shown in fig. 5, optionally, the voltage sampling circuit 31 includes a first voltage-dividing resistor Rfb1 and a second voltage-dividing resistor Rfb2, a first end of the first voltage-dividing resistor Rfb1 is connected to the output end of the power switch 10, a second end of the first voltage-dividing resistor Rfb1 and a first end of the second voltage-dividing resistor Rfb2 are connected in common to form a signal output end of the voltage sampling circuit 31, and a second end of the second voltage-dividing resistor Rfb2 is grounded.
The second comparison circuit 32 includes a second comparator U2;
the non-inverting input end of the second comparator U2 is connected to the output end of the voltage sampling circuit 31, the inverting input end of the second comparator U2 is connected to the output end of the reference circuit 20, and the output end of the second comparator U2 constitutes the output end of the second comparison circuit 32;
alternatively, the non-inverting input terminal of the comparator is connected to the output terminal of the reference circuit 20, the inverting input terminal of the second comparator U2 is connected to the output terminal of the voltage sampling circuit 31, and the output terminal of the second comparator U2 constitutes the output terminal of the second comparison circuit 32.
In this embodiment, when the non-inverting input terminal of the second comparator U2 is connected to the output terminal of the voltage sampling circuit 31 and the inverting input terminal of the second comparator U2 is connected to the output terminal of the reference circuit 20, the second comparator U2 and the voltage sampling circuit 31 form the positive feedback adjusting circuit 30, and the correspondingly driven power switch 10 is a PMOS transistor.
And when the inverting input end of the second comparator U2 is connected to the output end of the voltage sampling circuit 31 and the non-inverting input end of the second comparator U2 is connected to the output end of the reference circuit 20, the second comparator U2 and the voltage sampling circuit 31 form a negative feedback regulating circuit 30, and the correspondingly driven power switch 10 is an NMOS transistor.
Compared with the prior art, the embodiment of the utility model beneficial effect who exists is: the LDO voltage stabilizing circuit is composed of a power switch 10, a reference circuit 20, a feedback regulating circuit 30 and a fast recovery compensating circuit 40, when an output load is not changed, namely the LDO voltage stabilizing circuit outputs a target output voltage, at the moment, the fast recovery compensating circuit 40 outputs a first compensating voltage, the first compensating voltage does not affect the target comparison voltage and the output voltage of a controlled end of the power switch 10, when the output load is changed, the fast recovery compensating circuit 40 outputs a second compensating voltage to compensate the voltage of the controlled end of the power switch 10, so that the output voltage of the power switch 10 is quickly recovered to the target output voltage along with the voltage of the controlled end, the working reliability and the safety of a rear-end load circuit are ensured, meanwhile, the second compensating voltage correspondingly changes along with the size of the abrupt change output voltage, self-adaptive compensation regulation is realized, and compensation compatibility and diversity are improved.
In an alternative embodiment, as shown in fig. 4, the fast recovery compensation circuit 40 includes:
a first coupling circuit 41, a first end of which is connected to the output end of the power switch 10, the first coupling circuit 41 being configured to couple and output a voltage at the output end of the power switch 10;
a bias circuit 42, an input end of which is connected to the second end of the first coupling circuit 41, the bias circuit 42 being configured to bias output a first bias voltage when receiving the target output voltage and bias output a second bias voltage when receiving the abrupt change output voltage;
a first terminal of the compensation switch 43 is connected to the input terminal of the power switch 10, a second terminal of the compensation switch 43 is connected to the controlled terminal of the power switch 10, the controlled terminal of the compensation switch 43 is connected to the output terminal of the bias circuit 42, and the compensation switch 43 is configured to output a first compensation voltage to the power switch 10 when receiving a first bias voltage, and output a second compensation voltage to the power switch 10 when receiving a second bias voltage.
In this embodiment, when the LDO regulator circuit outputs normally, the first coupling circuit 41 feeds back the target output voltage to the bias circuit 42, the bias circuit 42 outputs a first bias voltage to the compensation switch 43 in a biased manner, the compensation switch 43 triggers and outputs the first compensation voltage to the controlled end of the power switch 10, the sum of the first compensation voltage and the comparison voltage output by the feedback regulator circuit 30 in a steady state is equal to the target comparison voltage, the output voltage of the power switch 10 is still stable within the range of the target output voltage, the first compensation voltage is close to or equal to 0V, and when the LDO regulator circuit outputs in a regulated manner, the first compensation voltage output by the compensation switch 43 does not affect the normal feedback regulation output of the LDO regulator circuit.
When the load current of the LDO voltage regulator circuit suddenly changes, the output voltage of the power switch 10 drops or rises to a sudden change output voltage, at this time, the first coupling circuit 41 feeds back the sudden change output voltage to the bias circuit 42, the bias circuit 42 outputs the second bias voltage to the compensation switch 43, the compensation switch 43 triggers and outputs the second compensation voltage to the controlled end of the power switch 10, and meanwhile, the feedback regulator circuit 30 feeds back and regulates the magnitude of the comparison voltage output to the power switch 10 according to the output voltage of the power switch 10, and the total voltage of the second compensation voltage and the comparison voltage is output to the controlled end of the power switch 10, so that the output voltage of the power switch 10 is quickly recovered to the target output voltage, and the working reliability and safety of the rear end load circuit are ensured.
The third voltage difference value of the second bias voltage and the first bias voltage changes correspondingly along with the change of the output voltage of the power switch 10 tube, the bias voltage and the compensation voltage are in a mapping relation, the compensation voltage changes along with the change of the bias voltage, and can be positive correlation change or negative correlation change, and the specific change rule is not limited.
The first coupling circuit 41 may adopt a structure such as a voltage follower and a voltage sampling circuit 31, the bias circuit 42 may adopt a structure such as a bias resistor and a capacitor, and the compensation switch 43 may select a corresponding switch tube structure.
In an alternative embodiment, as shown in fig. 5, the first coupling circuit 41 includes a first capacitor C1, a first terminal and a second terminal of which respectively form a first terminal and a second terminal of the first coupling circuit 41.
The bias circuit 42 includes a first resistor R1 and a second resistor R2;
the first end of the first resistor R1 is connected to the input end of the power switch 10, the second end of the first resistor R1, the controlled end of the compensation switch 43, the second end of the first capacitor C1 and the first end of the second resistor R2 are connected in common, and the second end of the second resistor R2 is grounded.
The compensation switch 43 includes a second electronic switch Q2, and the second electronic switch Q2 is a second PMOS transistor or a second PNP triode;
the source electrode of the second PMOS transistor or the emitter electrode of the second PNP triode forms the first end of the second electronic switch transistor Q2, the gate electrode of the second PMOS transistor or the base electrode of the second PNP triode forms the controlled end of the second electronic switch transistor Q2, and the drain electrode of the second PMOS transistor or the collector electrode of the second PNP triode forms the second end of the second electronic switch transistor Q2.
In this embodiment, the first resistor R1 and the second resistor R2 serve as bias resistors, and when the LDO voltage regulator circuit is outputting stably, the first resistor R1 and the second resistor R2 bias the second electronic switch Q2 in a sub-threshold region, which only provides a very small current, and does not affect the output of the power switch 10, that is, does not affect the normal operation of the main body of the LDO voltage regulator circuit.
When the load current suddenly rises, the output voltage of the LDO voltage stabilizing circuit drops, the voltage drop is coupled to the controlled end of the second electronic switch tube Q2 through the first capacitor C1, the current of the second electronic switch tube Q2 is increased, the voltage of the controlled end of the power switch 10 is raised to increase the current of the power switch 10, and the recovery of the output voltage is accelerated.
When the output voltage is recovered, the voltage of the controlled terminal of the second electronic switching tube Q2 is recovered to the dc value determined by the first resistor and the second resistor, and the abrupt change compensation operation of the fast recovery compensation circuit 40 is completed.
In another alternative embodiment, as shown in fig. 6, the first coupling circuit 41 comprises a first capacitor C1, the first terminal and the second terminal of which constitute the first terminal and the second terminal of the first coupling circuit 41, respectively.
The bias circuit 42 includes:
a current source I1, a first end of which is connected to the controlled end of the compensation switch 43, and a second end of which is grounded;
a first end of the first electronic switching tube Q1 is connected with a first end of the compensation switch 43, and a second end and a controlled end of the first electronic switching tube Q1 are connected with a first end of the current source I1;
the first electronic switch tube Q1 is a first PMOS tube or a first PNP triode, a source electrode of the first PMOS tube or an emitting electrode of the first PNP triode forms a first end of the first electronic switch tube Q1, a gate electrode of the first PMOS tube or a base electrode of the first PNP triode forms a controlled end of the first electronic switch tube Q1, and a drain electrode of the first PMOS tube or a collector electrode of the first PNP triode forms a second end of the first electronic switch tube Q1.
The compensation switch 43 includes a second electronic switch Q2, and the second electronic switch Q2 is a second PMOS transistor or a second PNP triode;
the source electrode of the second PMOS transistor or the emitter electrode of the second PNP triode forms the first end of the second electronic switch Q2, the gate electrode of the second PMOS transistor or the base electrode of the second PNP triode forms the controlled end of the second electronic switch Q2, and the drain electrode of the second PMOS transistor or the collector electrode of the second PNP triode forms the second end of the second electronic switch Q2.
In this embodiment, the current source I1 and the first electronic switching tube Q1 form the bias circuit 42, and when the LDO voltage regulator circuit is outputting stably, the current source I1 and the first electronic switching tube Q1 bias the second electronic switching tube Q2 in the sub-threshold region, which only provides a very small current and does not affect the output of the power switch 10, i.e., does not affect the normal operation of the LDO voltage regulator circuit main body.
When the load current suddenly rises, the output voltage of the LDO voltage stabilizing circuit drops, the voltage drop is coupled to the controlled end of the second electronic switch tube Q2 through the first capacitor C1, the current of the second electronic switch tube Q2 is increased, the voltage of the controlled end of the power switch 10 is raised to increase the current of the power switch 10, and the recovery of the output voltage is accelerated.
When the output voltage is recovered, the voltage of the controlled terminal of the second electronic switching tube Q2 is recovered to the dc value determined by the first resistor and the second resistor, and the abrupt change compensation operation of the fast recovery compensation circuit 40 is completed.
The current source I1, the first electronic switching tube Q1 and the second electronic switching tube Q2 form a current mirror circuit, and the second electronic switching tube Q2 outputs a current with a corresponding magnitude to the power switch 10 according to the circulating current proportion of the first electronic switching tube Q1 to change the voltage of the controlled end of the power switch 10, so that the compensation switch 43 needs to be a PMOS or PNP triode corresponding to the first electronic switching tube Q1.
In another alternative embodiment, as shown in fig. 7, the fast recovery compensation circuit 40 optionally includes:
a first comparison circuit 44 having an input terminal connected to the output terminal of the power switch 10, the first comparison circuit 44 being configured to compare the voltage at the output terminal of the power switch 10 with a reference voltage VREF2, and to output a first compensation voltage when receiving a target output voltage and output a second compensation voltage when receiving an abrupt change output voltage;
a first end of the second coupling circuit 45 is connected to the output end of the first comparing circuit 44, a second end of the second coupling circuit 45 is connected to the controlled end of the power switch 10, and the second coupling circuit 45 is configured to couple and feed back the first compensation voltage or the second compensation voltage to the power switch 10.
In this embodiment, when the LDO regulator circuit outputs normally, the first comparison circuit 44 compares the target output voltage with the reference voltage VREF2, and outputs a first compensation voltage to the second coupling circuit 45, and the second coupling circuit 45 couples and feeds back the target compensation voltage to the controlled end of the power switch 10, the sum of the first compensation voltage and the comparison voltage output by the feedback regulator circuit 30 in a steady state is equal to the target compensation voltage, the output voltage of the power switch 10 is still stabilized within the range of the target output voltage, the first compensation voltage is equal to 0V, and when the voltage is output stably, the first compensation voltage output by the second coupling circuit 45 does not affect the normal feedback regulation output of the LDO regulator circuit.
When the load current of the LDO voltage regulator circuit suddenly changes, the output voltage of the power switch 10 drops or rises to a sudden change output voltage, at this time, the first comparison circuit 44 compares the sudden change output voltage with the reference voltage VREF2, and outputs the second compensation voltage to the controlled end of the power switch 10, and meanwhile, the feedback regulation circuit 30 performs feedback regulation on the magnitude of the comparison voltage output to the power switch 10 according to the output voltage of the power switch 10, and the total voltage of the second compensation voltage and the comparison voltage is output to the controlled end of the power switch 10, so that the output voltage of the power switch 10 is quickly recovered to the target output voltage, and the working reliability and safety of the rear-end load circuit are ensured.
The first comparison circuit 44 may select a corresponding comparator, an inverter designed with a predetermined threshold voltage, and the like to implement a voltage comparison function, and the second coupling circuit 45 may select a corresponding voltage follower, the voltage sampling circuit 31, a coupling capacitor, and the like to implement a voltage coupling function.
As shown in fig. 8, in an alternative embodiment, to simplify the circuit configuration, the first comparison circuit 44 includes a first comparator U1;
the non-inverting input terminal of the first comparator U1 is used for inputting the reference voltage VREF2, the inverting input terminal of the first comparator U1 is connected to the output terminal of the power switch 10, and the output terminal of the first comparator U1 is connected to the first terminal of the second coupling circuit 45.
The second coupling circuit 45 comprises a second capacitor C2, the first and second terminals of which constitute the first and second terminals of the second coupling circuit 45, respectively.
In this embodiment, the first comparator U1 does not affect the power transistor when the LDO operates stably, that is, the first compensation voltage for comparison output is 0V, when the load current increases suddenly and the output voltage of the LDO becomes low, the first comparator U1 detects that the output voltage is lower than the reference voltage VREF2, the output of the first comparator U1 changes from low to high, as shown in fig. 9, the signal is coupled to the controlled end of the power switch 10 through the second capacitor C2, so as to increase the transient current of the power switch 10 and accelerate the stability of the output voltage of the LDO voltage stabilizing circuit. The first comparator U1 should be designed to take into account the larger bandwidth due to the need to provide faster response speed.
The utility model discloses still provide an electronic equipment, this electronic equipment include LDO voltage stabilizing circuit, and this LDO voltage stabilizing circuit's concrete structure refers to above-mentioned embodiment, because this electronic equipment has adopted the whole technical scheme of above-mentioned all embodiments, consequently has all beneficial effects that the technical scheme of above-mentioned embodiment brought at least, no longer gives unnecessary detail here.
The electronic equipment can be automobile electronic products, portable electronic equipment, communication equipment, industrial and medical equipment and the like, the specific type is not limited, and the working voltage of the corresponding load circuit in the electronic equipment is maintained in a stable state by arranging the LDO voltage stabilizing circuit, so that the safety and the reliability of the corresponding load circuit are improved.
The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (14)
1. An LDO voltage regulator circuit, comprising:
the input end and the output end of the power switch respectively form the input end and the output end of the LDO voltage stabilizing circuit, and the voltage of the output end and the voltage of the controlled end of the power switch are changed according to a first preset change rule;
a reference circuit for outputting a reference voltage;
the feedback regulating circuit is connected with the power switch and the reference circuit respectively, and is used for sampling the voltage of the output end of the power switch, comparing the sampled voltage obtained by sampling with the reference voltage, and outputting a comparison voltage to the controlled end of the power switch so as to regulate the voltage of the output end of the power switch to reach a target output voltage in a feedback manner;
the fast recovery compensation circuit is connected with the power switch and used for acquiring the voltage of the output end of the power switch so as to output a first compensation voltage to the controlled end of the power switch based on the target output voltage; and when the sudden change output voltage is obtained, the fast recovery compensation circuit outputs a second compensation voltage to the controlled end of the power switch based on the sudden change output voltage.
2. The LDO voltage regulator circuit of claim 1, wherein the fast recovery compensation circuit comprises:
a first coupling circuit, a first end of which is connected to the output end of the power switch, the first coupling circuit being configured to couple and output a voltage at the output end of the power switch;
the input end of the bias circuit is connected with the second end of the first coupling circuit, and the bias circuit is used for biasing and outputting a first bias voltage when receiving the target output voltage; when the sudden change output voltage is received, the bias circuit biases to output a second bias voltage;
a first end of the compensation switch is connected with an input end of the power switch, a second end of the compensation switch is connected with a controlled end of the power switch, the controlled end of the compensation switch is connected with an output end of the bias circuit, and the compensation switch is used for outputting the first compensation voltage to the power switch when receiving the first bias voltage; and when the second bias voltage is received, the compensation switch outputs the second compensation voltage to the power switch.
3. The LDO voltage regulator circuit of claim 2, wherein the first coupling circuit comprises a first capacitor having first and second terminals that form first and second terminals, respectively, of the first coupling circuit.
4. The LDO voltage regulator circuit of claim 3, wherein the bias circuit comprises a first resistor and a second resistor;
the first end of the first resistor is connected with the input end of the power switch, the second end of the first resistor, the controlled end of the compensation switch, the second end of the first capacitor and the first end of the second resistor are connected in common, and the second end of the second resistor is grounded.
5. The LDO voltage regulator circuit of claim 3, wherein the bias circuit comprises:
a first end of the current source is connected with the controlled end of the compensation switch, and a second end of the current source is grounded;
the first end of the first electronic switching tube is connected with the first end of the compensation switch, and the second end and the controlled end of the first electronic switching tube are connected with the first end of the current source;
the first electronic switch tube is a first PMOS tube or a first PNP triode, a source electrode of the first PMOS tube or an emitting electrode of the first PNP triode forms a first end of the first electronic switch tube, a grid electrode of the first PMOS tube or a base electrode of the first PNP triode forms a controlled end of the first electronic switch tube, and a drain electrode of the first PMOS tube or a collector electrode of the first PNP triode forms a second end of the first electronic switch tube.
6. The LDO voltage regulator circuit of claim 2, wherein the compensation switch comprises a second electronic switch transistor, the second electronic switch transistor being either a second PMOS transistor or a second PNP transistor;
the source electrode of the second PMOS tube or the emitting electrode of the second PNP triode forms the first end of the second electronic switch tube, the grid electrode of the second PMOS tube or the base electrode of the second PNP triode forms the controlled end of the second electronic switch tube, and the drain electrode of the second PMOS tube or the collector electrode of the second PNP triode forms the second end of the second electronic switch tube.
7. The LDO voltage regulator circuit of claim 1, wherein the fast recovery compensation circuit comprises:
a first comparison circuit, an input end of which is connected to an output end of the power switch, the first comparison circuit being configured to compare a voltage at the output end of the power switch with a reference voltage, and to output the first compensation voltage when receiving the target output voltage, and to output the second compensation voltage when receiving the abrupt change output voltage;
and a first end of the second coupling circuit is connected with the output end of the first comparison circuit, a second end of the second coupling circuit is connected with the controlled end of the power switch, and the second coupling circuit is used for coupling and feeding back the first compensation voltage or the second compensation voltage to the power switch.
8. The LDO voltage regulator circuit of claim 7, wherein the first comparison circuit comprises a first comparator;
the positive phase input end of the first comparator is used for inputting the reference voltage, the negative phase input end of the first comparator is connected with the output end of the power switch, and the output end of the first comparator is connected with the first end of the second coupling circuit.
9. The LDO voltage regulator circuit of claim 7, wherein the second coupling circuit comprises a second capacitor having first and second terminals that form first and second terminals, respectively, of the second coupling circuit.
10. The LDO voltage regulator circuit of any of claims 1 through 9, wherein the feedback regulation circuit comprises:
the input end of the voltage sampling circuit is connected with the output end of the power switch, and the voltage sampling circuit is used for sampling the voltage of the output end of the power switch and outputting the sampled voltage;
and the second comparison circuit is used for comparing the sampling voltage with the reference voltage and outputting the comparison voltage to a controlled end of the power switch so as to feed back and regulate the voltage at the output end of the power switch to reach the target output voltage.
11. The LDO voltage regulator circuit of claim 10, wherein the power switch comprises an NMOS transistor or a third PMOS transistor;
the grid electrode of the NMOS tube or the grid electrode of the third PMOS tube forms a controlled end of the power switch;
the drain electrode of the NMOS tube or the source electrode of the third PMOS tube forms the input end of the power switch, and the source electrode of the NMOS tube or the drain electrode of the third PMOS tube forms the output end of the power switch.
12. The LDO voltage regulator circuit of claim 11, wherein the second comparison circuit comprises a second comparator;
the positive phase input end of the second comparator is connected with the output end of the voltage sampling circuit, the negative phase input end of the second comparator is connected with the output end of the reference circuit, and the output end of the second comparator forms the output end of the second comparison circuit;
or the positive phase input end of the comparator is connected with the output end of the reference circuit, the negative phase input end of the second comparator is connected with the output end of the voltage sampling circuit, and the output end of the second comparator forms the output end of the second comparison circuit.
13. The LDO voltage regulator circuit of claim 1, further comprising:
and the compensation capacitor is connected with the power switch and is used for carrying out frequency compensation on the LDO voltage stabilizing circuit.
14. An electronic device comprising the LDO voltage regulator circuit according to any of claims 1 to 13.
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| CN202223035423.6U CN218497400U (en) | 2022-11-15 | 2022-11-15 | LDO voltage stabilizing circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202223035423.6U CN218497400U (en) | 2022-11-15 | 2022-11-15 | LDO voltage stabilizing circuit and electronic equipment |
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