CN218473215U - PAL input circuit and video processing apparatus including the same - Google Patents

Abstract

The utility model relates to a PAL input circuit reaches video processing apparatus including this PAL input circuit, PAL input circuit changes single-ended unit and video decoding unit including the difference that electric links together, and the difference changes single-ended chip and includes input pin + IN, input pin-IN, output pin OUT, and the video decoding chip includes analog video input pin AIP1A, video output pin YOUT0 to YOUT7, and the difference changes single-ended chip's output pin OUT electricity to be connected to the analog video input pin AIP1A of video decoding chip. The video processing device comprises the PAL input circuit, a differential video analog signal output by the video shooting unit is converted into a single-ended video signal through the differential-to-single-ended unit, the analog signal is converted into a digital signal through the video decoding unit, the digital signal is converted into the differential video signal again through the single-ended-to-differential unit after being processed by the processor, the digital-to-analog conversion is carried out on the video coding unit, and finally the digital signal is displayed on the display unit, so that the collection, the transmission and the processing of video data are realized.

Description

PAL input circuit and video processing apparatus including the same

Technical Field

The utility model relates to a video processing field specifically relates to PAL input circuit and including this PAL input circuit's video processing apparatus.

Background

With the increasing development of computer image technology, phase Alternating Line (PAL) video acquisition, transmission and processing technology is required to be applied to more and more fields, especially in the military industry and other fields. A large amount of information such as voice, data, video, graphics, etc. needs to be collected, stored, transmitted and processed by a computer in real time. The device for realizing the video processing mainly comprises four parts, namely: a front end portion, a transmission portion, a control portion, and a display portion. The front end part completes the shooting of analog video and mainly comprises a camera, an electric zoom lens and other equipment. The camera shoots the field condition into an analog video electrical signal through a built-in Charge-coupled Device (CCD) and an auxiliary circuit, and the analog video electrical signal is transmitted through a coaxial cable. The electric zoom lens draws a shooting scene close and pushes the shooting scene far, and optical adjustment such as aperture and focusing is achieved. The transmission section is mainly composed of a coaxial cable. The transmission part requires real-time transmission of images shot by a front-end camera, and meanwhile, the transmission has the advantages of low loss and reliable transmission quality, and the images can be clearly restored and displayed in a video control center. The control part is the core of the system and completes the functions of digital acquisition of analog video monitoring signals, video compression, monitoring data recording and retrieval, hard disk video recording and the like. The core unit of the system is an acquisition and compression unit, and the reliability of a channel, the operation processing capability and the convenience of video retrieval directly influence the performance of the whole system. The control part is a key part for realizing linkage of video recording. The display part mainly completes real-time display of video pictures and retrieval and playback of stored videos. Therefore, a specific circuit structure regarding a video processing apparatus and a PAL input circuit included in the video processing apparatus is required for collecting, transmitting and processing video data.

The above statements in the background are only intended to facilitate a thorough understanding of the present invention (including the technical means used, the technical problems solved and the technical effects produced), and should not be taken as an acknowledgement or any form of suggestion that this message constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a PAL input circuit reaches video processing apparatus including this PAL input circuit for collect, transmit and handle video data.

According to the embodiment of the present invention, a PAL input circuit is provided, which comprises a differential-to-single-ended unit and a video decoding unit, wherein the differential-to-single-ended unit is electrically connected to the video decoding unit, the differential-to-single-ended unit comprises a differential-to-single-ended chip, and the video decoding unit comprises a video decoding chip; the video decoding chip comprises an analog video input pin AIP1A, the output pin OUT of the differential-to-single end conversion chip is electrically connected to the analog video input pin AIP1A of the video decoding chip, a resistor R287, a resistor R290, a resistor R284 and a capacitor C116 are sequentially connected IN series between the output pin OUT of the differential-to-single end conversion chip and the analog video input pin AIP1A of the video decoding chip, the differential-to-single end conversion unit is provided with a pin, a first pin of the pin is electrically connected with a node between the resistor R287 and the resistor R290, a second pin of the pin is electrically connected to an analog ground AGND, and a node between the resistor R284 and the capacitor C116 is electrically connected to the analog ground AGND through the resistor R280; the video decoding chip further includes video output pins YOUT0 to YOUT7, the video output pins YOUT7 being electrically connected to the power supply 3V3 through a resistor R271 and to the power ground GND through a capacitor C112.

Further, the differential-to-single-ended chip further includes: a power supply pin + VS electrically connected to the analog power supply AVDD _5V0 and electrically connected to the analog ground AGND via a capacitor C462 and a capacitor C122 connected in parallel, a power supply pin-VS electrically connected to the analog power supply AVDD _ -5V and electrically connected to the analog ground AGND via a capacitor C463 and a capacitor C121 connected in parallel, a feedback pin FB electrically connected to the analog ground AGND through a resistor R293 and a capacitor C120 and electrically connected to the analog ground AGND through a resistor R292, and an output pin OUT electrically connected to the feedback pin FB through a resistor R289; the reference pin REF is electrically connected to analog ground AGND; the pull-down pin PD is electrically connected to the analog power supply AVDD _5V0, and the pull-down pin PD is electrically connected to the analog ground AGND via the capacitor C462 and the capacitor C122 connected in parallel.

Further, the video decoding chip further comprises: pin PLL _ AGND, pin PLL _ AVDD, pin REFM, pin REFP, pin DVDD, pin DGND, pin PLL _ AGND is electrically connected to analog ground AGND, pin PLL _ AVDD is electrically connected to analog power supply AVDD _5150, pin REFM is electrically connected to analog ground AGND through capacitor C111, pin REFP is electrically connected to analog ground AGND through capacitor C105, capacitor C107 is connected across between pin REFM and pin REFP, pin DVDD is electrically connected to power supply DVDD _5150, and pin DGND is electrically connected to power supply ground GND.

Further, the pins are single row 2-core pins with a pitch of 2.54 mm.

Further, the model of the differential-to-single-ended chip is AD8130.

Further, the model of the video decoding chip is GM7150A.

According to an embodiment of the present invention, there is provided a video processing apparatus, including the PAL input circuit described above, further including: the PAL output circuit comprises a video coding unit and a single-ended to differential unit, the video shooting unit is electrically connected to the differential to single-ended unit, the video decoding unit is electrically connected to the processor, the processor is electrically connected to the video coding unit, the video coding unit is electrically connected to the single-ended to differential unit, and the single-ended to differential unit is electrically connected to the display unit.

Further, the processor is of a HI3531A chip.

Furthermore, the single-ended to differential unit comprises a single-ended to differential chip, and the model of the single-ended to differential chip is AD8131.

Further, the video coding unit comprises a video coding chip, and the model of the video coding chip is GM7121-D.

The utility model adopts the above technical scheme, it has following beneficial effect: the video shooting unit outputs a differential video analog signal which is converted into a single-ended video signal through the differential-to-single-ended unit, the video decoding unit converts the analog signal into a digital signal, the digital signal is converted into a differential video signal again through the single-ended-to-differential unit after being processed by the processor, the digital-to-analog conversion is carried out on the video coding unit, and the differential video analog signal is displayed on the display unit finally, so that the collection, the transmission and the processing of video data are realized.

Drawings

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. For purposes of clarity, the same reference numbers will be used in different drawings to identify the same elements. It is noted that the drawings are merely schematic and are not necessarily drawn to scale. In these drawings:

fig. 1 is a block diagram showing the structure of a video processing apparatus according to an embodiment of the present invention.

Fig. 2 is a circuit schematic diagram illustrating a differential-to-single ended cell according to an embodiment of the present invention.

Fig. 3 is a circuit schematic diagram illustrating a video decoding unit according to an embodiment of the present invention.

Fig. 4 is a circuit schematic diagram illustrating a video encoding chip according to an embodiment of the present invention.

Detailed Description

The embodiments of the present invention will be described in detail below, and the embodiments are implemented on the premise of the technical solution of the present invention, and detailed embodiments and specific operation processes are given, but the scope of the present invention is not limited to the embodiments described below.

Fig. 1 is a block diagram showing the structure of a video processing apparatus according to an embodiment of the present invention. As shown in fig. 1, the video processing apparatus according to an embodiment of the present invention includes a video photographing unit 100, a PAL input circuit 200, a processor 300, a PAL output circuit 400, and a display unit 500. The PAL input circuit 200 includes a differential-to-single-ended unit 210 and a video decoding unit 220, and the PAL output circuit 400 includes a video encoding unit 410 and a single-to-differential unit 420.

The video capturing unit 100 is electrically connected to the differential-to-single-ended unit 210, the differential-to-single-ended unit 210 is electrically connected to the video decoding unit 220, the video decoding unit 220 is electrically connected to the processor 300, the processor 300 is electrically connected to the video encoding unit 410, the video encoding unit 410 is electrically connected to the single-ended-to-differential unit 420, and the single-ended-to-differential unit 420 is electrically connected to the display unit 500.

According to the utility model discloses an embodiment, video shooting unit 100 outputs PAL system difference analog signal, because the unable direct processing difference analog signal of treater 300, need can handle after converting into digital signal, consequently, PAL input circuit 200 mainly realizes that the difference changes two functions of single-ended and analog revolution number. The differential-to-single-ended unit 210 converts the video data to be processed output by the video shooting unit 100 into single-ended signal data; the video decoding unit 220 converts analog signal data into digital signal data. The processor 300 performs an analysis process on the received video image signal converted by the video decoding unit 220, for example, superimposes a time stamp or the like on the video image signal.

In addition, the PAL output circuit 400 mainly performs two functions of digital-to-analog conversion and single-ended-to-differential conversion, thereby transmitting the video image signal analyzed and processed by the processor 300 to the display unit 500. The video encoding unit 410 converts the received video image signal analyzed and processed by the processor 300 into a video single-ended analog signal of PAL system and sends the video single-ended analog signal to the single-ended to differential unit 420. The single-ended to differential unit 420 converts the received PAL format video single-ended analog signal into a differential signal and sends the differential signal to the display, so as to display on the display unit 500.

Fig. 2 is a circuit schematic diagram illustrating a differential-to-single ended cell according to an embodiment of the present invention. Fig. 3 is a circuit schematic diagram illustrating a video decoding unit according to an embodiment of the present invention. The differential-to-single-ended unit 210 includes a differential-to-single-ended chip, and the video decoding unit 220 includes a video decoding chip.

In one embodiment, the model of the differential-to-single-ended chip may be AD8130, and the model of the video decoding chip is GM7150A, but the present invention is not limited thereto. Specifically, the PAL input circuit 200 is implemented by a GM7150A (fully compatible TVP 5150) series acquisition chip of the shanghai shao core company and an AD8130 differential-to-single-ended operational amplifier, and the GM7150A series acquisition chip can be used to implement a large-scale video decoding integrated circuit with high integration and complete functions. GM7150A is a 9-bit video decoding chip, which is connected with a PC or DSP by an I2C bus to form an application system by adopting a CMOS process. The chip only comprises one analog processing channel, and can realize CVBS, S-Video signal source selection, A/D conversion, automatic clamping, automatic Gain Control (AGC), clock Generation (CGC), multi-system decoding and brightness/contrast/saturation control (BCS). The applicable range of GM7150A includes the fields of desktop video, multimedia, digital TV, image processing, video telephone, video image acquisition system, etc.

As shown IN fig. 2 and 3, the differential-to-single-ended chip includes an input pin + IN and an input pin-IN, and is configured to be electrically connected to an output terminal of the video shooting unit 100 and receive PAL video data from the video camera.

The video decoding chip includes an analog video input pin AIP1A, and the output pin OUT of the differential-to-single-ended chip is electrically connected to the analog video input pin AIP1A of the video decoding chip, so that the differential-to-single-ended unit 210 is electrically connected to the video decoding unit 220. Preferably, the video decoding chip further comprises an analog video input pin AIP1B, two analog video input ports for selection of use.

A resistor R287, a resistor R290, a resistor R284 and a capacitor C116 are sequentially connected in series between an output pin OUT of the differential-to-single-ended chip and an analog video input pin AIP1A of the video decoding chip, the differential-to-single-ended unit is provided with a pin J8, a first pin 1 of the pin is electrically connected with a node between the resistor R287 and the resistor R290, a second pin 2 of the pin is electrically connected to an analog ground AGND, and a node resistor R280 between the resistor R284 and the capacitor C116 is electrically connected to the analog ground AGND.

Preferably, the pins are 2.54mm pitch single row 2 core pins. R287=0 Ω, R290=0 Ω, R284=37.4 ± 1% Ω, C116=100nf, R280=37.4 ± 1% k Ω, R524=100NF, but the present invention is not limited thereto.

The video decoding chip further comprises video output pins YOUT0 to YOUT7 which are electrically connected with the processor to realize the acquisition of video data. The video output pin YOUT7 is electrically connected to the power supply 3V3 through a resistor R271 and to the power supply ground GND through a capacitor C112.

Preferably, R271=10K Ω, but the present invention is not limited thereto.

As shown in fig. 2, the differential-to-single-ended chip further includes: a power supply pin + VS electrically connected to the analog power supply AVDD _5V0, and the power supply pin + VS electrically connected to the analog ground AGND via a capacitor C462 and a capacitor C122 connected in parallel, a feedback pin FB electrically connected to the analog ground AGND through a resistor R293 and a capacitor C120, and the feedback pin FB electrically connected to the analog ground AGND through a resistor R292, and an output pin OUT electrically connected to the feedback pin FB through a resistor R289; the reference pin REF is electrically connected to the analog ground AGND; the pull-down pin PD is electrically connected to the analog power supply AVDD _5V0, and the pull-down pin PD is electrically connected to the analog ground AGND via the capacitor C462 and the capacitor C122 connected in parallel.

Preferably, the voltage of the analog power supply AVDD _5V0 is 5V, the voltage of the analog power supply AVDD _ -5V is 5V, c462=100nf, c122=10uf, c463=100nf, C121=10uF, R293=100 Ω, R292=499 Ω, C120=200pf, and R289=0 Ω, but the present invention is not limited thereto.

As shown in fig. 3, the video decoding chip further includes: pin PLL _ AGND, pin PLL _ AVDD, pin REFM, pin REFP, pin DVDD, and pin DGND. Pin PLL _ AGND is electrically connected to analog ground AGND, pin PLL _ AVDD is electrically connected to analog power supply AVDD _5150, pin REFM is electrically connected to analog ground AGND through capacitor C111, pin REFP is electrically connected to analog ground AGND through capacitor C105, capacitor C107 is connected across between pin REFM and pin REFP, pin DVDD is electrically connected to power supply DVDD _5150, and pin DGND is electrically connected to power supply ground GND.

Preferably, C111=1uf, C107=1uf, C105=1uf, but the present invention is not limited thereto.

In one embodiment, the processor is a HI3531A chip, but the invention is not limited thereto. Specifically, the processor is a domestic Haisi high-performance HI3531 processor, which is a professional high-end SOC chip applied to application and development of multi-path high-definition DVR and NVR products. The chip is internally provided with a powerful high-performance dual-core A9 processor, an engine with up to 5-path 1080P real-time multi-protocol coding and decoding capability and a special TOE network acceleration module, can easily meet the requirements of high-definition application and network, integrates excellent video front and back processing and coding and decoding algorithms, and combines multi-path high-definition display output capability.

According to the utility model discloses an embodiment, single-ended commentaries on classics difference unit 420 includes that single-ended changes difference chip, and video coding unit 410 includes video coding chip.

In one embodiment, the model of the single-ended to differential chip is AD8131, and the model of the video coding chip is GM7121-D. Specifically, PAL output circuit 400 employs GM7121-D from Dow Corning as the video coding chip for local playback. GM7121-D/GM7122 is a single-chip video DAC designed for high resolution color graphics and video systems, and also meets the field of low-cost, high-speed DAC applications, especially communication applications. Three high-speed 10-bit video digital-to-analog converters (RGB), a standard TTL input interface and a high-impedance analog output current source are built in the high-speed 10-bit video analog-to-digital converter. GM7121-D/GM7122 has three separate 10-bit pixel input ports for red, green, and blue video data, respectively. GM7121-D/GM7122 supports the NTSC-M, PAL-B/G standards and their sub-standards. The GM7121-D outputs standard single-ended PAL video signals, which can be converted into differential signals for output through AD8131 single-ended to differential operational amplifier.

Fig. 4 is a circuit schematic diagram illustrating a video encoding chip according to an embodiment of the present invention. As shown in fig. 4, the video coding chip inputs video signals through the pins MP0 to MP7 and outputs video signals through the pins CVBS, Y, and C.

According to the utility model discloses a PAL input circuit 200 of embodiment reaches video processing apparatus including this PAL input circuit 200, the differential video analog signal of unit 100 output is shot to the video turns into single-ended video signal through the difference to single-ended unit 210, convert analog signal into digital signal through video decoding unit 220, process the back through treater 300 and turn into differential video signal again through single-ended to differential unit 420 and carry out digital analog conversion at video coding unit 410, show at display element 500 at last, the collection to video data has been realized, transmission and processing.

The various embodiments of the present invention are not an exhaustive list of all possible combinations, but are intended to describe representative aspects of the invention, and what is described in the various embodiments can be applied independently or in combinations of two or more.

The above description of exemplary embodiments has been presented only to illustrate the technical solutions of the present invention, and is not intended to be exhaustive or to limit the present invention to the precise forms described. Obviously, many modifications and variations are possible in light of the above teaching to those skilled in the art. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to thereby enable others skilled in the art to understand, implement and utilize the invention in various exemplary embodiments and with various alternatives and modifications. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims (10)

1. A PAL input circuit includes a differential-to-single-ended unit and a video decoding unit, the differential-to-single-ended unit is electrically connected to the video decoding unit,

the video decoding unit comprises a video decoding chip;

the differential-to-single-ended chip comprises an input pin + IN and an input pin-IN, a resistor R294 is connected between the input pin + IN and the input pin-IN IN a bridging mode,

the differential-to-single-ended chip further comprises an output pin OUT, the video decoding chip comprises an analog video input pin AIP1A, the output pin OUT of the differential-to-single-ended chip is electrically connected to the analog video input pin AIP1A of the video decoding chip,

a resistor R287, a resistor R290, a resistor R284 and a capacitor C116 are sequentially connected in series between an output pin OUT of the differential-to-single-ended chip and an analog video input pin AIP1A of the video decoding chip, the differential-to-single-ended unit is provided with a pin, a first pin of the pin is electrically connected with a node between the resistor R287 and the resistor R290, a second pin of the pin is electrically connected to an analog ground AGND, a node between the resistor R284 and the capacitor C116 is electrically connected to the analog ground AGND through a resistor R280,

the video decoding chip further includes video output pins YOUT0 to YOUT7, the video output pins YOUT7 being electrically connected to the power supply 3V3 through a resistor R271 and to the power supply ground GND through a capacitor C112.

2. A PAL input circuit as claimed in claim 1,

the differential-to-single-ended chip further comprises: a power supply pin + VS, a power supply pin-VS, a feedback pin FB, a reference pin REF and a pull-down pin PD,

power supply pin + VS is electrically connected to analog power supply AVDD _5V0, and power supply pin + VS is electrically connected to analog ground AGND via capacitor C462 and capacitor C122 connected in parallel,

the power supply pin-VS is electrically connected to the analog power supply AVDD _ -5V, and the power supply pin-VS is electrically connected to the analog ground AGND via a capacitor C463 and a capacitor C121 connected in parallel,

the feedback pin FB is electrically connected to analog ground AGND through a resistor R293 and a capacitor C120, and the feedback pin FB is electrically connected to analog ground AGND through a resistor R292,

the output pin OUT is electrically connected to the feedback pin FB through a resistor R289,

reference pin REF is electrically connected to analog ground AGND,

the pull-down pin PD is electrically connected to the analog power supply AVDD _5V0, and the pull-down pin PD is electrically connected to the analog ground AGND via the capacitor C462 and the capacitor C122 connected in parallel.

3. The PAL input circuit of claim 1, wherein,

the video decoding chip further comprises: pin PLL _ AGND, pin PLL _ AVDD, pin REFM, pin REFP, pin DVDD, pin DGND,

pin PLL AGND is electrically connected to analog ground AGND,

pin AGND is electrically connected to analog ground AGND,

pin PLL _ AVDD is electrically connected to analog power supply AVDD _5150,

pin REFM is electrically connected to analog ground AGND through capacitor C111, pin REFP is electrically connected to analog ground AGND through capacitor C105, capacitor C107 is connected across pin REFM and pin REFP,

pin DVDD is electrically connected to power supply DVDD _5150,

pin DGND is electrically connected to power ground GND.

4. The PAL input circuit of claim 1, wherein said pins are 2.54mm pitch single row 2-core pins.

5. The PAL input circuit of claim 1, wherein said differential to single ended chip has a model number AD8130.

6. A PAL input circuit according to claim 1, wherein said video decoding chip has a model number of GM7150A.

7. A video processing apparatus comprising the PAL input circuit of any one of claims 1 to 6, further comprising: a video shooting unit, a processor, a PAL output circuit and a display unit,

the PAL output circuit includes a video encoding unit and a single-ended to differential unit,

the video shooting unit is electrically connected to the differential-to-single end unit, the video decoding unit is electrically connected to the processor, the processor is electrically connected to the video coding unit, the video coding unit is electrically connected to the single-end-to-differential unit, and the single-end-to-differential unit is electrically connected to the display unit.

8. The video processing apparatus of claim 7, wherein the processor is of a HI3531A chip.

9. The video processing device of claim 7, wherein the single-ended to differential unit comprises a single-ended to differential chip, and the model of the single-ended to differential chip is AD8131.

10. The video processing apparatus of claim 7, wherein the video coding unit comprises a video coding chip having a model number of GM7121-D.

Images