CN218450088U - Signal conditioning circuit, chip and electronic equipment - Google Patents

Abstract

The application provides a signal conditioning circuit, a chip and an electronic device. The signal conditioning circuit provided by the application comprises a gain amplifier and a successive approximation analog-to-digital converter; the first input end and the second input end of the gain amplifier are used for receiving differential input signals, the first input end of the gain amplifier is also used for receiving reference voltage, and the output end of the gain amplifier is fed back to the second input end; the first input end of the successive approximation analog-to-digital converter is electrically connected to the output end of the gain amplifier, and the second input end of the successive approximation analog-to-digital converter is used for receiving the reference voltage. The signal conditioning circuit provided by the application eliminates the influence of common-mode voltage while simplifying the circuit structure.

Description

Signal conditioning circuit, chip and electronic equipment

Technical Field

The application relates to the technical field of operational amplifiers, in particular to a signal conditioning circuit, a chip and electronic equipment.

Background

The programmable operational amplifier is used for the front end of the analog-to-digital converter and has the functions of amplifying small signals and driving. In most of the existing programmable operational amplifier schemes, the influence of the common mode voltage cannot be well eliminated, and in one existing scheme, a circuit schematic diagram of a first stage of the programmable operational amplifier is shown in fig. 1, wherein the first stage of the programmable operational amplifier is a gain amplification stage; a schematic circuit diagram of a second stage of the programmable operational amplifier, as shown in fig. 2, the second stage of the programmable operational amplifier being a driver; the scheme can eliminate the influence of common-mode voltage, but the common-mode voltage needs a common-mode feedback circuit, so that the circuit is complex.

SUMMERY OF THE UTILITY MODEL

An object of the application is to provide a signal conditioning circuit, a chip and an electronic device, so as to solve the technical problem that the influence of common mode voltage cannot be eliminated by using a simple circuit in the prior art.

The technical scheme of the application is that the signal conditioning circuit comprises a gain amplifier and an analog-to-digital converter;

the first input end and the second input end of the gain amplifier are used for receiving differential input signals, the first input end of the gain amplifier is also used for receiving reference voltage, and the output end of the gain amplifier is fed back to the second input end;

the first input end of the analog-to-digital converter is electrically connected to the output end of the gain amplifier, and the second input end of the analog-to-digital converter is used for receiving the reference voltage.

Another technical solution of the present application is as follows, further providing a chip including the signal conditioning circuit according to any one of the above technical solutions.

Another technical solution of the present application is as follows, further providing an electronic device including the signal conditioning circuit according to any one of the above technical solutions.

The beneficial effect of this application lies in: the first input end and the second input end of the gain amplifier are used for receiving differential input signals, the first input end of the gain amplifier is also used for receiving reference voltage, and the output end of the gain amplifier is fed back to the second input end; the first input end of the analog-to-digital converter is electrically connected with the output end of the gain amplifier, and the second input end of the analog-to-digital converter is used for receiving the reference voltage; by the mode, the influence of common-mode voltage is eliminated while the circuit structure is simplified.

Drawings

FIG. 1 is a circuit schematic of a first stage of a programmable operational amplifier as provided herein;

FIG. 2 is a circuit schematic of a second stage of the programmable operational amplifier provided herein;

fig. 3 is a block diagram of a signal conditioning circuit according to an embodiment of the present disclosure;

fig. 4 is a first circuit schematic diagram of a signal conditioning circuit according to an embodiment of the present disclosure;

fig. 5 is a second block diagram of a signal conditioning circuit according to an embodiment of the present disclosure;

FIG. 6 is a second circuit schematic of a signal conditioning circuit provided by an embodiment of the present application;

fig. 7 is a third circuit schematic diagram of a signal conditioning circuit according to an embodiment of the present application;

fig. 8 is a fourth circuit schematic diagram of a signal conditioning circuit according to an embodiment of the present application;

fig. 9 is a fifth circuit schematic diagram of a signal conditioning circuit according to an embodiment of the present application.

Detailed Description

To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

In the embodiments of the present application, at least one means one or more; plural means two or more. In the description of the present application, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance, nor order.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the terms "including," "comprising," "having," and variations thereof in this specification mean "including, but not limited to," unless expressly specified otherwise.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Fig. 3 is a first block diagram of a signal conditioning circuit according to an embodiment of the present application. It should be noted that the signal conditioning circuit provided in the present application is not limited to the structure shown in fig. 3 if the results are substantially the same. As shown in fig. 3, the signal conditioning circuit includes a gain amplifier PGA and an analog-to-digital converter ADC.

The first input end and the second input end of the gain amplifier PGA are used for receiving differential input signals (VINP and VINN), the first input end of the gain amplifier PGA is also used for receiving a reference voltage, and the output end of the gain amplifier PGA is fed back to the second input end; the gain amplifier PGA includes an operational amplifier, and an output terminal of the gain amplifier PGA is an output terminal of the operational amplifier and can be fed back to one of input terminals of the operational amplifier. Alternatively, the reference voltage may be directly input to the first input terminal of the gain amplifier PGA, or may be indirectly input to the first input terminal of the gain amplifier PGA through other components. For example, the reference voltage may be divided by one or more resistors and then input to the first input terminal of the gain amplifier PGA.

The first input terminal of the analog-to-digital converter ADC is electrically connected to the output terminal of the gain amplifier PGA, and the second input terminal of the analog-to-digital converter ADC is configured to receive a reference voltage. Alternatively, the analog-to-digital converter ADC may be a successive approximation analog-to-digital converter (sar ADC), or may be another type of analog-to-digital converter, such as a flash analog-to-digital converter, a pipeline analog-to-digital converter, or the like.

In the embodiment of the present application, the first input terminal and the second input terminal of the gain amplifier PGA receive a differential input signal, the output terminal of the gain amplifier PGA is fed back to the second input terminal, and the first input terminal of the gain amplifier PGA and the second input terminal of the analog-to-digital converter ADC respectively receive a reference voltage; the influence of common mode voltage is eliminated while the circuit structure is simplified. It should be noted that, since the output of the gain amplifier PGA is related to the reference voltage, the reference voltage determines the common-mode voltage of the output of the gain amplifier PGA, and the reference voltage is connected to the input terminal of the analog-to-digital converter ADC, so that the reference voltage portion (i.e., the low-frequency direct-current portion) in the output of the gain amplifier PGA can be cancelled, and the signal conditioning circuit provided in the embodiment of the present application is not affected by the common-mode voltage. The gain amplifier PGA may be a programmable gain amplifier.

As an example, the first input terminal and the second input terminal of the gain amplifier PGA may be a positive input terminal and a negative input terminal, respectively, and the first input terminal and the second input terminal of the analog-to-digital converter ADC may be a positive input terminal and a negative input terminal, respectively.

In some embodiments, as shown in fig. 5, the signal conditioning circuit further includes a reference voltage circuit, the reference voltage circuit includes a BANDGAP reference source BANDGAP and a conversion module VS, one end of the BANDGAP reference source BANDGAP is connected to the power supply, the other end of the BANDGAP reference source BANDGAP is connected to the conversion module VS, and an output end of the conversion module VS is used for outputting a reference voltage.

Specifically, the BANDGAP reference source BANDGAP can generate a BANDGAP reference voltage Vbg, which is used as a reference for the conversion module VS, and the conversion module VS generates a reference voltage VREF according to the BANDGAP reference voltage Vbg, and provides a reference voltage for the gain amplifier PGA and the successive approximation analog-to-digital converter ADC through the reference voltage VREF. As an example, the conversion module VS may be implemented by a low dropout linear regulator (LDO).

Alternatively, the conversion module VS may be used as a buffer to output the reference voltage Vbg in a ratio of 1. Or, further, the conversion module VS may also be used as a boosting circuit, and may boost the reference voltage Vbg by a ratio greater than 1 and output the boosted voltage as needed.

According to the embodiment of the application, the BANDGAP reference source BANDGAP and the conversion module VS are used for providing the reference voltage for the gain amplifier PGA, so that the signal conditioning circuit is not influenced by the common-mode voltage.

In some embodiments, a first circuit schematic of a signal conditioning circuit is shown in fig. 4. In fig. 4, the gain amplifier PGA includes an operational amplifier A1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R0; the differential input signal comprises a first input signal VINP and a second input signal VINN; a first input end of the operational amplifier A1 receives a first input signal VINP through a first resistor R1, and a second input end of the operational amplifier A1 receives a second input signal VINN through a second resistor R2; the first input terminal of the operational amplifier A1 also receives a reference voltage VREF through a fourth resistor R0. One end of the third resistor R3 is connected to the second input terminal of the operational amplifier A1, and the other end of the third resistor R3 is connected to the output terminal of the operational amplifier A1. In this embodiment, the end of the first resistor R1 not connected to the operational amplifier A1 is a first input end of the gain amplifier, the end of the second resistor R2 not connected to the operational amplifier A1 is a second input end of the gain amplifier, and the output end of the operational amplifier A1 is an output end of the gain amplifier.

In one embodiment, the resistance of the fourth resistor R0 is equal to the resistance of the resistor R3, and the resistance of the first resistor R1 is equal to the resistance of the second resistor R2.

In one embodiment, the first resistor R1 and the second resistor R2 are variable resistors. The gain of the gain amplifier can be adjusted through the first resistor R1 and the second resistor R2.

In one embodiment, the ratio of the resistance value of the first resistor R1 and the resistance value of the second resistor R2 to the resistance value of the fourth resistor R0 and the resistance value of the resistor R3 is proportional coefficient, and when R0= R3 and R1= R2, the output voltage PGA _ OUT of the gain amplifier can be obtained by the principle of virtual short of the operational amplifier:

wherein, VINP and VINN are a pair of differential signals, VINP is a first input signal, VINN is a second input signal, and in the correlation calculation formula, they represent corresponding voltage values, R0 and R1 represent corresponding resistance values in the correlation calculation formula, and VREF also represents corresponding reference voltage values in the correlation calculation formula. According to the formula, the gain amplification factor of the gain amplifier is R0/R1, the output voltage of the gain amplifier is equal to the result that the differential input signal (VINP-VINN) is amplified by R0/R1 and then is superposed with the reference voltage VREF, the reference voltage VREF is equivalent to the common mode voltage in the output voltage of the gain amplifier, and if the common mode voltage is too large, the output voltage of the gain amplifier can exceed the input voltage range of the analog-to-digital converter, so that the analog-to-digital converter cannot work normally.

In this embodiment, the analog-to-digital converter ADC is a differential input analog-to-digital converter, a non-inverting input terminal of the analog-to-digital converter ADC is connected to the output PGA _ OUT of the gain amplifier, an inverting input terminal of the analog-to-digital converter ADC is connected to the reference voltage VREF, and an object detected by the analog-to-digital converter ADC is a difference obtained by subtracting the reference voltage VREF from the output PGA _ OUT of the gain amplifier, so a voltage value detected by the ADC is R0/R1 (VINP-VINN), where R0/R1 is an amplification factor of the gain amplifier PGA, and a value thereof may be set according to an actual situation; therefore, the division of the output result of the successive approximation analog-to-digital converter ADC by R0/R1 is the magnitude of the differential input signal (VINP-VINN), i.e. the influence of the common mode voltage in the output voltage of the gain amplifier is eliminated.

In one embodiment, the reference voltage input of the successive approximation analog-to-digital converter is also used for receiving a reference voltage. The input signal range of the analog-to-digital converter depends on the reference voltage received by the reference voltage input terminal, and the reference voltage is the same as the common mode voltage in the output voltage of the PGA, so that the output voltage range of the gain amplifier can be matched with the input signal range of the analog-to-digital converter. As an embodiment, by adjusting the reference voltage, a resolution range of a full-scale input voltage of the successive approximation analog-to-digital converter can be adjusted, so as to adapt to various input signals with different sizes.

In some embodiments, a second circuit schematic of the signal conditioning circuit is shown in fig. 6, and in fig. 6, the signal conditioning circuit includes a gain amplifier PGA, an analog-to-digital converter ADC, a BANDGAP reference BANDGAP, and a conversion module VS. The circuit structures and the working principles of the gain amplifier PGA and the analog-to-digital converter ADC may refer to the foregoing embodiments, and the relevant descriptions of the BANDGAP reference source BANDGAP and the conversion module VS may also refer to the foregoing embodiments, which are not described herein again.

In some embodiments, the signal conditioning circuit further comprises a low-pass filter circuit, one end of the low-pass filter circuit is connected to the output end of the conversion module, and the other end of the low-pass filter circuit is grounded.

As an example, a third circuit schematic of the signal conditioning circuit is shown in fig. 7. In fig. 7, the low-pass filter circuit includes a first capacitor C1, one end of the first capacitor C1 is connected to the output end of the conversion module VS, and the other end of the first capacitor C1 is grounded.

The first capacitor C1 is connected to the reference voltage output terminal, so that low-pass filtering can be performed to suppress high-frequency interference.

Optionally, the first capacitor C1 may be integrated in a chip together with other circuits such as a gain amplifier, an analog-to-digital converter, a reference voltage circuit, and the like; alternatively, the first capacitor C1 may be disposed outside the chip to save chip area.

As an embodiment, when the analog-to-digital converter ADC is a successive approximation analog-to-digital converter, the capacitance value of the first capacitor C1 may be set to be much larger than the capacitance value of the capacitor array in the successive approximation analog-to-digital converter ADC, for example, the ratio of the capacitance value to the capacitance value is more than ten times, so that the capacitance in the successive approximation analog-to-digital converter ADC can be turned over faster, and the sampling rate is increased. It should be noted that, a low-resistance path is provided by the first capacitor C1 to reduce the output impedance of the reference voltage circuit, so that the sampling speed of the sub-approximation analog-to-digital converter ADC is increased, and the sampling rate thereof is increased. In this case, the first capacitor C1 needs a large area and can be disposed outside the chip.

In some embodiments, a fourth circuit schematic of the signal conditioning circuit is shown in fig. 8. In fig. 8, the signal conditioning circuit further includes a switch S1, one end of the switch S1 is connected to one end of the fourth resistor R0, the other end of the switch S1 is used for receiving a reference voltage, and the other end of the fourth resistor R0 is connected to the first input end of the operational amplifier. The switch S1 can be closed when the signal conditioning circuit needs to work, and can be opened when the signal conditioning circuit does not need to work, so that electric leakage is reduced, and power consumption is reduced.

In some embodiments, as shown in fig. 6, 7 or 8, the signal conditioning circuit further includes a digital module digital, which is electrically connected to the output of the analog-to-digital converter. The digital module digital performs digital processing on the output signal of the analog-to-digital converter.

In some embodiments, a fifth circuit schematic of the signal conditioning circuit is shown in fig. 9, and the gain amplifier further includes a second capacitor C2, and the second capacitor C2 is connected in parallel with the resistor R3. The second capacitor C2 may introduce a zero point, which has a compensation effect on the phase margin.

In some embodiments, the gain amplifier further comprises a third capacitor C3, the third resistor R3 comprises a first sub-resistor R31 and a second sub-resistor R31 connected in series; one end of the third capacitor C3 is connected to the connection node of the first sub-resistor R31 and the second sub-resistor R32, and the other end of the third capacitor C3 is grounded.

In the embodiment of the present application, after the first sub-resistor R31 and the second sub-resistor R32 are connected in series, the negative input terminal of the gain amplifier and the output terminal of the gain amplifier are connected, which can achieve the same function as the above-mentioned resistor R3, and the third capacitor C3 is added to further filter noise or interference in the circuit.

In the signal conditioning circuit disclosed in the embodiment of the present application, the first input terminal and the second input terminal of the gain amplifier PGA receive a differential input signal, and the first input terminal of the gain amplifier PGA also receives a reference voltage, so that the output terminal of the gain amplifier PGA is fed back to the second input terminal; the influence of common mode voltage is eliminated while the circuit structure is simplified. The signal conditioning circuit provided by the embodiment of the application has the advantages that the structure is simple, the circuit complexity is low, only one operational amplifier is arranged in the circuit structure, a common-mode feedback circuit is not needed, and the occupied area and power consumption of the circuit are reduced.

The embodiment of the application provides a chip, which comprises the signal conditioning circuit in any embodiment.

An embodiment of the present application provides an electronic device, including the signal conditioning circuit according to any one of the embodiments described above.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express the preferred embodiments of the present application, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the patent. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (15)

1. A signal conditioning circuit is characterized by comprising a gain amplifier and an analog-to-digital converter;

the first input end and the second input end of the gain amplifier are used for receiving differential input signals, the first input end of the gain amplifier is also used for receiving reference voltage, and the output end of the gain amplifier is fed back to the second input end;

the first input end of the analog-to-digital converter is electrically connected to the output end of the gain amplifier, and the second input end of the analog-to-digital converter is used for receiving the reference voltage.

2. The signal conditioning circuit of claim 1, further comprising a reference voltage circuit, wherein the reference voltage circuit comprises a bandgap reference source and a conversion module, one end of the bandgap reference source is connected to a power supply, the other end of the bandgap reference source is connected to the conversion module, and an output end of the conversion module outputs the reference voltage.

3. The signal conditioning circuit of claim 2, further comprising a low pass filter circuit, one end of the low pass filter circuit being connected to the output of the conversion module, the other end of the low pass filter circuit being connected to ground.

4. The signal conditioning circuit of claim 3 wherein the low pass filter circuit comprises a first capacitor C1, one end of the first capacitor C1 is connected to the output terminal of the conversion module, and the other end of the first capacitor C1 is grounded.

5. The signal conditioning circuit of any of claims 1-4, wherein the gain amplifier comprises an operational amplifier, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R0; the differential input signal comprises a first input signal and a second input signal;

the first input end of the operational amplifier receives the first input signal through the first resistor R1, and the second input end of the operational amplifier receives the second input signal through the second resistor R2;

one end of the third resistor R3 is connected with the second input end of the operational amplifier, and the other end of the third resistor R3 is connected with the output end of the operational amplifier;

the first input terminal of the operational amplifier receives the reference voltage through the fourth resistor R0.

6. The signal conditioning circuit of claim 5, further comprising a switch S1, wherein one end of the switch S1 is connected to one end of the fourth resistor R0, the other end of the switch S1 is used for receiving the reference voltage, and the other end of the fourth resistor R0 is connected to the first input end of the operational amplifier.

7. The signal conditioning circuit of claim 5 wherein the resistance value of the fourth resistor R0 is equal to the resistance value of the resistor R3, and the resistance value of the first resistor R1 is equal to the resistance value of the second resistor R2.

8. The signal conditioning circuit of claim 5 wherein the first resistor R1 and the second resistor R2 are variable resistors.

9. The signal conditioning circuit of claim 5 wherein the gain amplifier further comprises a second capacitor C2, the second capacitor C2 being connected in parallel with the third resistor R3.

10. The signal conditioning circuit of claim 5 wherein the gain amplifier further comprises a third capacitor C3, the third resistor R3 comprising a first resistor R31 and a second resistor R31 connected in series;

one end of the third capacitor C3 is connected to the connection node of the first sub-resistor R31 and the second sub-resistor R32, and the other end of the third capacitor C3 is grounded.

11. The signal conditioning circuit of claim 1 wherein the analog-to-digital converter is a successive approximation register analog-to-digital converter.

12. The signal conditioning circuit of any of claims 1-4, wherein a reference voltage input of the analog-to-digital converter is configured to receive the reference voltage.

13. The signal conditioning circuit of any of claims 1-4, further comprising a digital module electrically connected to an output of the analog-to-digital converter.

14. A chip comprising the signal conditioning circuit of any of claims 1-13.

15. An electronic device comprising the signal conditioning circuit of any of claims 1-13.

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