CN218416382U - Broadband satellite signal receiving and transmitting device - Google Patents

Abstract

The utility model discloses a device of broadband satellite signal reception and transmission, the device includes: the receiving module is used for receiving radio frequency signals and comprises a band-pass filter used for filtering useless signals, a gain module used for carrying out gain amplification on the input radio frequency signals, an IQ demodulator used for carrying out quadrature decoding on the amplified radio frequency signals to obtain broadband intermediate frequency signals and an ADC receiver used for carrying out analog-to-digital conversion on the input intermediate frequency signals; the sampling rate of the ADC receiver is 5000Msps; and the transmitting module comprises a DAC transmitter for performing digital-to-analog conversion on a video signal to be transmitted, and the sampling rate of the DAC transmitter is 12.6Gsps.

Description

Broadband satellite signal receiving and transmitting device

Technical Field

The utility model belongs to the technical field of the satellite communication product, concretely relates to device of broadband satellite signal reception and transmission.

Background

Satellite communication is space microwave communication between radio communication stations on earth (including in the land, water and lower atmosphere) using artificial satellites as relay stations, and is the inheritance and development of terrestrial microwave relay communication.

The radio communication station receives and retransmits the satellite signal, and the satellite signal needs to be received, collected, processed and the like. Satellite signal bands can be generally divided into c-band, ku-band, ka-band, S-band, L-band, etc., and each band is defined as follows:

1) The c wave band is a section of frequency band with the frequency of 4.0-8.0 GHz and is used as the frequency band of the downlink transmission signal of the communication satellite;

2) Ku band, wherein the downlink of Ku band is from 10.7 to 12.75GHz, and the uplink is from 12.75 to 18.1GHz;

3) A Ka band, a portion of the microwave band of the electromagnetic spectrum, the frequency range of the Ka band being 26.5-40GHz;

4) The S wave band refers to an electromagnetic wave frequency band with the frequency range of 1.55-3.4 GHz;

5) The L-band is a radio wave band with a frequency of 1-2 GHz according to the IEEE 521-2002 standard, and belongs to millimeter waves.

At present, in broadband satellite communication, a user uses a plurality of narrowband receiving devices and transmitting devices to realize receiving and transmitting of L-band broadband signals, so that the whole receiving and transmitting devices are large in size, and the multiple devices are interfered with each other, and the stability is poor.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a device of broadband satellite signal reception and transmission, the device can realize L frequency channel broadband signal reception and emitter simultaneously, simplifies equipment structure, reduces equipment cost and can effectively solve the mutual interference problem between many narrowband equipment.

Therefore, the utility model provides a device includes:

the receiving module is used for receiving radio frequency signals and comprises a band-pass filter used for filtering useless signals, a gain module used for carrying out gain amplification on input radio frequency signals, an IQ demodulator used for carrying out quadrature decoding on the amplified radio frequency signals to obtain broadband intermediate frequency signals and an ADC receiver used for carrying out analog-to-digital conversion on the input intermediate frequency signals; the sampling rate of the ADC receiver is 5000Msps;

and the transmitting module comprises a DAC transmitter for performing digital-to-analog conversion on a video signal to be transmitted, and the sampling rate of the DAC transmitter is 12.6Gsps.

In some embodiments, the receiving module further comprises a programmable intermediate frequency gain control module for gain amplifying or attenuating the intermediate frequency signal output by the IQ demodulator, and the programmable intermediate frequency gain control module comprises an intermediate frequency gain amplifier and a programmable attenuator.

In some embodiments, the programmable if gain control module has an output coupled to a programmable if filter for filtering unwanted signals.

In some embodiments, the receiving module further comprises a first FPGA circuit connected to the ADC receiver output for demodulating and decoding the ADC receiver output signal.

In some embodiments, the transmitting module further includes a programmable rf gain control module for gain amplifying or attenuating the rf signal output by the DAC transmitter, and the programmable rf gain control module includes an rf gain amplifier and a programmable attenuator.

In some embodiments, the programmable rf gain control module has an output connected to a programmable filter array for filtering unwanted signals; including bandpass filters of various bandwidths.

In some embodiments, the transmitting module further includes an ARM circuit, a second FPGA circuit for encoding and modulating data, and an SERDES interface for data transmission, the ARM circuit is connected to the SERDES interface and the second FPGA circuit, respectively, an output end of the second FPGA circuit is electrically connected to an input end of the DAC transmitter, and the encoded and modulated data is input to the DAC transmitter as a radio frequency signal to be transmitted.

The utility model provides an another kind of structure of device of broadband satellite signal receiving and transmission includes:

the receiving module is used for receiving radio frequency signals and comprises a band-pass filter used for filtering useless signals, a gain module used for performing gain amplification on input radio frequency signals, an IQ demodulator used for performing quadrature decoding on the amplified radio frequency signals to obtain broadband intermediate frequency signals, an ADC receiver used for performing analog-to-digital conversion on the input intermediate frequency signals and a first FPGA circuit used for demodulating and decoding output signals of the ADC receiver; the ADC receiver has a sampling rate of 5000Msps;

the transmitting module comprises an ARM circuit, a second FPGA circuit electrically connected with the output end of the ARM circuit and a DAC transmitter electrically connected with the output end of the second FPGA circuit, and the sampling rate of the DAC transmitter is 12.6Gsps;

the SWITCH module comprises a first SERDES interface electrically connected with the output end of the first FPGA circuit and a second SERDES interface electrically connected with the input end of the ARM circuit;

the interface module comprises a data interface circuit and a management interface circuit which are respectively connected with the SWITCH module;

the clock module is used for generating various clock frequency signals, providing the clock frequency signals to the ADC receiver, the DAC transmitter, the IQ demodulator, the first FPGA circuit and the second FPGA circuit as reference clocks, and comprises a constant temperature crystal oscillator and a phase-locked loop;

the ARM circuit is further connected with the IQ demodulator, the ADC receiver, the DAC transmitter and the phase-locked loop respectively.

In some embodiments, the receiving module of the second structure of the apparatus of the present invention further comprises:

the programmable intermediate frequency gain control module is used for carrying out gain amplification or attenuation on the intermediate frequency signal output by the IQ demodulator and comprises an intermediate frequency gain amplifier and a programmable attenuator;

the programmable intermediate frequency filter is connected with the output of the programmable intermediate frequency gain control module and is used for filtering useless signals;

the programmable intermediate frequency gain control module and the programmable intermediate frequency filter are also respectively connected with the ARM circuit.

In some embodiments, the receiving module of the second structure of the apparatus of the present invention further comprises:

the programmable radio frequency gain control module is used for performing gain amplification or attenuation on the radio frequency signal output by the DAC transmitter and comprises a radio frequency gain amplifier and a programmable attenuator;

the programmable filter array is connected with the output of the programmable radio frequency gain control module and is used for filtering useless signals, and the programmable filter array comprises band-pass filters with various bandwidths;

the programmable radio frequency gain control module and the programmable filter array are also respectively connected with the ARM circuit.

Adopt the technical scheme of the utility model, the technological effect that can reach is at least: the device provided by the utility model is provided with an ADC module with sampling frequency of 5000Msps, and carries out full sampling on signals in 1.2GHz bandwidth; and configuring a DAC transmitter with the sampling frequency of 12.6Gsps to fully sample the signals in the bandwidth of 1.2 GHz. The L-band broadband signal receiving and transmitting are realized by one device, the combination of a plurality of narrowband receiving devices and a plurality of narrowband transmitting devices is not needed, the device structure is simplified, the device cost is reduced, and the problem of mutual interference among a plurality of narrowband devices is effectively solved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:

fig. 1 is a schematic block diagram of a device circuit provided by the present invention;

FIG. 2 is a layout view of a PCBA board of the apparatus provided by the present invention;

fig. 3 is a top view of the apparatus provided by the present invention;

fig. 4 is a plan view of the appearance of the shield case according to the present invention;

fig. 5 is a bottom view of the outer appearance of the shield case according to the present invention.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

For realizing L frequency channel broadband signal reception and transmission simultaneously, the utility model discloses a device of broadband satellite signal reception and transmission. Referring to fig. 1, the apparatus includes:

a) A first RF interface for receiving a radio frequency signal;

b) A second RF interface for transmitting radio frequency signals;

c) The band-pass filter BPF is connected with the first RF interface and filters useless signals outside the input L-band signal;

d) The RF gain module is used for realizing gain amplification on an input radio frequency signal;

e) The IQ demodulator is used for carrying out quadrature demodulation on the amplified radio frequency signal to obtain a broadband intermediate frequency signal;

f) The programmable intermediate frequency gain control module comprises an intermediate frequency gain amplifier and a programmable attenuator and is used for realizing gain amplification and attenuation of intermediate frequency signals;

g) The programmable intermediate frequency filter is a low-pass filter with configurable cut-off frequency parameters, and can be used for configuring the cut-off frequency parameters according to requirements and filtering out unnecessary signals;

h) The ADC receiver is used for carrying out analog-to-digital conversion (A/D conversion) on an input intermediate frequency signal, the sampling rate of the ADC receiver is 5000Msps, and the ADC receiver can carry out full sampling on the signal within the bandwidth of 1.2 GHz; the DDC module is integrated in the DDC module and can perform digital down-conversion on the sampled data; the method adopts a high-speed SERDES interface to transmit data;

i) The DAC transmitter comprises 1 DAC channel, 8 DUC channels and 1 combiner, the sampling rate is 12.6Gsps, digital up-conversion, aggregation and digital-to-analog conversion (D/A conversion) are carried out on a band-to-band transmission radio frequency signal, and an L-band broadband satellite signal containing a plurality of carrier signals can be generated;

j) The programmable radio frequency gain control module comprises a radio frequency gain amplifier and a programmable attenuator and is used for realizing gain amplification and attenuation on the radio frequency signal output by the DAC transmitter;

k) The programmable filter array comprises band-pass filters (BPF) with various bandwidths, and can select a filter with a proper bandwidth according to the frequency and the bandwidth of an output signal to obtain better signal output;

l) the FPGA circuit comprises a first FPGA circuit and a second FPGA circuit, each FPGA circuit comprises a DDR circuit, the first FPGA circuit completes digital demodulation and decoding of data output by the ADC receiver, and demodulated or decoded data are output to the SWITCH circuit through a high-speed SERDES interface; the second FPG circuit receives data from the ARM circuit through the high-speed PCIE interface, the data are subjected to line coding, modulation and the like, digital baseband signals are generated, and the digital baseband signals are output to the DAC transmitter through the high-speed JESD204B interface; the DDR circuit realizes data caching;

m) the ARM circuit receives network data through a high-speed SERDES interface SWITCH circuit, extracts service data to be sent, and outputs the service data to the second FPGA circuit through a high-speed PCIE interface; the ARM circuit also controls the IQ demodulator, the programmable intermediate frequency gain control module, the programmable intermediate frequency filter, the ADC receiver, the DAC transmitter, the programmable radio frequency gain module, the programmable filter array and the phase-locked loop through a serial interface; the ARM circuit provides an ETH interface for management for a user and is connected to the SWTICH;

n) the SWTICH circuit provides a high-speed SERDES interface for the FPGA circuit, the ARM circuit and the user respectively to realize the transmission of service data; providing a kilomega power port for a user to realize the transmission of management data;

o) a clock circuit which comprises a constant temperature crystal oscillator OCXO and a phase-locked loop PLL and generates various clock frequency signals which are provided for a DAC transmitter, an ADC receiver, an IQ demodulator and an FPGA circuit as reference clocks;

p) the interface circuit includes: 1) The data interface circuit adopts a fiber connector to transmit service data; 2) The management interface circuit adopts an RJ45 connector to transmit management data; the data interface circuit and the management interface circuit are respectively connected with the SWTICH circuit.

It is understood that the apparatus of the present disclosure includes all of the functional modules described above, or only some of the functional modules described above, such as:

1) The digital-to-analog converter comprises a band-pass filter, a gain module, an IQ demodulator, an ADC receiver and a DAC transmitter.

2) The digital-to-analog converter comprises a band-pass filter, a gain module, an IQ demodulator, a programmable intermediate frequency gain control module, an ADC receiver and a DAC transmitter.

3) The digital-to-analog converter comprises a band-pass filter, a gain module, an IQ demodulator, a programmable intermediate frequency gain control module, a programmable intermediate frequency filter, an ADC receiver and a DAC transmitter.

4) Including all functional modules and a first FPGA circuit in 1), 2) or 3).

5) Including 4) middle functional module and programmable RF gain control module and/or programmable filter array.

6) The FPGA-based touch control circuit comprises a 4) middle functional module, an ARM circuit, a second FPGA circuit and an SWTICH circuit.

In the disclosure, when the device is configured with the interface circuit, the ARM circuit and the second FPGA circuit, the device can be connected with an upper computer through the data interface circuit and the management interface circuit; the method comprises the steps of generating signal data to be sent through operation of an upper computer, inputting the signal data to be sent to an ARM circuit through a data interface circuit, inputting the signal data to be sent to a second FPGA circuit after being processed by the ARM circuit, coding and modulating the signal data to form a digital baseband signal to be sent, inputting the digital baseband signal to a DAC (digital-to-analog converter) transmitter, carrying out frequency conversion, converging (synthesizing a plurality of signals into one path of signal), sampling (digital-to-analog conversion) and outputting a radio frequency signal. Of course, the digital baseband signal to be transmitted input to the DAC transmitter may also be generated by other devices.

In addition, through the operation of the upper computer, a management instruction can be sent out and input into the ARM circuit through the management interface circuit, so that parameter configuration or working state control is performed on functional modules/devices such as an IQ demodulator, a programmable intermediate frequency gain control module, a programmable intermediate frequency filter, an ADC receiver, a DAC transmitter, a programmable radio frequency gain module, a programmable filter array and a PLL.

In the disclosure, when the device is configured with the first FPGA circuit connected to the ADC receiver, the data collected by the ADC may be demodulated and decoded, and may be directly input to the storage module for storage after being processed, so as to be read for use or stored; or the data processed by the first FPGA circuit is connected with an upper computer or other equipment through an SERDES interface and a data interface and is read and utilized.

The functional circuits/modules are laid out on the PCBA board, and as shown in fig. 2, the PCBA board includes the following components:

1) Connectors, SMA female connectors 1, 26 as a first RF interface and a second RF interface, an optical fiber connector 9 as a data interface circuit, a network connector 11 as a management interface circuit, and a power connector 16 for power supply access;

2) A circuit module: a constant temperature crystal oscillator 27 and a phase-locked loop 28 of a clock circuit, a programmable radio frequency gain module 23, a programmable filter array 25, a DAC transmitter 21, a BPF2, an RF gain module 3, an IQ demodulator 4, a programmable intermediate frequency gain module 5, a programmable intermediate frequency filter 6, an ADC receiver 7, an FPGA circuit including a first FPGA circuit 8, a second FPGA circuit 10, DDR circuits 18, 19, an ARM circuit 13, a SWITCH circuit 12 matched with the first FPGA circuit and the second FPGA circuit respectively, and power supply circuits 14, 15, 17, 20, 22, 24 connected with power supply connectors respectively. The power supply is connected to the device through the power supply connector, and the power supply circuit performs AC/DC and/or DC/DC conversion to generate a 3.3V power supply, a 5V power supply, a 12V power supply and the like to provide working voltage for each functional module/circuit.

The disclosed apparatus also includes a shield that is mounted on the upper portion of the PCBA, as shown in fig. 3. The shield and the main chip shown in fig. 2 are contacted together by a thermal conductive silicone pad and then fastened by screws.

The appearance of the shield cover of the present disclosure is shown in fig. 4 and 5, the shield cover is in the shape of a fin 16, and the shield cover body is provided with a power connector opening 31 for power connector assembly, a fiber connector opening 35 for fiber connector assembly, a network connector opening 36 for network connector assembly, a radio frequency connector opening for SMA female connector assembly, a fan 32, a boss 37 and a mounting hole 30.

In order to increase the radio frequency reliability of the device, the shielding case is further divided into a plurality of sub-cavities 34, the layout on the PCBA board enables radio frequency circuits (a DAC transmitter, a programmable radio frequency gain control module, a programmable filter array, an ADC receiver, an RF gain module, an IQ demodulator, a programmable intermediate frequency gain control module, a programmable intermediate frequency filter and the like), digital circuits (an ARM circuit, an FPGA circuit and the like) and a clock circuit to be respectively positioned in the different sub-cavities 34, so that the radio frequency circuits, the digital circuits and the clock circuit are isolated, and the radio frequency reliability of the device is increased.

This shield cover of disclosure adopts the fin and with main between the chip through heat conduction silica gel pad contact together, increased PCBA's heat dispersion.

The device provided by the utility model realize sampling totally 950MHz ~ 2150 MHz's broadband satellite signal, realized the broadband satellite signal transmission to 950MHz ~ 2150MHz, realize L frequency channel broadband signal reception and transmission with an equipment.

The above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and modifications or equivalent replacements made by those of ordinary skill in the art to the technical solutions of the present invention are all covered within the scope of the claims of the present invention as long as they do not depart from the spirit and scope of the technical solutions of the present invention.

Claims (10)

1. An apparatus for broadband satellite signal reception and transmission, the apparatus comprising:

the receiving module is used for receiving radio frequency signals and comprises a band-pass filter used for filtering useless signals, a gain module used for carrying out gain amplification on input radio frequency signals, an IQ demodulator used for carrying out quadrature decoding on the amplified radio frequency signals to obtain broadband intermediate frequency signals and an ADC receiver used for carrying out analog-to-digital conversion on the input intermediate frequency signals; the sampling rate of the ADC receiver is 5000Msps;

and the transmitting module comprises a DAC transmitter for performing digital-to-analog conversion on a video signal to be transmitted, and the sampling rate of the DAC transmitter is 12.6Gsps.

2. The apparatus of claim 1, wherein the receiving module further comprises a programmable if gain control module for gain amplifying or attenuating the if signal outputted from the IQ demodulator, and the programmable if gain control module comprises an if gain amplifier and a programmable attenuator.

3. The apparatus of claim 2, wherein the programmable if gain control module has an output coupled to a programmable if filter for filtering unwanted signals.

4. The apparatus of claim 1, wherein said receiving module further comprises a first FPGA circuit connected to said ADC receiver output for demodulating and decoding said ADC receiver output signal.

5. The apparatus of claim 1, wherein said transmitter module further comprises a programmable rf gain control module for gain amplifying or attenuating the rf signal output by said DAC transmitter, said programmable rf gain control module comprising an rf gain amplifier and a programmable attenuator.

6. The apparatus according to claim 5, wherein the programmable rf gain control module outputs are connected to a programmable filter array for filtering unwanted signals; including bandpass filters of various bandwidths.

7. The device for receiving and transmitting broadband satellite signals according to claim 1, wherein the transmitting module further comprises an ARM circuit, a second FPGA circuit for encoding and modulating data, and an SERDES interface for data transmission, the ARM circuit is respectively connected to the SERDES interface and the second FPGA circuit, an output end of the second FPGA circuit is electrically connected to an input end of the DAC transmitter, and the encoded and modulated data is input to the DAC transmitter as a radio frequency signal to be transmitted.

8. An apparatus for broadband satellite signal reception and transmission, the apparatus comprising:

the receiving module is used for receiving radio frequency signals and comprises a band-pass filter used for filtering useless signals, a gain module used for performing gain amplification on input radio frequency signals, an IQ demodulator used for performing quadrature decoding on the amplified radio frequency signals to obtain broadband intermediate frequency signals, an ADC receiver used for performing analog-to-digital conversion on the input intermediate frequency signals and a first FPGA circuit used for demodulating and decoding output signals of the ADC receiver; the ADC receiver sampling rate is 5000Msps;

the transmitting module comprises an ARM circuit, a second FPGA circuit electrically connected with the output end of the ARM circuit and a DAC transmitter electrically connected with the output end of the second FPGA circuit, and the sampling rate of the DAC transmitter is 12.6Gsps;

the SWITCH module comprises a first SERDES interface electrically connected with the output end of the first FPGA circuit and a second SERDES interface electrically connected with the input end of the ARM circuit;

the interface module comprises a data interface circuit and a management interface circuit which are respectively connected with the SWITCH module;

the clock module is used for generating various clock frequency signals, providing the clock frequency signals to the ADC receiver, the DAC transmitter, the IQ demodulator, the first FPGA circuit and the second FPGA circuit as reference clocks, and comprises a constant temperature crystal oscillator and a phase-locked loop;

the ARM circuit is further connected with the IQ demodulator, the ADC receiver, the DAC transmitter and the phase-locked loop respectively.

9. The apparatus for broadband satellite signal reception and transmission of claim 8, wherein the receiving module further comprises:

the programmable intermediate frequency gain control module is used for carrying out gain amplification or attenuation on the intermediate frequency signal output by the IQ demodulator and comprises an intermediate frequency gain amplifier and a programmable attenuator;

the programmable intermediate frequency filter is connected with the output of the programmable intermediate frequency gain control module and is used for filtering useless signals;

the programmable intermediate frequency gain control module and the programmable intermediate frequency filter are also respectively connected with the ARM circuit.

10. The apparatus for broadband satellite signal reception and transmission of claim 8, wherein the receiving module further comprises:

the programmable radio frequency gain control module is used for performing gain amplification or attenuation on the radio frequency signal output by the DAC transmitter and comprises a radio frequency gain amplifier and a programmable attenuator;

the programmable filter array is connected with the output of the programmable radio frequency gain control module and is used for filtering useless signals, and the programmable filter array comprises band-pass filters with various bandwidths;

the programmable radio frequency gain control module and the programmable filter array are also respectively connected with the ARM circuit.

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