CN218352519U - Switch control circuit - Google Patents
Switch control circuit Download PDFInfo
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- CN218352519U CN218352519U CN202222997012.9U CN202222997012U CN218352519U CN 218352519 U CN218352519 U CN 218352519U CN 202222997012 U CN202222997012 U CN 202222997012U CN 218352519 U CN218352519 U CN 218352519U
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Abstract
The application provides a switch control circuit, wherein, switch control circuit includes switch circuit and switching circuit, wherein, switch circuit's input is connected with the control end of treater, switch circuit's output is connected with switching circuit's enable end, switching circuit's first data transmission end is connected with the data transmission end of treater, switching circuit's second data transmission end is connected with the data transmission end of switch chip. This application is through the data transmission between switch circuit and the switching circuit control treater and the switch chip, direct connection between the treater and the switch that exist among the solution prior art, and it transmits the virus program to the switch chip to appear the virus easily through being connected between treater and the switch, has caused the problem of great network security hidden danger, reaches the relation of connection between control switch chip and the treater according to the demand, guarantees network security's effect.
Description
Technical Field
The application relates to the technical field of switch configuration, in particular to a switch control circuit.
Background
At present, with the technological progress, the internet of things and artificial intelligence are developed, the requirement on the network is higher and higher, the network is limited by a CPU, the number and the performance of network ports cannot meet the use requirement, more and more embedded products introduce a switch chip to expand the network ports, divide and manage the network and the like. The configuration of the switch chip is an important requirement.
However, the existing direct connection between the processor and the switch is easy to cause virus program transmission to the switch chip through the connection between the processor and the switch, which causes great network security hidden trouble.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the present application is to provide a switch control circuit, which can control data transmission between a processor and a switch chip through a switch circuit and a switching circuit, so as to solve the problem that the connection between the processor and the switch chip cannot be controlled according to the requirement in the prior art, and achieve the effect of controlling the connection relationship between the switch chip and the processor according to the requirement and ensuring network security.
In a first aspect, an embodiment of the present application provides a switch control circuit, the switch control circuit includes a switch circuit and a switching circuit, wherein, an input end of the switch circuit is connected with a control end of a processor, an output end of the switch circuit is connected with an enable end of the switching circuit, a first data transmission end of the switching circuit is connected with a data transmission end of the processor, and a second data transmission end of the switching circuit is connected with a data transmission end of a switch chip.
Optionally, the switch circuit includes a first voltage boosting sub-circuit, a field effect transistor, and a second voltage boosting sub-circuit, wherein, the source electrode of the field effect transistor is used as the input end of the switch circuit and is connected with the control end of the processor, the gate electrode of the field effect transistor is connected with the first power supply, the drain electrode of the field effect transistor is used as the output end of the switch circuit and is connected with the enable end of the adapter circuit, one end of the first voltage boosting sub-circuit is connected with the second power supply, the other end of the first voltage boosting sub-circuit is connected with the source electrode of the field effect transistor, one end of the second voltage boosting sub-circuit is connected with the third power supply, and the other end of the second voltage boosting sub-circuit is connected with the drain electrode of the field effect transistor.
Optionally, the first voltage boosting sub-circuit includes a first resistor, wherein one end of the first resistor is connected to a second power source as one end of the first voltage boosting sub-circuit, and the other end of the first resistor is connected to the source of the field effect transistor as the other end of the first voltage boosting sub-circuit.
Optionally, the second voltage boosting sub-circuit includes a second resistor, wherein one end of the second resistor is connected to a third power source as one end of the second voltage boosting sub-circuit, and the other end of the second resistor is connected to the drain of the field effect transistor as the other end of the second voltage boosting sub-circuit.
Optionally, the switch control circuit further includes a third voltage boost sub-circuit, wherein a first connection point is formed between the data transmission end of the processor and the first data transmission end of the adapter circuit, one end of the third voltage boost sub-circuit is connected to the first connection point, and the other end of the third voltage boost sub-circuit is connected to a fourth power supply.
Optionally, the third voltage boost sub-circuit includes a third resistor, where one end of the third resistor is connected to the first connection point as one end of the third voltage boost sub-circuit, and the other end of the third resistor is connected to a fourth power supply as the other end of the third voltage boost sub-circuit.
Optionally, the switch control circuit further includes a fourth voltage boosting sub-circuit, wherein one end of the fourth voltage boosting sub-circuit is connected to the data transmission end of the switch chip, the other end of the fourth voltage boosting sub-circuit is connected to the second data transmission end of the switching circuit, a second connection point is formed between the other end of the fourth voltage boosting sub-circuit and the second data transmission end of the switching circuit, and the second connection point is connected to a fifth power supply.
Optionally, the fourth voltage boosting sub-circuit includes a fourth resistor, where one end of the fourth resistor is connected to the data transmission terminal of the switch chip as one end of the fourth voltage boosting sub-circuit, the other end of the fourth resistor is connected to the second data transmission terminal of the switching circuit as the other end of the fourth voltage boosting sub-circuit, a second connection point is formed between the other end of the fourth resistor and the data transmission terminal of the processor, and the second connection point is connected to a fifth power supply.
Optionally, the switch control circuit further includes a tank filter circuit, wherein one end of the tank filter circuit is connected to the second connection point, and the other end of the tank filter circuit is grounded.
Optionally, a clock transmission end of the processor is connected to a first clock transmission end of the switching circuit, and a second clock transmission end of the switching circuit is connected to a clock transmission end of the switch chip.
The switch control circuit that this application embodiment provided can control data transmission between treater and the switch chip through switch circuit and switching circuit, solves that the unable control of being connected between treater and the switch chip according to the demand that exists among the prior art, reaches the relation of connection between switch chip and the treater according to demand control, guarantees network security's effect.
In order to make the aforementioned objects, features and advantages of the present application comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a first schematic diagram of a switch control circuit according to an embodiment of the present disclosure;
fig. 2 is a second schematic diagram of a switch control circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. Every other embodiment that can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present application falls within the protection scope of the present application.
First, an application scenario to which the present application is applicable will be described. The method and the device can be applied to the technical field of switch configuration.
Research shows that with the technological progress, the development of the internet of things and artificial intelligence, the requirement on the network is higher and higher, the requirement is limited by a CPU, the number and the performance of network ports cannot meet the use requirement, more and more embedded products are introduced into a switch chip to expand the network ports, divide and manage the network and the like. The configuration of the switch chip is an important requirement.
However, the existing direct connection between the processor and the switch is easy to cause virus program transmission to the switch chip through the connection between the processor and the switch, which causes great network security hidden trouble.
Based on this, the embodiment of the application provides a switch control circuit, can control data transmission between processor and the switch chip through switch circuit and switching circuit, solve the unable connection between processor and the switch chip of controlling according to the demand that exists among the prior art, reach the connected relation between switch chip and the processor of controlling according to the demand, guarantee the effect of network security.
Referring to fig. 1, fig. 1 is a first schematic diagram of a switch control circuit according to an embodiment of the present disclosure. As shown in fig. 1, a schematic diagram of a switch control circuit provided in an embodiment of the present application includes: processor 101, switching circuit 102, switching circuit 103, switch chip 104.
The input end of the switch circuit 102 is connected to the control end of the processor 101, and the output end of the switch circuit 102 is connected to the enable end of the switching circuit 103.
A first data transmission terminal of the switching circuit 103 is connected to a data transmission terminal of the processor 101, and a second data transmission terminal of the switching circuit 103 is connected to a data transmission terminal of the switch chip 104.
Illustratively, when the processor 101 needs to configure the switch chip 104, the switch circuit 102 controls the switch circuit 103, so that the switch circuit 103 receives the switch configuration file received from the data transmission end of the processor 101 through the first data transmission end and transmits the switch configuration file received from the processor 101 to the switch chip 104, after a preset time, the processor 101 may further read the configuration information of the switch chip 104 through the switch circuit 103, and when it is determined that the current configuration information of the switch chip 104 is consistent with the configuration information in the configuration file, the switch control circuit controls the switch circuit 103, and data transmission between the processor 101 and the switch chip 104 is no longer allowed.
Referring to fig. 2, fig. 2 is a second schematic diagram of a switch control circuit according to an embodiment of the present disclosure. As shown in fig. 2, a second schematic diagram of a switch control circuit provided in the embodiment of the present application includes: processor 101, switching circuit 103, switch chip 104, first power VCC1, second power VCC2, third power VCC3, fourth power VCC4, fifth power VCC5, sixth power VCC6, seventh power VCC7, first resistance R1, second resistance R2, third resistance R3, fourth resistance R4, field effect transistor Q2, energy storage filter circuit 202, wherein, energy storage filter circuit 202 includes: the capacitor comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a fifth capacitor C5.
Illustratively, the first power supply VCC1, the second power supply VCC2, the third power supply VCC3, and the fourth power supply VCC4 may be 3.3 volt power supplies provided by the processor. The fifth power source VCC5 may be an external 2.7 v power source.
Specifically, switch circuit 102 includes first voltage promotion sub-circuit, field effect transistor Q2, second voltage promotion sub-circuit, wherein, field effect transistor Q2's source electrode conduct switch circuit 102's input with processor 101's control end is connected, field effect transistor Q2's grid and first power VCC1 are connected, field effect transistor Q2's drain electrode conduct switch circuit 102's output with switching circuit 103's enable end is connected, the one end of first voltage promotion sub-circuit is connected with second power VCC2, the other end of first voltage promotion sub-circuit with field effect transistor Q2's source electrode is connected, the one end of second voltage promotion sub-circuit is connected with third power VCC3, the other end of second voltage promotion sub-circuit with field effect transistor Q2's drain electrode is connected.
Illustratively, when the control terminal of the processor 101 outputs a low level signal, the gate of the field effect transistor Q2 receives the low level signal, and at this time, the source and the drain of the field effect transistor Q2 are turned on, and the drain of the field effect transistor Q2 outputs a high level signal to the enable terminal of the through circuit 103, so as to control the through circuit 103 to allow data transmission between the processor 101 and the switch chip 104; when the control end of the processor 101 outputs a high level signal, the gate of the field effect transistor Q2 receives the high level signal, at this time, the source and the drain of the field effect transistor Q2 are disconnected, the drain of the field effect transistor Q2 outputs a low level signal to the enable end of the switching circuit 103, and the switching circuit 103 is controlled to disconnect the data transmission between the processor 101 and the switch chip 104.
For example, the switch chip may be of a model QCA8334, the function of the switch circuit 103 may be implemented by a logic circuit, or may be implemented by a switch chip of a model UM3202Q, and the processor may be an ARM CPU. The control terminal of the processor 101 may be a P2.0 (A8) pin of an ARM CPU, the enable terminal of the adaptor circuit may be an OE pin of an adaptor chip UM3202Q, the adaptor chip allows a P3.0 (MDIO) and a P3.1 (MDC) pins of the processor to pass through the A1 and A2 pins of the adaptor chip when the enable terminal OE receives a high level signal, the B1 and B2 pins are switched to UART _ TXD and UART _ RXD pins of the switch chip, so that data transmission is performed between the P3.0 (MDIO) and P3.1 (MDC) pins of the processor and the UART _ TXD and UART _ RXD pins of the switch chip, when the adaptor chip receives a low level signal at the enable terminal, the adaptor chip no longer performs a data transmission function, so that the data transmission between the P3.0 (MDIO) and P3.1 (MDC) pins of the processor and the UART _ TXD and UART _ RXD pins of the switch chip cannot perform a data transmission function, so that the data transmission between the adaptor chip and the switch chip cannot be performed after the adaptor chip receives a low level signal, and the data transmission between the adaptor chip cannot be performed, so that a network exchange can be performed after the data transmission between the processor is disconnected, and the switch chip can be performed, and the switch can be guaranteed.
Optionally, a VCCA pin of the transit chip of the model UM3202Q is connected to the sixth power VCC6, and a VCCB pin of the transit chip of the model UM3202Q is connected to the seventh power VCC7. Here, the sixth power source may be connected to a 3.3 volt power source, and the seventh power source may be connected to a 2.7 volt power source to supply power to the adaptor chip.
One end of the fourth capacitor C4 is connected to the sixth power VCC6, the other end of the fourth capacitor C4 is grounded, one end of the fifth capacitor C5 is connected to the seventh power VCC7, and the other end of the fifth capacitor C5 is grounded.
Specifically, the first voltage boost sub-circuit includes a first resistor R1, wherein, the one end of the first resistor R1 is used as the one end of the first voltage boost sub-circuit is connected with a second power VCC2, the other end of the first resistor R1 is used as the other end of the first voltage boost sub-circuit and the source electrode of the field effect transistor Q2 is connected.
Specifically, the second voltage boost sub-circuit includes a second resistor R2, wherein, one end of the second resistor R2 is used as one end of the second voltage boost sub-circuit to be connected with a third power VCC3, and the other end of the second resistor R2 is used as the other end of the second voltage boost sub-circuit to be connected with the drain electrode of the field effect transistor Q2.
Optionally, the switch control circuit further includes a third voltage boosting sub-circuit, wherein a first connection point is formed between the data transmission end of the processor 101 and the first data transmission end of the switching circuit 103, one end of the third voltage boosting sub-circuit is connected to the first connection point, and the other end of the third voltage boosting sub-circuit is connected to the fourth power VCC 4.
Specifically, referring to fig. 2, the third voltage boost sub-circuit includes a third resistor R3.
Illustratively, one end of the third resistor R3 is connected to the first connection point as one end of the third voltage boosting sub-circuit, and the other end of the third resistor R3 is connected to a fourth power VCC4 as the other end of the third voltage boosting sub-circuit.
Optionally, the switch control circuit further comprises a fourth voltage boost sub-circuit.
Illustratively, one end of the fourth voltage boosting sub-circuit is connected to the data transmission terminal of the switch chip 104, the other end of the fourth voltage boosting sub-circuit is connected to the second data transmission terminal of the switch circuit 103, a second connection point is formed between the other end of the fourth voltage boosting sub-circuit and the second data transmission terminal of the switch circuit 103, and the second connection point is connected to a fifth power source VCC 5.
Specifically, referring to fig. 2, the fourth voltage boosting sub-circuit includes a fourth resistor R4.
Illustratively, one end of the fourth resistor R4 is used as one end of the fourth voltage boosting sub-circuit to be connected to the data transmission end of the switch chip 104, the other end of the fourth resistor R4 is used as the other end of the fourth voltage boosting sub-circuit to be connected to the second data transmission end of the switch circuit 103, a second connection point is formed between the other end of the fourth resistor R4 and the data transmission end of the processor 101, and the second connection point is connected to a fifth power source VCC 5.
Optionally, referring to fig. 2, the switch control circuit further includes a tank filter circuit 202.
Illustratively, one end of the tank filter circuit 202 is connected to the second connection point, and the other end of the tank filter circuit 202 is grounded.
Specifically, the energy storage filter circuit 202 includes a first capacitor C1, a second capacitor C2 and a third capacitor C3, wherein one end of the third capacitor C3 is connected to the second connection point, the other end of the third capacitor C3 is grounded, one end of the second capacitor C2 is connected to one end of the third capacitor C3, the other end of the second capacitor C2 is connected to the other end of the third capacitor C3, one end of the first capacitor C1 is connected to one end of the second capacitor C2, and the other end of the first capacitor C1 is connected to the other end of the second capacitor C2.
Thus, stability of data input or output from the data transmission side of the switch chip 104 is ensured.
Optionally, a clock transmission terminal of the processor 101 is connected to a first clock transmission terminal of the switch circuit 103, and a second clock transmission terminal of the switch circuit 103 is connected to a clock transmission terminal of the switch chip 104.
Thus, the processor and the chip can work normally under the condition that no external clock/crystal oscillator input exists.
The switch control circuit that this application embodiment provided, can be through the data transmission between switch circuit and the switching circuit control treater and the switch chip, it transmits the configuration file to the switch chip to solve the difficult according to the demand that exists among the prior art when needing to dispose the switch, and close the data transmission of switch and treater after the configuration is accomplished, the problem of great network security hidden danger has been caused, reach the relation of connection between switch chip and the treater according to demand control, guarantee network security's effect.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present application and are intended to be covered by the appended claims. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A switch control circuit is characterized in that the switch control circuit comprises a switch circuit and a switching circuit,
wherein, the input end of the switch circuit is connected with the control end of the processor, the output end of the switch circuit is connected with the enable end of the switching circuit,
and a first data transmission end of the switching circuit is connected with a data transmission end of the processor, and a second data transmission end of the switching circuit is connected with a data transmission end of the switch chip.
2. The switch-control circuit of claim 1, wherein the switch circuit comprises a first voltage-boosting sub-circuit, a field-effect transistor, a second voltage-boosting sub-circuit,
the source electrode of the field effect tube is used as the input end of the switch circuit and connected with the control end of the processor, the grid electrode of the field effect tube is connected with the first power supply, the drain electrode of the field effect tube is used as the output end of the switch circuit and connected with the enabling end of the switching circuit, one end of the first voltage boosting sub-circuit is connected with the second power supply, the other end of the first voltage boosting sub-circuit is connected with the source electrode of the field effect tube, one end of the second voltage boosting sub-circuit is connected with the third power supply, and the other end of the second voltage boosting sub-circuit is connected with the drain electrode of the field effect tube.
3. The switch control circuit of claim 2, wherein the first voltage boost sub-circuit comprises a first resistor,
one end of the first resistor is used as one end of the first voltage boosting sub-circuit and is connected with a second power supply, and the other end of the first resistor is used as the other end of the first voltage boosting sub-circuit and is connected with a source electrode of the field effect transistor.
4. The switch control circuit of claim 2, wherein the second voltage boost sub-circuit comprises a second resistor,
one end of the second resistor is used as one end of the second voltage boosting sub-circuit and connected with a third power supply, and the other end of the second resistor is used as the other end of the second voltage boosting sub-circuit and connected with the drain electrode of the field effect transistor.
5. The switch control circuit of claim 1, further comprising a third voltage boost sub-circuit,
a first connection point is formed between the data transmission end of the processor and the first data transmission end of the switching circuit, one end of the third voltage boosting sub-circuit is connected to the first connection point, and the other end of the third voltage boosting sub-circuit is connected with a fourth power supply.
6. The switch control circuit of claim 5, wherein the third voltage boost sub-circuit comprises a third resistor,
one end of the third resistor is connected to the first connection point as one end of the third voltage boosting sub-circuit, and the other end of the third resistor is connected to a fourth power supply as the other end of the third voltage boosting sub-circuit.
7. The switch control circuit of claim 1, further comprising a fourth voltage boost sub-circuit,
one end of the fourth voltage boosting sub-circuit is connected with the data transmission end of the switch chip, the other end of the fourth voltage boosting sub-circuit is connected with the second data transmission end of the switching circuit, a second connection point is formed between the other end of the fourth voltage boosting sub-circuit and the second data transmission end of the switching circuit, and the second connection point is connected with a fifth power supply.
8. The switch control circuit of claim 7, wherein the fourth voltage boost sub-circuit comprises a fourth resistor,
one end of the fourth resistor is used as one end of the fourth voltage boosting sub-circuit and connected with the data transmission end of the switch chip, the other end of the fourth resistor is used as the other end of the fourth voltage boosting sub-circuit and connected with the second data transmission end of the switching circuit, a second connection point is formed between the other end of the fourth resistor and the data transmission end of the processor, and the second connection point is connected with a fifth power supply.
9. The switch control circuit of claim 7, further comprising a tank filter circuit,
one end of the energy storage filter circuit is connected with the second connection point, and the other end of the energy storage filter circuit is grounded.
10. The switch control circuit of claim 1, wherein the clock terminal of the processor is coupled to the first clock terminal of the patching circuit, and the second clock terminal of the patching circuit is coupled to the clock terminal of the switch chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222997012.9U CN218352519U (en) | 2022-11-10 | 2022-11-10 | Switch control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222997012.9U CN218352519U (en) | 2022-11-10 | 2022-11-10 | Switch control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218352519U true CN218352519U (en) | 2023-01-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222997012.9U Active CN218352519U (en) | 2022-11-10 | 2022-11-10 | Switch control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218352519U (en) |
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2022
- 2022-11-10 CN CN202222997012.9U patent/CN218352519U/en active Active
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