CN218335720U - Power management system for domain controller - Google Patents

Abstract

Embodiments of the present disclosure disclose a power management system for a domain controller. One embodiment of the power management system comprises: the power input circuit is connected with a power input pin of the power management chip and used for providing voltage input; the power output circuits are connected with the power output pins of the power management chip in a one-to-one correspondence manner, so that a plurality of paths of power supplies are provided; the power supply wake-up circuit is connected with a wake-up pin of the power supply management chip; the power supply reset circuit is connected with a reset pin of the power supply management chip; the power supply safe state signal output circuit is connected with the safe state pin of the power supply management chip and is used for controlling the on-off of the corresponding output power supply. The embodiment realizes the output of multiple power supplies and also improves the safety.

Description

Power management system for domain controller

Technical Field

The embodiment of the disclosure relates to the technical field of domain controllers, in particular to a power management system for a domain controller.

Background

With the mass information flow brought by the intelligent networking of the automobile, perception, decision and control systems related to automobile driving are more and more complex, and all the systems can normally work only by supplying energy to the power supply, so that the types of the power supply are more. Power management systems become particularly important.

The related power management chip system is generally single, and therefore, the following technical problems exist:

first, the types of voltages output by the power management chip are few, and it is difficult to satisfy various power requirements of various systems.

Second, the safety level is low and cannot be controlled in time when a certain output voltage fails.

SUMMERY OF THE UTILITY MODEL

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

Some embodiments of the present disclosure propose a power management system for a domain controller to solve one or more of the technical problems mentioned in the background section above.

The system comprises: the power supply comprises a power supply management chip, a power supply input circuit, a plurality of power supply output circuits, a power supply wake-up circuit, a power supply reset circuit and a power supply safety state signal output circuit, wherein the power supply input circuit is connected with a power supply input pin of the power supply management chip and is used for providing voltage input; the power output circuits are connected with the power output pins of the power management chip in a one-to-one correspondence manner, so that a plurality of paths of power supplies are provided; the power supply wake-up circuit is connected with a wake-up pin of the power supply management chip and used for sending a wake-up signal to enable the power supply management chip to output voltage; the power supply reset circuit is connected with the reset pin of the power supply management chip and is used for controlling the power supply management chip to reset the power supply; the power supply safe state signal output circuit is connected with the safe state pin of the power supply management chip and is used for controlling the on-off of the corresponding output power supply according to the power supply safe state signal output by the power supply management chip.

The above embodiments of the present disclosure have the following advantages: through the power management system for the domain controller of some embodiments of the present disclosure, multiple paths of power outputs can be provided, and the power supply requirements of various systems can be met. Specifically, the reason why the related power management chip is difficult to satisfy the power supply requirements of various systems is that: the output voltage of the related power management chip is single. Based on this, the power management system for a domain controller of some embodiments of the present disclosure includes a power management chip, a power input circuit, and a power output circuit. The power input circuit may input a wide voltage, and the power management chip may be a chip having multiple power outputs, and may further provide multiple power outputs through a dc-dc converter, so as to supply power to an MCU (micro controller Unit), a transceiver, a sensor, and the like. Therefore, various voltages can be flexibly provided, and the power supply requirements of a plurality of systems are met.

In addition, the power supply wake-up circuit and the power supply reset circuit can wake up and reset the power supply, and the control capability of the system is improved.

Finally, the power supply safety state signal output circuit can send high-level or low-level signals according to monitoring of the output power supply, so that the on-off of the output power supply is realized, and the safety and the reliability of the system are improved.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numbers refer to the same or similar elements. It should be understood that the drawings are schematic and that elements and features are not necessarily drawn to scale.

FIG. 1 is a schematic block diagram of some embodiments of a power management system for a domain controller according to the present disclosure;

FIG. 2 is a schematic block diagram of some embodiments of a power input circuit according to the present disclosure;

FIG. 3 is a schematic block diagram of some embodiments of a first power output circuit according to the present disclosure;

FIG. 4 is a schematic block diagram of some embodiments of a second power output circuit according to the present disclosure;

FIG. 5 is a schematic block diagram of some embodiments of a power wake-up circuit according to the present disclosure;

FIG. 6 is a schematic block diagram of some embodiments of a power reset circuit according to the present disclosure;

FIG. 7 is a schematic block diagram of some embodiments of a power supply safety state signal output circuit according to the present disclosure;

fig. 8 is a schematic block diagram of further embodiments of a power supply safety state signal output circuit according to the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings. The embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

It should be noted that the terms "first", "second", and the like in the present disclosure are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.

It is noted that references to "a", "an", and "the" modifications in this disclosure are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that "one or more" may be used unless the context clearly dictates otherwise.

The names of messages or information exchanged between devices in the embodiments of the present disclosure are for illustrative purposes only, and are not intended to limit the scope of the messages or information.

The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring first to fig. 1, fig. 1 is a schematic structural diagram of some embodiments of a power management system for a domain controller according to the present disclosure. As shown in fig. 1, the system includes a power management chip 1, a power input circuit 2, a plurality of power output circuits, a power wake-up circuit 4, a power reset circuit 5, and a power safe state signal output circuit 6.

Specifically, the power management chip 1 includes a power input pin connection, a plurality of power output pins, a wake-up pin, a reset pin, and a safe state pin. The power input circuit 2 is connected to a power input pin. The plurality of power output circuits are connected with the plurality of power output pins of the power management chip in a one-to-one correspondence manner. The power wake-up circuit 4 is connected to the wake-up pin. The power supply reset circuit 5 is connected to the reset pin. The power supply safety state signal output circuit 6 is connected to the safety state pin.

The power management chip 1 has a function of outputting multiple power sources, and can provide multiple power outputs. Although fig. 1 shows the power supply output pin 1, the power supply output pin 2, and the power supply output pin 3 as an example, this is not exclusive, and a plurality of power supply output pins may be provided. Similarly, although fig. 1 shows the power output circuits 1, 2, and 3 as an example, those skilled in the art can adjust the number of power output circuits according to actual circumstances.

For example, the power management chip 1 may be a tff 35584QVVS2 chip of the british flying, or may be one of a tff 35584QVVS1 chip, a tff 35584QKVS1 chip, and a tff 35584QKVS2 chip.

Referring next to fig. 2, fig. 2 is a schematic diagram of a power input circuit according to some embodiments of the present disclosure. As shown in fig. 2, the power input circuit 2 includes an input terminal inductor L1 and an input terminal diode D1 connected in series with an external power source. The cathode of the input terminal diode D1 is connected to the power input pin. The inductor L1 performs a filtering function in the power input circuit 2. The input end diode D1 plays a role in one-way conduction based on self characteristics. Further, the power input circuit 2 further includes a plurality of input capacitors. Two input end capacitors C01 and C02 may be provided between the positive electrode terminal of the inductor L1 and the power input pin in parallel. Two input-side capacitors C03 and C04 are provided in parallel to the negative terminal of the input-side diode D1 and grounded. The number of the input end capacitors can be adjusted according to actual conditions. The input end capacitor plays a role in filtering.

The power output circuit may include one or more first power output circuits and/or one or more second power output circuits. Next, the first power supply output circuit will be described with reference to fig. 3. Fig. 3 is a schematic block diagram of some embodiments of a first power output circuit according to the present disclosure. As shown in fig. 3, the first power output circuit 31 includes an output inductor L2, a dc-dc converter (not shown), and two first power output capacitors C05 and C06. The output inductor L2 is connected to the first power output pin, and the number of the first power output pins may be one or more. The adjustment can be made by those skilled in the art according to actual needs. The dc-dc converter is connected in series with the output inductor L2. The output inductor L2 is used for filtering. The dc-dc converter is configured such that the first power output end capacitors C05 and C06 are connected in parallel to the negative electrode of the output end inductor L2. The number of the first power output circuit 31 and the number of the first power output terminal capacitors may be adjusted according to actual conditions. Therefore, the power output 1 of the adaptive voltage can be directly provided for the MCU through the conversion of the DC/DC converter.

Next, the second power supply output circuit will be described with reference to fig. 4. Fig. 4 is a schematic block diagram of some embodiments of a second power output circuit according to the present disclosure. As shown in fig. 4, the second power output circuit 32 is connected to a second power output pin. The second power supply output pin may be one or more. Each second power supply output pin may provide a different power supply output. Further, the second power output circuit 32 further includes second power output end capacitors C07, C08, C09, and C10. The second power supply output terminal capacitor is connected in parallel with the second power supply output pin. The number of the second power output circuit 32 and the number of the second power output terminal capacitors may be adjusted according to actual conditions. In this way, the second power output pins can provide voltages and currents of various specifications, and directly provide power output 1 and power output 2 for sensors, buses and the like through the filtering effect of the second power output end capacitor.

Referring next to fig. 5, fig. 5 is a schematic diagram of some embodiments of a power wake-up circuit according to the present disclosure. The power wake-up circuit 4 includes wake-up end voltage dividing resistors R01 and R02 and a wake-up end diode D2. The wake-up end diode D2 is connected in parallel with the wake-up end voltage-dividing resistor R02 and grounded. And the R02 cathode of the awakening end divider resistor is connected to the awakening pin of the power management chip. The wake-up diode D2 plays a role in voltage stabilization. In a working state, an external power supply triggers a wake-up signal through the wake-up end voltage dividing resistors R01 and R02 and the wake-up end diode D2, so that the power management chip 1 outputs voltage. If the external power is turned off, the power management chip 1 has no power output. And then the on-off of the output voltage is realized.

Referring next to fig. 6, fig. 6 is a schematic diagram of some embodiments of a power reset circuit according to the present disclosure. As shown in fig. 6, the power supply reset circuit 5 includes a reset terminal pull-up resistor R03 and a reset terminal capacitor C11. The reset signal is pulled up by the voltage of the reset terminal pull-up resistor R03 and connected to the reset pin of the power management chip 1. The reset terminal capacitor C11 is connected in parallel to the reset terminal pull-up resistor R03, and is used for jitter elimination of signals. In response to the reset signal being high, the system operates normally. And responding to the low level of the reset signal, and resetting the power supply by the reset pin after the preset time. It should be noted that the preset time may be set by a technician according to actual situations.

Referring next to fig. 7, fig. 7 is a schematic diagram of some embodiments of a power safety state signal output circuit according to the present disclosure. As shown in fig. 7, the power supply safe state signal output circuit 6 includes a first MOS Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) M1, a second MOS Transistor M2, a third MOS Transistor M3, and a fourth MOS Transistor M4 connected in series with the safe state pin of the power management chip 1. The first MOS transistor M1 and the third MOS transistor M3 are N-channel MOS transistors, and the second MOS transistor M2 and the fourth MOS transistor M4 are P-channel MOS transistors. The drain of the second MOS transistor M2 is connected to a first external enable signal, and the drains of the first MOS transistor M1 and the third MOS transistor M3 are grounded. And the source electrode of the fourth MOS tube is connected with an output power supply. The first external enable signal is sent out by an external MCU.

When the power supply safety state signal output by the safety state pin is high level and the first external enable signal is high level, the grid of the first MOS transistor M1 is high level, the source of the first MOS transistor M1 is grounded, VGS (voltage of the grid relative to the source) is greater than 0, and the first MOS transistor M1 is turned on and reaches the grid of the second MOS transistor M2. Since the first external enable signal is at a high level and is connected to the source of the second MOS transistor M2, VGS is less than 0, and the second MOS transistor M2 is turned on. Next, the source of the third MOS transistor M3 is grounded, such that VGS > 0, and the third MOS transistor M3 is turned on. Finally, the source electrode of the fourth MOS transistor M4 is externally connected with an external power supply, and VGS is less than 0, so that the fourth MOS transistor M4 is turned on, and further, a power supply is output.

The power supply safety state signal output by the safety state pin in the standby, sleep, shutdown, interrupt, wake-up and fault modes is at a low level, and at this time, no matter the first external enable signal outputs a high level or a low level, the fourth MOS transistor M4 is turned off. Specifically, when the power source safety state signal is at a low level and the first external enable signal is at a high level, the gate of the first MOS transistor M1 is connected to the first external enable signal, so that the gate voltage of the first MOS transistor M1 is higher, and the current is difficult to flow to the second MOS transistor M2. When the first external enable signal is at a low level, VGS > 0, so that the second MOS transistor M2 is turned off. Thereby controlling the output of the power supply.

Furthermore, three voltage dividing resistors R05, R07 and R09 may be connected in parallel to the first MOS transistor M1, the second MOS transistor M2 and the fourth MOS transistor M4. And voltage dividing resistors R04 and R08 connected in series with the first MOS transistor M1 and the third MOS transistor M3. And then make the VGS of first MOS pipe M1, second MOS pipe M2, third MOS pipe M3 and fourth MOS pipe M4 satisfy above-mentioned process in the work for this system is more accurate reliable.

The technical scheme is taken as an invention point of the embodiment of the disclosure, and solves the technical problem two mentioned in the background art that the safety level is low, and timely control cannot be performed when a certain output voltage fails. Factors that contribute to a low level of security for the associated power management system tend to be as follows: the output of the power supply cannot be controlled when the power supply fails or fails. If the above factors are solved, the effect of improving the safety level can be achieved. In order to achieve the effect, four MOS tubes M1, M2, M3 and M4 and a plurality of divider resistors are introduced in the disclosure. Therefore, in a normal working state, the power supply safety state signal is at a high level, and when the first external enable signal is at a high level, the fourth MOS transistor M4 is turned on, so as to output the power supply. When the power supply has faults such as short circuit, overload and the like, the power supply safety state signal is at a low level, and at the moment, no matter the external MCU sends a first external enabling signal at a high level or a low level, the fourth MOS transistor M4 is disconnected. The control of the rear-end output power supply is realized. The safety and reliability of the system are improved.

Referring next to fig. 8, fig. 8 is a schematic structural diagram of another embodiment of a power safety status signal output circuit according to the present disclosure. As shown in fig. 8, the power source safety state signal output circuit 6 includes a common anode diode D3, two input terminals of the common anode diode D3 are respectively connected to the power source safety state pin and the second external enable signal, and an output terminal of the common anode diode D3 is connected to the rear power management chip. And when the power supply safety state signal output by the response safety state pin and the second external enable signal are in high level, the rear-end power supply management chip works normally. And responding to the power supply safety state signal to monitor that the rear-end power supply management chip has a fault, outputting the power supply safety state signal to be a low level, and shutting down the rear-end power supply management chip at the moment. Therefore, the effective control of the rear-end power management chip is realized.

The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the embodiments of the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is made without departing from the inventive concept as defined above. For example, the above features and (but not limited to) the features with similar functions disclosed in the embodiments of the present disclosure are mutually replaced to form the technical solution.

Claims (8)

1. A power management system for a domain controller, comprising: a power management chip, a power input circuit, a plurality of power output circuits, a power wake-up circuit, a power reset circuit, a power safe state signal output circuit,

the power input circuit is connected with a power input pin of the power management chip and is used for providing voltage input;

the power output circuits are connected with the power output pins of the power management chip in a one-to-one correspondence manner, so that a plurality of paths of power supplies are provided;

the power supply wake-up circuit is connected with a wake-up pin of the power supply management chip and used for sending a wake-up signal to enable the power supply management chip to output voltage;

the power supply reset circuit is connected with a reset pin of the power supply management chip and is used for controlling the power supply management chip to reset the power supply;

the power supply safe state signal output circuit is connected with the safe state pin of the power supply management chip and used for controlling the on-off of the corresponding output power supply according to the power supply safe state signal output by the power supply management chip.

2. The power management system for domain controllers according to claim 1, wherein said power input circuit comprises an input terminal inductor and an input terminal diode connected in series with an external power source, the cathode of said input terminal diode being connected to the power input pin of said power management chip, wherein a plurality of input terminal capacitors are connected in parallel between the anode of said input terminal inductor and the cathode of said input terminal diode.

3. The power management system for a domain controller of claim 1, wherein said power output circuits comprise one or more first power output circuits, wherein said first power output circuits comprise an output inductor, a dc-dc converter and a first power output capacitor, said output inductor is connected to a first power output pin of said power management chip, said dc-dc converter is connected in series with said output inductor, and said first power output capacitor is connected in parallel to a negative pole of said output inductor.

4. The power management system for a domain controller of claim 1, wherein said power output circuits further comprise one or more second power output circuits comprising a second power output terminal capacitance connected in parallel to a second power output pin of said power management chip and connected to ground.

5. The power management system of claim 1, wherein the power wake-up circuit comprises a wake-up end divider resistor and a wake-up end diode, wherein the wake-up end diode is connected in parallel with the wake-up end divider resistor to ground, and a negative electrode of the wake-up end divider resistor is connected to a wake-up pin of the power management chip.

6. The power management system of claim 1, wherein the power reset circuit comprises a reset pull-up resistor and a reset capacitor, and a reset signal is pulled up by a voltage of the reset pull-up resistor and connected to a reset pin of the power management chip, wherein the reset capacitor is connected in parallel with the reset pull-up resistor and the reset pin performs a reset of the power supply in response to the reset signal being at a low level.

7. The power management system of any of claims 1-6, wherein the power safety status signal output circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor connected in series to the safety status pin of the power management chip, wherein the first MOS transistor and the third MOS transistor are N-channel MOS transistors, the second MOS transistor and the fourth MOS transistor are P-channel MOS transistors, a drain of the second MOS transistor is connected to a first external enable signal, drains of the first MOS transistor and the third MOS transistor are grounded, and a source of the fourth MOS transistor is connected to an output power supply, and the output power supply is connected when the power safety status signal output by the safety status pin is at a high level and the first external enable signal is at a high level.

8. The power management system of claim 1, wherein the power safety state signal output circuit comprises a diode, two input terminals of the diode are respectively connected to the power safety state pin and the second external enable signal, an output terminal of the diode is connected to the back-end power management chip, and the back-end power management chip operates normally when the power safety state signal output from the safety state pin and the second external enable signal are high level.

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