CN218274567U - DFN packaging structure for leading back electrode of semiconductor chip to front side - Google Patents
DFN packaging structure for leading back electrode of semiconductor chip to front side Download PDFInfo
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- CN218274567U CN218274567U CN202222872945.5U CN202222872945U CN218274567U CN 218274567 U CN218274567 U CN 218274567U CN 202222872945 U CN202222872945 U CN 202222872945U CN 218274567 U CN218274567 U CN 218274567U
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Abstract
The utility model discloses a DFN packaging structure for leading a back electrode of a semiconductor chip to the front, which belongs to the technical field of semiconductor packaging and sequentially comprises a plastic packaging layer, a first dielectric layer, a second dielectric layer and a bonding pad from bottom to top; a chip and a conductive block are packaged in the plastic packaging layer, and a back electrode of the chip is bonded with the conductive block; the first medium layer is positioned on the plastic package layer on the front surface of the chip, wiring layers are formed in the first medium layer and the second medium layer, and the front surface electrode and the conductive block of the chip are bonded with the bonding pad through the wiring layers. The utility model leads out the back electrode to the front side through the conductive block and the wiring layer to form DFN packaging, and the whole structure does not need to adopt a high copper column, thereby reducing the process complexity on one hand, reducing the packaging volume on the other hand, and having small packaging area and low manufacturing cost; meanwhile, the back electrode is bonded with the conductive block, so that parasitic resistance can be effectively reduced.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a semiconductor chip back electrode draws forth to positive DFN packaging structure.
Background
The latest surface mount package technology of DFN (Dual Flat No-lead package) adopts advanced double-sided or square Flat lead-free package, has higher flexibility, and is widely applied to the design and assembly process of mounting pads, solder masks and templates of Printed Circuit Boards (PCBs).
At present, the DFN packaging method for simultaneously forming the front surface and the back surface of a chip on a metal electrode generally pastes the back surface of the chip on a lead frame, then the front surface electrode is led out by a routing method, the area of a packaging body formed by the method is large, and the lead bonding of the front surface is unfavorable for the parasitic resistance of a packaging structure; in addition, the back electrode of the chip is led out to the front side by adopting a copper column mode, the process is complex, and the cost for manufacturing the large-size copper column is high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art's problem, provide a semiconductor chip back electrode and draw forth to positive DFN packaging structure.
The purpose of the utility model is realized through the following technical scheme: a DFN packaging structure with a semiconductor chip back electrode led out to the front side sequentially comprises a plastic packaging layer, a first dielectric layer, a second dielectric layer and a bonding pad from bottom to top; a chip and a conductive block are packaged in the plastic packaging layer, and a back electrode of the chip is bonded with the conductive block; the first medium layer is positioned on the plastic package layer on the front surface of the chip, wiring layers are formed in the first medium layer and the second medium layer, and the front surface electrode and the conductive block of the chip are bonded with the bonding pad through the wiring layers.
In one example, the conductive blocks are respectively arranged on two sides of the chip.
In one example, the conductive block is a metal block.
In one example, the distances from the conductive block and the front electrode of the chip to the surface of the plastic package layer are equal.
In one example, the back electrode of the chip is bonded to the conductive bumps via wires.
In one example, the front electrodes, the conductive blocks and the leads of the chip are all covered by the plastic package layer.
In one example, a plurality of through holes are formed in the first dielectric layer, and the through holes correspond to the positions of the conductive blocks and the front electrodes; the wiring layer is formed on the first dielectric layer and in the through hole, and the second dielectric layer wraps the wiring layer.
In one example, a lead layer is formed on the wiring layer, the second dielectric layer wraps the wiring layer and the lead layer, and the lead layer is bonded with the bonding pad.
In one example, the molding layer is made of epoxy resin.
In one example, the dielectric layer is Al 2 O 3 、SiO 2 Any one of SiNx, epoxy resin, PI and PBO.
It should be further noted that the technical features corresponding to the above examples can be combined with each other or replaced to form a new technical solution.
Compared with the prior art, the utility model discloses beneficial effect is:
(1) In one example, the DFN package is formed by leading out the back electrode to the front side through the conductive block and the wiring layer, and the whole structure does not need to adopt a high copper column, so that the process complexity is reduced, the package volume is reduced, the package area is small, and the manufacturing cost is low; meanwhile, the back electrode is bonded with the conductive block, so that parasitic resistance can be effectively reduced.
(2) In one example, the interconnection of the back electrode and the front electrode is realized by using a low-resistance metal block, so that the parasitic resistance of the packaging structure is further reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention.
Fig. 1 is a schematic view of a package structure prepared in step S1 according to a preferred embodiment of the present invention;
FIG. 2 is a schematic diagram of a package structure prepared in step S2 according to a preferred embodiment of the present invention;
FIG. 3 is a schematic diagram of a package structure prepared in step S3 according to a preferred embodiment of the present invention;
FIG. 4 is a schematic diagram of a package structure prepared in step S4 according to a preferred embodiment of the present invention;
FIG. 5 is a schematic diagram of a package structure prepared in step S5 according to a preferred embodiment of the present invention;
FIG. 6 is a schematic diagram of a package structure prepared in step S6 according to a preferred embodiment of the present invention;
fig. 7 is a schematic diagram of a package structure prepared in step S7 according to a preferred embodiment of the present invention.
In the figure: 1-plastic package layer, 2-chip, 3-metal block, 4-first preferred dielectric layer, 5-second dielectric layer, 6-wiring layer, 7-front electrode, 8-bonding pad, 9-lead, 10-pin layer and 11-carrier plate.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like are the directions or positional relationships indicated on the basis of the drawings, and are only for convenience of description and simplification of the description, but not for indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to the order, but rather are to be construed to indicate or imply relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly stated or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Furthermore, the technical features mentioned in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
In one example, the DFN packaging structure with the semiconductor chip back electrode led out to the front side sequentially comprises a plastic packaging layer, a first dielectric layer, a second dielectric layer and a bonding pad from bottom to top. The chip and the conductive blocks are arranged in the plastic packaging layer in a sealing mode, the back electrode of the chip is connected with the conductive blocks in an interconnecting mode, and the number of the conductive blocks is adjusted based on the number of the back electrodes; furthermore, the first dielectric layer is formed on the plastic package layer on the front side of the chip, wiring layers are formed in the first dielectric layer and the second dielectric layer, the wiring layers are wrapped by the first dielectric layer and the second dielectric layer, the front electrode and the conductive block of the chip are bonded with the bonding pad through the wiring layers, the back electrode, the conductive block, the wiring layers and the bonding pad of the chip are sequentially interconnected, and the front electrode, the wiring layers and the bonding pad of the chip are sequentially interconnected.
In the example, the back electrode is led out to the front side through the conductive block and the wiring layer to form the DFN package, and the whole structure does not need to adopt a high copper column, so that the process complexity is reduced, the package volume is reduced, the package area is small, and the manufacturing cost is low; meanwhile, the back electrode is bonded with the conductive block, so that parasitic resistance can be effectively reduced.
In one example, the conductive blocks are respectively arranged on two sides of the chip, so that the back electrodes on the two sides are respectively connected with the conductive blocks on the same side, and the wiring layout is simplified.
In one example, the conductive block is a metal block, preferably a low-resistance metal material, such as silver, copper, and the like, and the low-resistance metal block is used to interconnect the back electrode and the front electrode, so as to further reduce the parasitic resistance of the package structure.
In one example, distances from the front electrodes of the conductive block and the chip to the surface of the plastic package layer are equal, that is, the front surfaces of the conductive block and the front electrode are at the same horizontal height, which is convenient for plastic package on one hand and interconnection of the wiring layer with the conductive block and the front electrode on the other hand.
In one example, the back electrodes of the chips are bonded with the conductive bumps via leads, which enables reliable interconnection of the conductive bumps with the back electrodes. Furthermore, the front electrode, the conductive block and the lead of the chip are covered by a plastic package layer.
In one example, a plurality of through holes are formed in the first dielectric layer, and the through holes correspond to the conductive blocks and the front electrodes; the wiring layer is formed on the first dielectric layer and in the through hole, and the second dielectric layer wraps the wiring layer, so that the rewiring of the front side is realized, and the back electrode is led out to the front side.
In an example, a lead layer is formed on the wiring layer, the second dielectric layer wraps the wiring layer and the lead layer, the lead layer is bonded with the pad, that is, the back electrode, the conductive block, the wiring layer, the lead layer and the pad are sequentially interconnected, and the front electrode, the wiring layer, the lead layer and the pad of the chip are sequentially interconnected.
In one example, the plastic package layer is made of epoxy resin, has the characteristics of light weight, high strength, good corrosion resistance, excellent electrical property, shock absorption and the like, and can better meet the chip packaging requirements.
In one example, the dielectric layer is Al 2 O 3 、SiO 2 Any one of SiNx, epoxy resin, PI and PBO.
The above examples are combined to obtain a preferred example of the present invention, and as shown in fig. 7, the package structure includes a plastic package layer 1, a first dielectric layer 4, a second dielectric layer 5, and a bonding pad 8 from bottom to top. The chip 2 and the metal block 3 are packaged in the plastic packaging layer 1, the metal block 3 is respectively arranged on two sides of the chip 2, and the front surface of the metal block 3 and the front surface of the front electrode 7 are at the same horizontal height; the back electrode of the chip 2 is interconnected with the metal block 3 via a lead 9. The first medium layer 4 is formed on the plastic package layer 1 on the front side of the chip 2, the wiring layer 6 is formed in the first medium layer 4 and the second medium layer 5, the lead layer 10 is formed on the wiring layer 6, the lead layer 10 is located in the second medium layer 5, and the front electrode 7 and the metal block 3 of the chip 2 are sequentially bonded with the bonding pad 8 through the wiring layer 6 and the lead layer 10.
To illustrate the technical concept of the present invention, a method for fabricating a DFN encapsulation structure in a preferred example will now be described, the method comprising the steps of:
s1: as shown in fig. 1, a chip 2 is mounted on a carrier 11, the chip 2 faces downward, and metal blocks 3 are attached to the carrier 11 on both sides of the chip 2; the front surface of the chip 2 is adhered to the surface of the carrier 11 by temporary bonding glue, and the carrier 11 includes but is not limited to a steel plate, a glass plate, and the like.
S2: as shown in fig. 2, the back electrodes of the chip 2 are respectively bonded to the metal blocks 3 at the left and right ends through leads 9;
s3: as shown in fig. 3, plastic-packaging the current structure to form a plastic-packaged layer 1, and removing the carrier plate 11; wherein the carrier plate 11 is removed by removing the temporary bonding glue.
S4: as shown in fig. 4, a first dielectric layer 4 is formed on the front side plastic package layer 1 of the chip 2, and a through hole is formed, and the position of the through hole corresponds to the front electrode 7 and the metal block 3;
s5: as shown in fig. 5, a wiring layer 6 (RDL) is prepared at the via hole position;
s6: as shown in fig. 6, a second dielectric layer 5 is formed on the wiring layer 6, and an opening is formed, wherein the position of the opening corresponds to the position of the wiring layer 6;
s7: as shown in fig. 7, the lead layer 10 and the pad 8 were formed at the opening position, and the DFN package structure of the present invention was obtained.
The above detailed description is the detailed description of the present invention, and it can not be considered that the detailed description of the present invention is limited to these descriptions, and to the ordinary skilled person in the art to which the present invention belongs, without departing from the concept of the present invention, a plurality of simple deductions and replacements can be made, which should be regarded as belonging to the protection scope of the present invention.
Claims (10)
1. A DFN packaging structure for leading back electrodes of a semiconductor chip out to the front is characterized in that: the plastic packaging structure sequentially comprises a plastic packaging layer, a first dielectric layer, a second dielectric layer and a bonding pad from bottom to top;
a chip and a conductive block are packaged in the plastic packaging layer, and a back electrode of the chip is bonded with the conductive block;
the first medium layer is positioned on the plastic package layer on the front surface of the chip, wiring layers are formed in the first medium layer and the second medium layer, and the front surface electrode and the conductive block of the chip are bonded with the bonding pad through the wiring layers.
2. The DFN package structure of claim 1, wherein the semiconductor chip comprises a back electrode leading out to the front side, and wherein: the conductive blocks are respectively arranged on two sides of the chip.
3. The DFN package structure of claim 1, wherein the DFN package structure further comprises: the conductive block is a metal block.
4. The DFN package structure of claim 1, wherein the semiconductor chip comprises a back electrode leading out to the front side, and wherein: the distances from the conductive block and the front electrode of the chip to the surface of the plastic package layer are equal.
5. The DFN package structure of claim 1, wherein the semiconductor chip comprises a back electrode leading out to the front side, and wherein: and the back electrode of the chip is bonded with the conductive block through a lead.
6. The DFN package structure of claim 5 wherein the back electrode of the semiconductor die is leaded out to the front side, further comprising: the front electrode, the conductive block and the lead of the chip are covered by the plastic package layer.
7. The DFN package structure of claim 1, wherein the DFN package structure further comprises: a plurality of through holes are formed in the first dielectric layer, and correspond to the conductive block and the front electrode; the wiring layer is formed on the first dielectric layer and in the through hole, and the second dielectric layer wraps the wiring layer.
8. The DFN package structure of claim 1, wherein the DFN package structure further comprises: and a lead layer is formed on the wiring layer, the second dielectric layer wraps the wiring layer and the lead layer, and the lead layer is bonded with the bonding pad.
9. The DFN package structure of claim 1, wherein the semiconductor chip comprises a back electrode leading out to the front side, and wherein: the plastic packaging layer is made of epoxy resin.
10. The DFN package structure of claim 1, wherein the semiconductor chip comprises a back electrode leading out to the front side, and wherein: the dielectric layer is Al 2 O 3 、SiO 2 Any one of SiNx, epoxy resin, PI and PBO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222872945.5U CN218274567U (en) | 2022-10-28 | 2022-10-28 | DFN packaging structure for leading back electrode of semiconductor chip to front side |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222872945.5U CN218274567U (en) | 2022-10-28 | 2022-10-28 | DFN packaging structure for leading back electrode of semiconductor chip to front side |
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| Publication Number | Publication Date |
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| CN218274567U true CN218274567U (en) | 2023-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222872945.5U Active CN218274567U (en) | 2022-10-28 | 2022-10-28 | DFN packaging structure for leading back electrode of semiconductor chip to front side |
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| CN (1) | CN218274567U (en) |
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- 2022-10-28 CN CN202222872945.5U patent/CN218274567U/en active Active
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