CN218215276U - Semiconductor structure - Google Patents

Abstract

The embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a device structure disposed on the middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position thereof in a cross-section perpendicular to the substrate being greater than or equal to a cross-sectional width at a top surface of the grooves; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region.

Description

Semiconductor structure

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure.

Background

The manufacturing process of semiconductor devices involves a large number of film structures, wherein one portion of the film structure needs to be removed and another portion of the film structure needs to be permanently retained in the semiconductor device for protection or shielding. For film layer structures to be retained in a semiconductor device, adhesion between the film layer structures is critical. If the adhesiveness between the film layer structures is poor or the subsequent process has destructiveness on the adhesiveness between the film layer structures, the film layer structures are easy to fall off and cannot exert due protective effect.

SUMMERY OF THE UTILITY MODEL

Accordingly, the embodiments of the present disclosure provide a semiconductor structure to solve at least one technical problem in the prior art.

In order to achieve the purpose, the technical scheme of the disclosure is realized as follows:

in a first aspect, embodiments of the present disclosure provide a semiconductor structure, which includes:

a substrate;

a device structure disposed on the middle region of the substrate;

a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position thereof in a cross-section perpendicular to the substrate being greater than or equal to a cross-sectional width at a top surface of the grooves; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region.

In some embodiments, the semiconductor structure further comprises a second sealing layer; wherein, the first and the second end of the pipe are connected with each other,

the second sealing layer is arranged on one side of the device structure far away from the substrate, the second sealing layer covers the substrate, and a first cavity is formed between the second sealing layer and the middle area of the substrate; the device structure is located within the first cavity.

In some embodiments, the sidewalls of the grooves are uneven surfaces; and/or the bottom surface of the groove is an uneven surface.

In some embodiments, a ratio between a cross-sectional width at a bottom surface of the groove and a depth of the groove is greater than or equal to 10 in a cross-section perpendicular to the substrate.

In some embodiments, the depth of the groove in a direction perpendicular to the substrate is greater than 500nm;

a cross-sectional width at a bottom surface of the groove is greater than 5 μm in a cross-section perpendicular to the substrate.

In some embodiments, in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer with a second cavity therebetween, in a direction pointing away from the substrate in proximity to the substrate.

In some embodiments, the device structure further includes an etch hole through at least the piezoelectric layer.

In some embodiments, the distribution density of the grooves on the transition layer close to the etching holes is greater than that of the grooves far away from the etching holes;

the depth of the groove on the transition layer close to the etching hole is larger than that of the groove far away from the etching hole along the direction vertical to the substrate.

In some embodiments, in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator includes a lower electrode layer, a piezoelectric layer, an upper electrode layer, and a regulation layer, in a direction pointing away from the substrate in proximity to the substrate, with a second cavity between the lower electrode layer and the substrate.

In a second aspect, embodiments of the present disclosure provide a semiconductor structure, including:

a wafer; the wafer comprises a plurality of chip areas;

a device structure disposed on the intermediate region of each of the chip regions;

the transition layer and the first sealing layer are arranged on the edge area of each chip area, a plurality of grooves are arranged on the transition layer, and the section width of at least one depth position of each groove on the section perpendicular to the wafer is larger than or equal to the section width of the groove on the top surface of the groove; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region.

In some embodiments, a distribution density of the grooves on the transition layer is greater in an edge area close to the wafer and/or the chip area than in an edge area far from the wafer and/or the chip area;

in a direction perpendicular to the wafer, a depth of the groove on the transition layer near an edge region of the wafer and/or the chip region is greater than a depth of the groove far from the edge region of the wafer and/or the chip region.

In some embodiments, the semiconductor structure further comprises a second sealing layer; wherein, the first and the second end of the pipe are connected with each other,

the second sealing layer is arranged on one side of the device structure far away from the wafer, the second sealing layer covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity.

In some embodiments, in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, and an upper electrode layer, in a direction towards the wafer and away from the wafer;

the semiconductor structure further comprises a welding pad, and the upper electrode layer and the lower electrode layer of the film bulk acoustic resonator in each chip area are electrically connected with the welding pad through electrode leads; wherein, the first and the second end of the pipe are connected with each other,

the distribution density of the grooves close to the welding pads on the transition layer is greater than that of the grooves far away from the welding pads;

along the direction perpendicular to the wafer, the depth of the groove close to the welding pad on the transition layer is larger than the depth of the groove far away from the welding pad.

The embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a device structure disposed on the middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position thereof in a cross-section perpendicular to the substrate being greater than or equal to a cross-sectional width at a top surface of the grooves; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region. In the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with a plurality of grooves, and the cross-sectional width of at least one depth position of each groove is greater than or equal to the cross-sectional width of the top surface of each groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded to form a similar buckle structure, so as to improve the adhesion between the transition layer and the first sealing layer, and further improve the adhesion between the substrate and the first sealing layer.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure;

fig. 2 is a schematic flow chart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 3A is a first cross-sectional view of a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 3B is a cross-sectional view of a second process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

FIG. 3C is a cross-sectional view III of a process for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 3D is a cross-sectional view of a fourth process for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

fig. 4A is a schematic cross-sectional structure diagram of a groove according to an embodiment of the present disclosure;

fig. 4B is a schematic cross-sectional structure diagram of a groove provided in the present disclosure;

fig. 4C is a schematic cross-sectional structure diagram of a groove provided in the embodiment of the present disclosure;

fig. 4D is a schematic cross-sectional structure diagram of a groove provided in the embodiment of the present disclosure;

fig. 4E is a schematic cross-sectional structure diagram of a groove provided in the embodiment of the present disclosure;

fig. 4F is a schematic cross-sectional structure diagram six of a groove provided in the present disclosure;

fig. 5 is a schematic cross-sectional view of another semiconductor structure according to an embodiment of the present disclosure;

fig. 6A is a schematic cross-sectional structure diagram of a thin film bulk acoustic resonator according to an embodiment of the present disclosure;

fig. 6B is a schematic cross-sectional structure diagram of a thin film bulk acoustic resonator according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure diagram of another film bulk acoustic resonator according to an embodiment of the disclosure;

fig. 8 is a top-down perspective view of a semiconductor structure provided by an embodiment of the present disclosure;

the drawing comprises the following steps: 101. 201, 301, a substrate; 101a, 201a, 301a, a middle region of the substrate; 101b, 201b, 301b, edge regions of the substrate; 102. a device structure; 103. 203, 306, a transition layer; 104. 104a, 104b, 104c, 104d, 104e, 104f, 204, 307, grooves; 105. 209, 309, a first sealing layer; 106. 210, 310, bumps; 107. a patterned photoresist layer; 108. 211, 311, a second sealing layer; 202. 302, a lower electrode layer; 205. 303, a piezoelectric layer; 206. 304, 404, etching holes; 207. 305, 403, an upper electrode layer; 208. 308, a regulating layer; 401. a wafer; 402. a chip region; 405. an electrode lead; 406. and (6) a bonding pad.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the embodiments of the present disclosure and the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without inventive step, are within the scope of the present disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" \8230; \8230 ";," - \8230;, "\8230"; "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to, or coupled to the other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," 8230; \8230 ";," "directly adjacent," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is necessarily present in the disclosure.

Spatial relational terms such as "in 8230," "below," "in 8230," "below," "8230," "above," "above," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230; \8230; below" and "at 8230; \8230; below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be set forth in the following description in order to explain the technical aspects of the present disclosure. The following detailed description of the preferred embodiments of the present disclosure, however, the present disclosure may have other embodiments in addition to these detailed descriptions.

During the fabrication of a semiconductor device (e.g., a semiconductor device including a cavity), a cavity may be formed in the semiconductor device using a sacrificial layer Release (Release) process. Specifically, a suitable etchant may be selected by a dry etching method and/or a wet etching method, and the etchant is injected into the etching holes exposing the sacrificial layer, so that the etchant contacts the exposed sacrificial layer and a chemical reaction occurs, so as to remove the sacrificial layer and form a cavity.

The manufacturing process of semiconductor devices involves a large number of film structures, wherein one portion of the film structure needs to be removed and another portion of the film structure needs to be permanently retained in the semiconductor device for protection or shielding. For film layer structures to be retained in a semiconductor device, adhesion between the film layer structures is critical. If the adhesion between the film structures themselves is not good, or if the adhesion between the film structures is damaged by a subsequent process (for example, a sacrificial layer release process), the film structures are easily peeled off and cannot exert the required protection effect. As a preferred material, polyimide (PI) has good heat resistance, good insulation, resistance to moist heat, resistance to high temperature radiation, and the like, and has good adhesion to a substrate (e.g., a silicon wafer) itself, but adhesion between the Polyimide and the substrate becomes poor after a sacrificial layer release process. This is because the longer Hydrogen Fluoride (HF) ambient in the sacrificial layer release process destroys the adhesion between the polyimide and the silicon wafer.

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same.

Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 1, the semiconductor structure provided by the embodiment of the present disclosure includes: a substrate 101; a device structure 102 disposed on the intermediate region 101a of the substrate; a transition layer 103 and a first sealing layer 105 provided on the edge region 101b of the substrate, the transition layer 103 being provided with a plurality of grooves 104, a cross-sectional width of the grooves 104 at least one depth position in a cross-section perpendicular to the substrate 101 being greater than or equal to a cross-sectional width at a top surface of the grooves 104; a plurality of bulges 106 are arranged at the positions of the first sealing layer 105 opposite to the grooves 104, and the grooves 104 of the transition layer 103 and the bulges 106 of the first sealing layer 105 are mutually embedded; wherein the edge region 101b of the substrate surrounds the middle region 101a of the substrate.

It is to be noted that the cross-sectional shape of the groove shown in fig. 1 in the cross-section perpendicular to the substrate appears rectangular, that is, the cross-sectional width is the same at each depth position of the groove. For example, the cross-sectional width at the bottom surface of the groove is the same as the cross-sectional width at the top surface of the groove.

In the embodiment of the disclosure, by arranging the transition layer between the substrate and the first sealing layer, the transition layer is provided with a plurality of grooves, and the cross-sectional width of at least one depth position of each groove is greater than or equal to the cross-sectional width of the top surface of the groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded, the adhesion between the transition layer and the first sealing layer is improved, and the adhesion between the substrate and the first sealing layer is improved. It should be noted that the adhesion between the substrate and the transition layer itself is good.

Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 2, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes:

step S201: providing a substrate;

step S202: forming a transition layer on the edge area of the substrate while forming a device structure in the middle area of the substrate;

step S203: forming a plurality of grooves on the transition layer; on a cross section perpendicular to the substrate, a cross-sectional width at least one depth position of the groove is greater than or equal to a cross-sectional width at a top surface of the groove;

step S204: coating a first sealing material on the transition layer to form a first sealing layer having a plurality of protrusions opposite the grooves; the groove of the transition layer and the protrusion of the first sealing layer are mutually embedded; the edge region surrounds the middle region.

The method for manufacturing the semiconductor structure provided by the embodiment of the disclosure will be described in detail below with reference to fig. 3A to 3D.

Referring to fig. 3A, a transition layer 103 is formed on an edge region 101b of the substrate while a device structure 102 is formed on a middle region 101a of the substrate. Wherein the edge region 101b of the substrate surrounds the middle region 101a of the substrate.

Referring to fig. 3B, a patterned photoresist layer 107 is formed on the transition layer 103. The pattern of the photoresist layer is used for defining the shape of a groove formed on the transition layer in the subsequent process.

Referring to fig. 3C, the transition layer 103 is etched through the patterned photoresist layer 107 to form the recess 104.

In the embodiments of the present disclosure, the transition layer may be etched using dry etching, wet etching, or a combination thereof to form the groove. Here, the number and distribution density of the grooves may be set according to the needs of those skilled in the art. Note that wet etching is performed with an etchant, for example, an acid-base solution; the dry etching includes physical etching, chemical etching, and physical chemical etching. The physical etching is to ionize gas into positively charged ions by glow discharge, accelerate the ions by bias voltage, and sputter the ions on the surface of an etched object to knock out atoms of the etched object; the chemical etching utilizes plasma to ionize etching gas and form charged ions, molecules and atomic groups with strong reactivity, the charged ions, the molecules and the atomic groups are diffused to the surface of an etched object and then react with atoms on the surface of the etched object to generate a reaction product with volatility, and the reaction product is pumped out of a reaction cavity by vacuum equipment.

Still referring to figure 3C of the drawings,the cross-sectional shape of the groove 104 appears rectangular in a cross section perpendicular to the substrate. Wherein, along the direction vertical to the substrate, the depth of the groove 104 is H ₁ (ii) a The width of the cross section at the top surface of the groove 104 in a cross section perpendicular to the substrate is W ₁ The width of the cross section at the bottom surface of the groove 104 is W ₂ 。

In the embodiment of the disclosure, the depth of the groove is smaller than the thickness of the transition layer along the direction perpendicular to the substrate. In other words, the transition layer is etched to form a groove, and the bottom of the groove does not expose the surface of the substrate.

It is noted that fig. 3C illustrates that the sectional shape of the groove appears rectangular, and therefore, the sectional width W at the top surface of the groove ₁ And a cross-sectional width W at the bottom surface of the groove ₂ The same is true.

In the embodiment of the present disclosure, in a cross section perpendicular to the substrate, a ratio between a cross-sectional width at a bottom surface of the groove and a depth of the groove is greater than or equal to 10.

In the disclosed embodiment, the depth H of the groove is along the direction vertical to the substrate ₁ Greater than 500nm; a cross-sectional width W at the bottom surface of the groove in a cross-section perpendicular to the substrate ₂ Greater than 5 μm.

Referring to fig. 3D, the patterned photoresist layer is removed, and a first sealing material is coated on the transition layer 103 to form a first sealing layer 105 having a plurality of protrusions 106 opposite to the grooves 104; wherein, the groove 104 of the transition layer 103 and the bulge 106 of the first sealing layer 105 are mutually embedded.

In the embodiments of the present disclosure, the first sealing layer may be formed by a spin coating process. The first sealing material is coated on the transition layer, enters the groove of the transition layer in the coating process, and is cured in a post-baking mode and the like, so that the first sealing layer can be embedded into the groove of the transition layer, the contact area between the transition layer and the first sealing layer is increased, the adhesion between the transition layer and the first sealing layer is improved, and the adhesion between the substrate and the first sealing layer is further improved.

Here, the process of forming the first sealing layer using the spin coating process is as follows: and coating the first sealing material on the transition layer, rotating at a certain speed, wherein in the rotating process, the first sealing material enters the groove of the transition layer, and the first sealing material entering the groove of the transition layer is solidified to form a bulge of the first sealing layer, so that the first sealing layer with a certain thickness is formed finally.

It should be noted that, in the process of forming the device structure on the middle region of the substrate, a sacrificial layer release process may be used to form the cavity. According to the semiconductor structure provided by the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, and the groove on the transition layer and the protrusion on the first sealing layer are mutually embedded, so that even if a hydrogen fluoride environment exists for a long time in a sacrificial layer release process, the adhesiveness between the substrate and the first sealing layer is difficult to damage, and therefore, the adhesiveness between the substrate and the first sealing layer can be improved, the performance of the device structure is improved, and the service life of the device structure is prolonged. It should be noted that the substrate and the transition layer have good adhesion even in a hydrogen fluoride atmosphere.

Different cross-sectional shapes of the grooves provided by the embodiments of the present disclosure will be described in detail below with reference to fig. 4A to 4E.

Referring to fig. 4A, the transition layer 103 is etched to form a plurality of grooves 104A; the depth of the groove 104a in the direction perpendicular to the substrate is H ₂ (ii) a The width of the cross section at the top surface of the groove 104a on the cross section perpendicular to the substrate is W ₃ The width of the cross section at the bottom surface of the groove 104a is W ₄ . The cross-sectional shape of the groove 104A illustrated in fig. 4A still appears rectangular, the cross-sectional width W at the top surface of the groove 104A ₃ And a sectional width W at the bottom surface of the groove 104a ₄ The same; and a plurality of tooth-like projections are formed on the side walls and the bottom of the recess 104 a.

In the embodiment of the disclosure, the side wall of the groove is an uneven surface; and/or the bottom surface of the groove is an uneven surface. Here, increasing the roughness of the side walls of the groove and/or the bottom surface of the groove may increase the interaction force between the groove and the protrusions of the first sealing layer, which may be beneficial to improve the engagement effect between the transition layer and the first sealing layer, and thus improve the adhesion between the transition layer and the first sealing layer.

In the embodiment of the disclosure, the tooth-shaped protrusions are formed on the side walls and the bottom of the groove, so that the roughness of the side walls and the bottom of the groove is increased, and the adhesion between the groove and the first sealing layer is further increased.

Referring to fig. 4B, the transition layer 103 is etched to form a plurality of grooves 104B; the depth of the groove 104b in the direction perpendicular to the substrate is H ₃ (ii) a The cross-sectional width at the top surface of the groove 104b on a cross-section perpendicular to the substrate is W ₅ The width of the cross section at the bottom surface of the groove 104b is W ₆ Wherein the cross-sectional width W at the top surface of the groove 104b ₅ Is smaller than the sectional width W at the bottom surface of the groove 104b ₆ . The cross-sectional shape of the groove 104B illustrated in FIG. 4B includes two rectangles, the first rectangle having a cross-sectional width W ₅ The second rectangle has a cross-sectional width W ₆ The sum of the depths of the two rectangles in the direction perpendicular to the substrate is H ₃ 。

Here, the etching may be performed stepwise, with the etching being performed longitudinally to a depth H in a direction perpendicular to the substrate ₃ Cross-sectional width of W ₅ Pre-grooving; then, the cross section width of the bottom of the pre-groove is increased to W by horizontal etching ₆ To form the recess 104b. Generally, a dry etching process is used for the longitudinal etching, and a wet etching process is used for the lateral etching.

Referring to fig. 4C, the transition layer 103 is etched to form a plurality of recesses 104C; the depth of the recess 104c in the direction perpendicular to the substrate is H ₄ (ii) a The cross-sectional width at the top surface of the groove 104c on a cross-section perpendicular to the substrate is W ₇ The cross-sectional width at the bottom surface of the groove 104c is W ₈ Wherein the cross-sectional width W at the top surface of the groove 104c ₇ Is smaller than the cross-sectional width W at the bottom surface of the groove 104c ₈ . The cross-sectional shape of the groove 104C illustrated in fig. 4C is a trapezoid with a narrow top and a wide bottom, starting from the top surface of the groove 104C and increasing with the depth of the groove 104CAdditionally, the cross-sectional width of the groove 104c increases.

Referring to fig. 4D, the transition layer 103 is etched to form a plurality of grooves 104D; the depth of the groove 104d in the direction perpendicular to the substrate is H ₅ (ii) a The width of the cross section at the top surface of the groove 104d is W in the cross section perpendicular to the substrate ₉ The groove 104d has a cross-sectional width W at a certain depth position ₁₀ Wherein, W ₁₀ The maximum cross-sectional width of the groove 104d, the cross-sectional width W at the top surface of the groove 104d ₉ Is smaller than the cross-sectional width W of the groove 104d at a certain depth position ₁₀ . The sectional shape of the groove 104D illustrated in fig. 4D is polygonal, and the sectional width of the groove 104D increases first and then decreases as the depth of the groove 104D increases, starting from the top surface of the groove 104D.

Referring to fig. 4E, the transition layer 103 is etched to form a plurality of grooves 104E; the depth of the groove 104e in the direction perpendicular to the substrate is H ₆ (ii) a The width of the cross section at the top surface of the groove 104e is W in the cross section perpendicular to the substrate ₁₁ The groove 104e has a cross-sectional width W at a depth position ₁₂ Wherein, W ₁₂ The maximum cross-sectional width of the groove 104e, the cross-sectional width W at the top surface of the groove 104e ₁₁ Is smaller than the cross-sectional width W of the groove 104e at a depth position ₁₂ . Fig. 4E schematically shows that the cross-sectional shape of the groove 104E is irregular, the side wall of the groove 104E is formed by connecting a plurality of arcs, and the cross-sectional width of the groove 104E increases and then decreases as the depth of the groove 104E increases from the top surface of the groove 104E.

Referring to fig. 4F, the transition layer 103 is etched to form a plurality of recesses 104F; the depth of the recess 104f in the direction perpendicular to the substrate is H ₇ (ii) a The width of the cross section at the top surface of the groove 104f is W on the cross section perpendicular to the substrate ₁₃ The width of the cross section at the bottom surface of the groove 104f is W ₁₄ Wherein, W ₁₄ The maximum cross-sectional width of the groove 104e, the cross-sectional width W at the top surface of the groove 104f ₁₃ Is smaller than the cross-sectional width W of the groove 104f at a depth position ₁₄ . The cross-sectional shape of the groove 104F illustrated in FIG. 4F includes a momentA trapezoid with a narrow top and a wide bottom, the rectangle has a cross-sectional width W ₁₃ The width of the top edge of the trapezoid is W ₁₃ The width of the bottom side of the trapezoid is W ₁₄ The sum of the depths of the rectangle and the trapezoid in the direction perpendicular to the substrate is H ₇ . In other words, starting from the top surface of the groove 104f, the sectional width of the groove 104f is constant first and then increases as the depth of the groove 104f increases. Here, a snap effect is formed between the portion of the groove of the transition layer with the increased cross-sectional width (i.e., the portion with the trapezoidal cross-sectional shape) and the protrusion of the first sealing layer, increasing the interaction force between the transition layer and the first sealing layer.

In an embodiment of the present disclosure, a cross-sectional width at least one depth position of the groove is greater than or equal to a cross-sectional width at a top surface of the groove on a cross-section perpendicular to the substrate. In other words, when the first sealing material is coated on the transition layer, the first sealing material enters the groove of the transition layer in the coating process, and then the first sealing material is cured in a post-baking mode and the like, so that the first sealing layer can be embedded into the groove of the transition layer, and due to the fact that the groove in the special shape is formed in the transition layer, the effect similar to buckling is formed between the groove of the transition layer and the protrusion of the first sealing layer, the interaction force between the transition layer and the first sealing layer is increased, the adhesion between the transition layer and the first sealing layer is improved, and the adhesion between the substrate and the first sealing layer is further improved.

Referring to fig. 5, fig. 5 is a schematic cross-sectional structure diagram of another semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 5, the semiconductor structure further includes a second encapsulation layer 108; wherein the second sealing layer 108 is disposed on a side of the device structure 102 away from the substrate 101, and the second sealing layer 108 covers the substrate 101, and a first cavity is formed between the second sealing layer 108 and the middle region 101a of the substrate; the device structure 102 is located within the first cavity.

In the embodiment of the present disclosure, a sacrificial layer covering the device structure may be formed on the middle region of the substrate, the sacrificial layer is removed through a sacrificial layer release process, a first cavity is formed between the second sealing layer and the middle region of the substrate, and the device structure is located in the first cavity. In embodiments of the present disclosure, a device structure having a cavity may also be formed on the middle region of the substrate, wherein the cavity within the device structure is formed by a sacrificial layer release process.

In embodiments of the present disclosure, the material of the transition layer includes a material that is resistant to an etchant. Here, during the formation of the first cavity by the sacrificial layer release process, and during the formation of the device structure having the cavity by the sacrificial layer release process, the etchant inevitably contacts the transition layer. The transition layer is formed by selecting a material resistant to an etchant, and the etching rate of the etchant to the transition layer is obviously lower than that of the etchant to the sacrificial layer, so that the transition layer is not obviously etched and damaged by the etchant in the process of removing the sacrificial layer by using the etchant. Even the transition layer can be formed by selecting proper etchant-resistant materials, and the transition layer is not etched while the sacrificial layer is etched and removed.

In embodiments of the present disclosure, a sacrificial layer release process is used to form a first cavity between the middle region of the substrate and the second sealing layer and to form a device structure having a cavity. According to the semiconductor structure provided by the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with the plurality of grooves, and the section width of at least one depth position of each groove is larger than or equal to the section width of the top surface of each groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded, and thus, even if a hydrogen fluoride environment exists for a long time in a sacrificial layer release process, the adhesion between the substrate and the first sealing layer is difficult to damage, the adhesion between the substrate and the first sealing layer can be improved, the performance of the device structure is improved, and the service life of the device structure is prolonged.

In one particular example, the device structure may include a Thin Film Bulk Acoustic Wave Resonator (FBAR).

The semiconductor structure and the method for manufacturing the same according to the embodiments of the present disclosure will be described in detail with reference to fig. 6A, 6B and 7.

Fig. 6A and 6B illustrate schematic cross-sectional structures in a case where the device structure is a thin film bulk acoustic resonator in a specific example.

Referring to fig. 6A, a semiconductor structure provided by an embodiment of the present disclosure includes: a substrate 201; forming a film bulk acoustic resonator on the middle area 201a of the substrate, wherein the film bulk acoustic resonator comprises a lower electrode layer 202, a piezoelectric layer 205 and an upper electrode layer 207 along a direction pointing away from the substrate 201 close to the substrate 201, and a second cavity is formed between the lower electrode layer 202 and the substrate 201; the material of the transition layer 203 and the piezoelectric layer 205 are the same, and the transition layer 203 and the piezoelectric layer 205 are formed in the same process step. The film bulk acoustic resonator further comprises an etch hole 206 through the piezoelectric layer 205.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a first sealing layer 209 disposed on the transition layer 203 on the edge region 201b of the substrate; the transition layer 203 is provided with a plurality of grooves 204, the cross section width of at least one depth position of the grooves 204 is larger than or equal to the cross section width of the top surface of the grooves 204, a plurality of bulges 210 are arranged at the position of the first sealing layer 209 opposite to the grooves 204, and the grooves 204 of the transition layer 203 and the bulges 210 of the first sealing layer 209 are mutually embedded; wherein the edge region 201b of the substrate surrounds the middle region 201a of the substrate.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a second sealant 211; the second sealing layer 211 is arranged on the side, far away from the substrate 201, of the film bulk acoustic resonator, the second sealing layer 211 covers the substrate 201, and a first cavity is formed between the second sealing layer 211 and the middle area 201a of the substrate; the film bulk acoustic resonator is located in the first cavity.

The specific process for forming the film bulk acoustic resonator in the semiconductor structure provided by the disclosed embodiment is as follows: forming a sacrificial layer (not illustrated in fig. 6A) and a lower electrode layer 202 covering the sacrificial layer on the middle region 201a of the substrate; forming a transition layer 203 on an edge area 201b of the substrate while forming a piezoelectric layer 205 covering the lower electrode layer 202 on a middle area 201a of the substrate; forming an upper electrode layer 207 covering the piezoelectric layer 205 on the middle area 201a of the substrate; forming etching holes 206 penetrating at least the piezoelectric layer 205; the transition layer 203 is etched to form a plurality of recesses 204 and a first sealing material is applied over the transition layer 203 to form a first sealing layer 209 having a plurality of protrusions 210 opposite the recesses 204.

In an embodiment of the disclosure, the material of the transition layer and the material of the piezoelectric layer may be the same, and the material of the transition layer includes at least one of: aluminum nitride AlN, aluminum nitride scandium AlScN, zinc oxide ZnO and lead zirconate titanate PZT.

In the embodiment of the present disclosure, the piezoelectric layer on the middle region of the substrate and the transition layer on the edge region of the substrate may be simultaneously formed through a plating process.

In the embodiment of the present disclosure, the material of the sacrificial layer may be silicon dioxide.

Forming the thin film bulk acoustic resonator in a semiconductor structure provided by the disclosed embodiments further comprises: and selecting a proper etchant by a wet etching method, and injecting the etchant into the etching hole exposed out of the sacrificial layer to enable the etchant to contact with the sacrificial layer and perform a chemical reaction to generate a liquid product or a gaseous product so as to remove the sacrificial layer and form a second cavity between the lower electrode layer and the substrate.

In one specific example, when the material of the sacrificial layer is silicon dioxide, hydrogen fluoride may be selected as an etchant to remove the sacrificial layer. After the hydrogen fluoride reacts with the sacrificial layer through the etching holes, gaseous silicon fluoride and liquid water are generated.

In some embodiments, etch holes may be formed through the upper electrode layer, the piezoelectric layer, and the lower electrode layer. In other embodiments, the position of the piezoelectric layer corresponding to the etching hole can be exposed when the lower electrode layer and the upper electrode layer are formed, so that the sacrificial layer can be exposed only by penetrating the piezoelectric layer through the etching hole.

In the embodiment of the present disclosure, as shown in fig. 6A, the resonance region of the thin film bulk acoustic resonator includes the lower electrode layer 202, the piezoelectric layer 205, and the upper electrode layer 207 on the second cavity.

Forming the semiconductor structure provided by the disclosed embodiments further includes the steps of: a second sealing layer 211 is formed on the first sealing layer 209 covering the substrate 201.

In the embodiment of the disclosure, the second sealing layer is used for shielding and protecting the film bulk acoustic resonator. Here, a gap exists between the second sealing layer and the resonance region of the thin film bulk acoustic resonator, and the gap can be used for reflecting the acoustic wave.

In the embodiment of the present disclosure, the composition material of the second sealing layer may include a layer structure, such as a dry film, which can be used for encapsulation.

In the embodiment of the disclosure, in the same process step, the transition layer and the piezoelectric layer are formed at the same time, the materials of the transition layer and the piezoelectric layer are the same, the adhesion between the substrate and the first sealing layer is improved through the transition layer, the process step of forming the transition layer is not required to be additionally added, and the manufacturing time and the manufacturing cost are saved. It should be noted that the adhesion between the transition layer made of the same material as the piezoelectric layer and the substrate itself is good, and the adhesion between the transition layer and the substrate is good even in a hydrogen fluoride atmosphere.

Referring to fig. 6B, a semiconductor structure provided by an embodiment of the present disclosure includes: a substrate 201; forming a film bulk acoustic resonator on the middle area 201a of the substrate, wherein the film bulk acoustic resonator comprises a lower electrode layer 202, a piezoelectric layer 205, an upper electrode layer 207 and a regulating layer 208 along a direction pointing away from the substrate 201 close to the substrate 201, and a second cavity is formed between the lower electrode layer 202 and the substrate 201; wherein the material of the transition layer 203 and the piezoelectric layer 205 are the same, and the transition layer 203 and the piezoelectric layer 205 are formed in the same process step. The film bulk acoustic resonator further comprises an etch hole 206 through the piezoelectric layer 205.

It should be noted that the process of trimming (trimming) the adjustment layer is a frequency modulation process for the device structure. Specifically, the frequency modulation of the device structure can be realized by thinning the adjusting layer.

In the embodiment of the present disclosure, as shown in fig. 6B, the resonance region of the thin film bulk acoustic resonator includes the lower electrode layer 202, the piezoelectric layer 205, the upper electrode layer 207, and the adjustment layer 208 on the second cavity.

In the embodiment of the disclosure, the distribution density of the grooves close to the etching holes on the transition layer is greater than that of the grooves far away from the etching holes; the depth of the groove close to the etching hole on the transition layer is larger than that of the groove far away from the etching hole along the direction vertical to the substrate.

It should be noted that, the larger the distribution density of the grooves on the transition layer is, the stronger the adhesion between the transition layer and the first sealing layer is; the greater the depth of the recess in the transition layer, the greater the adhesion between the transition layer and the first sealing layer. However, the greater the distribution density of the grooves on the transition layer and the greater the depth of the grooves on the transition layer, the weaker the strength of the transition layer, and the excessive grooves cause the transition layer to be easily broken. Therefore, it is necessary to adjust the distribution density and depth of the grooves on the transition layer by considering both the adhesion between the transition layer and the first sealing layer and the strength of the transition layer. The arrangement of the distribution density and the depth of the grooves on the transition layer needs to be compatible with the strength of the transition layer and the adhesiveness between the transition layer and the first sealing layer.

In the embodiment of the disclosure, the distribution density of the grooves close to the etching holes on the transition layer is set to be greater than that of the grooves far away from the etching holes; and the depth of the groove close to the etching hole on the transition layer is larger than that of the groove far away from the etching hole, so that a closed cavity is formed, the sealing property of the cavity is improved, the problem that external micromolecules enter the closed cavity and are attached to the film bulk acoustic resonator is avoided, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

Fig. 7 illustrates a schematic cross-sectional structure in a case where the device structure is a thin film bulk acoustic resonator in a specific example. As shown in fig. 7, the semiconductor structure provided by the embodiment of the present disclosure includes: a substrate 301; forming a thin film bulk acoustic resonator on the middle area 301a of the substrate, wherein the thin film bulk acoustic resonator comprises a lower electrode layer 302, a piezoelectric layer 303, an upper electrode layer 305 and a regulating layer 308 along a direction pointing away from the substrate 301 and close to the substrate 301, and a second cavity is formed between the lower electrode layer 302 and the substrate 301; wherein the transition layer 306 and the adjustment layer 308 are made of the same material, and the transition layer 306 and the adjustment layer 308 are formed in the same process step. The thin film bulk acoustic resonator further comprises an etch hole 304 through the tuning layer 308 and the piezoelectric layer 303.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a first sealing layer 309 disposed on the transition layer 306 on the edge region 301b of the substrate; a plurality of grooves 307 are arranged on the transition layer 306, the section width of at least one depth position of the groove 307 is larger than or equal to the section width of the top surface of the groove 307, a plurality of bulges 310 are arranged on the position of the first sealing layer 309 opposite to the groove 307, and the grooves 307 of the transition layer 306 and the bulges 310 of the first sealing layer 309 are mutually embedded; wherein the edge region 301b of the substrate surrounds the middle region 301a of the substrate.

The semiconductor structure provided by the embodiment of the disclosure further comprises: a second sealing layer 311; the second sealing layer 311 is arranged on the side, far away from the substrate 301, of the film bulk acoustic resonator, the second sealing layer 311 covers the substrate 301, and a first cavity is formed between the second sealing layer 311 and the middle region 301a of the substrate; the film bulk acoustic resonator is located in the first cavity.

The specific process for forming the film bulk acoustic resonator in the semiconductor structure provided by the disclosed embodiment is as follows: forming a sacrificial layer (not illustrated in fig. 7) and a lower electrode layer 302 covering the sacrificial layer on the middle region 301a of the substrate; forming a piezoelectric layer 303 overlying the lower electrode layer 302 on the substrate 301, and forming an upper electrode layer 305 overlying the piezoelectric layer 303 on the central region 301a of the substrate; forming a transition layer 306 on an edge region 301b of the substrate while forming a regulation layer 308 covering the upper electrode layer 305 on the middle region 301a of the substrate; forming an etching hole 304 penetrating at least the piezoelectric layer 303 and the adjustment layer 308; the transition layer 306 is etched to form a plurality of recesses 307 and a first sealing material is applied over the transition layer 306 to form a first sealing layer 309 having a plurality of protrusions 310 opposite the recesses 307.

In an embodiment of the present disclosure, the material of the transition layer and the material of the adjustment layer may be the same, and the material of the transition layer includes at least one of: molybdenum Mo, gold Au, ruthenium Ru, chromium Cr, and platinum Pt.

In the embodiment of the present disclosure, the adjustment layer on the middle region of the substrate and the transition layer on the edge region of the substrate may be simultaneously formed through a plating process.

Forming the thin film bulk acoustic resonator in a semiconductor structure provided by the disclosed embodiments further comprises: and injecting an etchant into the etching hole exposed out of the sacrificial layer by a wet etching method, so that the etchant and the sacrificial layer are contacted and undergo a chemical reaction to generate a liquid product or a gaseous product, so as to remove the sacrificial layer, and form a second cavity between the lower electrode layer and the substrate.

In an embodiment of the disclosure, the material of the first sealing layer comprises at least one of: the photoresist and resin may be cured.

Here, the curable photoresist may include an ultraviolet curable photoresist. And coating an ultraviolet curable photoresist on the transition layer by using a spin coating process, irradiating by ultraviolet light, carrying out a crosslinking reaction, and curing to form a first sealing layer.

Here, the resin may include polyimide PI, polybenzoxazole PBO, benzocyclobutene BCB, silicone, and acrylate.

In the embodiment of the present disclosure, it is considered that the adhesion between the first sealing layer and the substrate is easily damaged by a hydrogen fluoride environment, and therefore, in the same process step, the transition layer and the adjustment layer are formed at the same time, and the materials of the transition layer and the adjustment layer are the same, so that the adhesion between the substrate and the first sealing layer is improved by the transition layer, and a process step of forming the transition layer does not need to be additionally added, which is beneficial to saving the manufacturing time and the manufacturing cost. Therefore, even if a hydrogen fluoride environment exists for a long time in the sacrificial layer releasing process, the adhesiveness between the substrate and the first sealing layer is difficult to damage, so that the adhesiveness between the substrate and the first sealing layer can be improved, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged. It should be noted that the adhesion between the substrate and the piezoelectric layer itself is good, and the adhesion between the substrate and the piezoelectric layer is good even in a hydrogen fluoride atmosphere.

Referring to fig. 8, fig. 8 is a partial perspective view of a top view of a semiconductor structure provided by an embodiment of the present disclosure, and more specifically, a top view through a second sealing layer on top of the semiconductor structure. As shown in fig. 8, the semiconductor structure includes: a wafer 401; the wafer 401 includes a plurality of chip regions 402 (shown as dashed boxes in fig. 8); a device structure disposed on an intermediate region of each chip region 402; a transition layer and a first sealing layer disposed on an edge region of each chip region 402, the transition layer having a plurality of grooves, a cross-sectional width of the grooves at least one depth position on a cross-section perpendicular to the wafer being greater than or equal to a cross-sectional width of the grooves at a top surface thereof; a plurality of bulges are arranged at the positions of the first sealing layer opposite to the grooves, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region of the chip region surrounds the middle region of the chip region.

In an embodiment of the present disclosure, the semiconductor structure further includes a second sealing layer; the second sealing layer is arranged on one side of the device structure far away from the wafer, the second sealing layer covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity. Fig. 8 is only used to illustrate the placement of the chip regions on the wafer through the second encapsulant layer on top of the semiconductor structures, and does not illustrate the specific device structures within each chip region.

In the embodiment of the disclosure, the distribution density of the grooves in the edge area close to the wafer and/or the chip area on the transition layer is greater than that of the grooves in the edge area far away from the wafer and/or the chip area; in the direction perpendicular to the wafer, the depth of the groove on the transition layer is greater in the edge region close to the wafer and/or the chip region than in the edge region far from the wafer and/or the chip region.

It should be noted that the larger the distribution density of the grooves on the transition layer is, the stronger the adhesion between the transition layer and the first sealing layer is; the greater the depth of the recess in the transition layer, the greater the adhesion between the transition layer and the first sealing layer. However, the greater the distribution density of the grooves on the transition layer and the greater the depth of the grooves on the transition layer, the weaker the strength of the transition layer, and the excessive grooves cause the transition layer to be easily broken. Therefore, it is necessary to adjust the distribution density and depth of the grooves on the transition layer by considering both the adhesion between the transition layer and the first sealing layer and the strength of the transition layer.

In the embodiment of the disclosure, the distribution density of the grooves in the edge area close to the wafer and/or the chip area on the transition layer is set to be greater than the distribution density of the grooves in the edge area far away from the wafer and/or the chip area; and the depth of the groove close to the edge area of the wafer and/or the chip area on the transition layer is larger than the depth of the groove far away from the edge area of the wafer and/or the chip area, so that a closed cavity is formed, the problem that external small molecules enter the closed cavity and are attached to the film bulk acoustic resonator is solved, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

Fig. 8 also illustrates that the device structure of each chip region 402 can be a thin film bulk acoustic resonator, which includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer 403, and an etching hole 404 penetrating at least the piezoelectric layer, in a direction pointing away from the wafer 401 near the wafer 401. The semiconductor structure further includes a pad 406, and the upper electrode layer 403 and the lower electrode layer of the thin film bulk acoustic resonator in each chip region 402 are electrically connected to the pad 406 through an electrode lead 405.

In the embodiment of the disclosure, the distribution density of the grooves close to the welding pads on the transition layer is greater than that of the grooves far away from the welding pads; the depth of the groove close to the welding pad on the transition layer is larger than that of the groove far away from the welding pad along the direction vertical to the wafer.

In the embodiment of the disclosure, the distribution density of the grooves close to the welding pads on the transition layer is set to be greater than that of the grooves far away from the welding pads; and the depth of the groove close to the welding pad on the transition layer is greater than that of the groove far away from the welding pad, so that a closed cavity is formed, the problem that external small molecules enter the closed cavity and are attached to the film bulk acoustic resonator is avoided, the performance of the film bulk acoustic resonator is improved, and the service life of the film bulk acoustic resonator is prolonged.

The embodiment of the disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a device structure disposed on the middle region of the substrate; a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position thereof in a cross-section perpendicular to the substrate being greater than or equal to a cross-sectional width at a top surface of the grooves; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region. In the embodiment of the disclosure, the transition layer is arranged between the substrate and the first sealing layer, the transition layer is provided with a plurality of grooves, and the cross-sectional width of at least one depth position of each groove is larger than or equal to the cross-sectional width of the top surface of each groove, so that the grooves on the transition layer and the protrusions on the first sealing layer are mutually embedded, and the adhesion between the substrate and the first sealing layer is improved.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the above-mentioned processes do not imply an order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description, and do not represent the advantages or disadvantages of the embodiments.

The above description is only a preferred embodiment of the present disclosure, and does not limit the scope of the present disclosure, and all equivalent structural changes made by using the contents of the specification and drawings of the present disclosure or other related technical fields directly/indirectly applied to the present disclosure are included in the scope of the present disclosure.

Claims (13)

1. A semiconductor structure, comprising:

a substrate;

a device structure disposed on the middle region of the substrate;

a transition layer and a first sealing layer disposed on an edge region of the substrate, the transition layer having a plurality of grooves disposed thereon, a cross-sectional width of the grooves at least one depth position thereof in a cross-section perpendicular to the substrate being greater than or equal to a cross-sectional width at a top surface of the grooves; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region.

2. The semiconductor structure of claim 1, further comprising a second sealing layer; wherein, the first and the second end of the pipe are connected with each other,

the second sealing layer is arranged on one side of the device structure far away from the substrate, the second sealing layer covers the substrate, and a first cavity is formed between the second sealing layer and the middle area of the substrate; the device structure is located within the first cavity.

3. The semiconductor structure of claim 1, wherein the sidewalls of the recess are uneven surfaces; and/or the bottom surface of the groove is an uneven surface.

4. The semiconductor structure of claim 1, wherein, in a cross-section perpendicular to the substrate, a ratio between a cross-sectional width at a bottom surface of the groove and a depth of the groove is greater than or equal to 10.

5. The semiconductor structure of claim 4,

the depth of the groove is larger than 500nm along the direction vertical to the substrate;

a cross-sectional width at a bottom surface of the groove is greater than 5 μm in a cross-section perpendicular to the substrate.

6. The semiconductor structure of claim 2, wherein in a case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, and an upper electrode layer with a second cavity therebetween, in a direction pointing away from the substrate in proximity to the substrate.

7. The semiconductor structure of claim 6, wherein the device structure further comprises an etch hole through at least the piezoelectric layer.

8. The semiconductor structure of claim 7,

the distribution density of the grooves close to the etching holes on the transition layer is greater than that of the grooves far away from the etching holes;

the depth of the groove on the transition layer close to the etching hole is larger than that of the groove far away from the etching hole along the direction vertical to the substrate.

9. The semiconductor structure of claim 2, wherein in a case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, an upper electrode layer, and an adjustment layer, in a direction pointing away from the substrate in proximity to the substrate, with a second cavity between the lower electrode layer and the substrate.

10. A semiconductor structure, comprising:

a wafer; the wafer comprises a plurality of chip areas;

a device structure disposed on the intermediate region of each of the chip regions;

the transition layer and the first sealing layer are arranged on the edge area of each chip area, a plurality of grooves are arranged on the transition layer, and the section width of at least one depth position of each groove on the section perpendicular to the wafer is larger than or equal to the section width of the groove on the top surface of the groove; a plurality of bulges are arranged at the positions, opposite to the grooves, of the first sealing layer, and the grooves of the transition layer and the bulges of the first sealing layer are mutually embedded; wherein the edge region surrounds the middle region.

11. The semiconductor structure of claim 10,

the distribution density of the grooves on the transition layer close to the edge area of the wafer and/or the chip area is greater than that of the grooves on the edge area far away from the wafer and/or the chip area;

in a direction perpendicular to the wafer, a depth of the groove on the transition layer near an edge region of the wafer and/or the chip region is greater than a depth of the groove far from the edge region of the wafer and/or the chip region.

12. The semiconductor structure of claim 10, further comprising a second encapsulation layer; wherein, the first and the second end of the pipe are connected with each other,

the second sealing layer is arranged on one side of the device structure far away from the wafer, the second sealing layer covers the chip area, and a first cavity is formed between the second sealing layer and the middle area of the chip area; the device structure is located within the first cavity.

13. The semiconductor structure of claim 12, wherein in the case where the device structure is a thin film bulk acoustic resonator, the thin film bulk acoustic resonator comprises a lower electrode layer, a piezoelectric layer, and an upper electrode layer, in a direction pointing away from the wafer, closer to the wafer;

the semiconductor structure further comprises a welding pad, and the upper electrode layer and the lower electrode layer of the film bulk acoustic resonator in each chip area are electrically connected with the welding pad through electrode leads; wherein the content of the first and second substances,

the distribution density of the grooves close to the welding pads on the transition layer is greater than that of the grooves far away from the welding pads;

and along the direction vertical to the wafer, the depth of the groove close to the welding pad on the transition layer is greater than that of the groove far away from the welding pad.

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