CN218162419U

CN218162419U - Shortwave baseband signal filtering control circuit based on DSP

Info

Publication number: CN218162419U
Application number: CN202221732349.0U
Authority: CN
Inventors: 沈旭; 周成; 冯政曦
Original assignee: Changzhou Guoguang Data Communication Co ltd
Current assignee: Changzhou Guoguang Data Communication Co ltd
Priority date: 2022-07-05
Filing date: 2022-07-05
Publication date: 2022-12-27
Anticipated expiration: 2032-07-05

Abstract

The utility model discloses a shortwave baseband signal filter control circuit based on DSP, including analog/digital conversion circuit, DSP treater unit, FLASH memory, the crystal oscillator circuit, power supply circuit and external interface circuit, DSP treater unit includes the main DSP treater of electricity connection and follows the DSP treater, analog/digital conversion circuit, main DSP treater and FLASH memory electricity connection in proper order, analog/digital conversion circuit, main DSP treater and follow DSP treater all are connected with the crystal oscillator circuit electricity, power supply circuit converts outside DC power supply into the required power of analog/digital conversion circuit and DSP treater unit, external interface circuit provides JTAG debugging interface, the user serial ports, analog input output interface and power supply interface. The utility model discloses simplify the circuit, reduced the circuit scale, improved the data processing precision, can dispose working parameter according to user's demand is nimble simultaneously, effective filtering if multiple noise interference such as single audio noise, multi-audio noise and white noise, improves short wave communication's communication quality.

Description

Shortwave baseband signal filtering control circuit based on DSP

Technical Field

The utility model relates to a filter circuit technical field especially relates to a shortwave baseband signal filtering control circuit based on DSP.

Background

A DSP (digital signal processor) is a unique microprocessor, and is a device that processes a large amount of information with digital signals. The working principle is that the analog signal is received and converted into a digital signal of 0 or 1, then the digital signal is modified, deleted and strengthened, and the digital data is interpreted back to the analog data or the actual environment format in other system chips. It has not only programmability, but also its real-time running speed can reach tens of millions of complex instruction programs per second, far exceeding general microprocessor, and is an increasingly important computer chip in the digital electronic world.

With the wide application of short-wave communication technology and the development of other wireless communication technologies, the noise of short-wave communication is also increasingly complex and diverse, so that a filter circuit is often required to be added in front of a short-wave modem to increase the anti-interference capability of the modem in the current short-wave communication equipment, the traditional filter circuit is usually built by adopting an analog device, different filter circuits are built for different audio noises, and the short-wave communication equipment has the advantages of complex circuit, larger volume, lower precision, easy aging of part of analog devices, larger performance change along with time and temperature, difficult maintenance, inflexible design, difficulty in adapting to various application scenes and incapability of meeting the miniaturization requirement.

SUMMERY OF THE UTILITY MODEL

The utility model aims at prior art's weak point and propose a shortwave baseband signal filtering control circuit based on DSP, simplify the circuit, reduced the circuit scale, improved the data processing precision, can dispose working parameter according to user's demand is nimble simultaneously, effective filtering is like multiple noise interference such as single audio noise, multi-audio noise and white noise, improves short wave communication's communication quality.

Realize the utility model discloses purpose technical scheme is:

the utility model provides a shortwave baseband signal filter control circuit based on DSP, includes analog/digital conversion circuit, DSP treater unit, FLASH memory, crystal oscillator circuit, power supply circuit and external interface circuit, DSP treater unit is including the main DSP treater and the follow DSP treater of electricity connection, analog/digital conversion circuit, main DSP treater and FLASH memory electricity in proper order connect, analog/digital conversion circuit, main DSP treater and follow DSP treater all are connected with the crystal oscillator circuit electricity, power supply circuit's input termination external DC power supply, the output connects analog/digital conversion circuit and DSP treater unit respectively, external interface circuit and main DSP treater, follow DSP treater, analog/digital conversion circuit and external DC power supply electricity are all connected and are suitable for providing JTAG debugging interface, user's serial ports, analog input output interface and power source interface.

Further, the master DSP processor and the slave DSP processor adopt TMS320VC5510 series.

Furthermore, the EMIF interface of the master DSP processor and the slave DSP processor are in bidirectional electrical connection by adopting an HPI interface, and the slave DSP processor is hung on an EMIF bus of the master DSP processor through the HPI interface.

Further, the FLASH memory adopts AT45DB161D series and is in bidirectional electrical connection with the main DSP processor by adopting an McBSP bus.

Further, the analog-to-digital conversion circuit adopts TLV320AIC20 audio codec, and is in bidirectional electrical connection with the main DSP processor by adopting McBSP bus.

Further, the crystal oscillator circuit comprises a chip X1, a capacitor C14, a NOT gate logic gate circuit chip U11, a resistor R12, a resistor R13, a resistor R14 and a resistor R15; one end of the capacitor C14 is connected with a pin 3 of the chip X1, the other end of the capacitor C14, the resistor R11, the resistor R12 and the resistor R13 are all connected with a pin 1 of the NOT gate logic gate circuit chip U11, the other end of the resistor R12 is grounded, and the other end of the resistor R13 is connected with a pin 2 of the NOT gate logic gate circuit chip U11; one end of the resistor R15 is connected with a pin 4 of the NOT gate logic gate circuit chip U11, and the other end is connected with an analog/digital conversion circuit; one end of the resistor R14 is connected with a pin 6 of the NOT gate logic gate circuit chip U11, and the other end of the resistor R is simultaneously connected with the master DSP processor and the slave DSP processor. The 4 pins of the chip X1 are connected with an external direct current power supply.

Further, the power supply circuit comprises a power supply chip U9, a power supply chip U10, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C60, an inductor L3 and an inductor L4; the model of the power supply chip U9 is TPS62224, and the model of the power supply chip U10 is TPS62222DDC; one end of the capacitor C45 and the

pins

3 and 1 of the power chip U9 are connected with an external direct-current power supply, and the other end of the capacitor C45 is connected with a GND signal; one end of the inductor L3 is connected with the pin 5 of the power chip U9, and the other end of the inductor L3, one end of the capacitor C46, one end of the capacitor C47 and the pin 4 of the power chip U9 are connected with the DSP processor unit; the other end of the capacitor C46 is connected with a GND signal; the other end of the capacitor C47 is connected with a GND signal; one end of the capacitor C48 and the

pins

3 and 1 of the power supply chip U10 are connected with an external direct-current power supply, and the other end of the capacitor C is connected with a GND signal; one end of the inductor L4 is connected with the pin 5 of the power supply chip U10, and the other end of the inductor L4, one end of the capacitor C48, one end of the capacitor C60 and the pin 4 of the power supply chip U10 are connected with an analog/digital conversion circuit; the other end of the capacitor C48 is connected with a GND signal; the other end of the capacitor C60 is connected with a GND signal.

Furthermore, the external interface circuit comprises a connector P1 and a connector P2, wherein pins 1 to 7 of the connector P1 are respectively connected with pins L17, L16, L15, K14, C17, R16 and L14 of the main DSP 6, and a JTAG debugging port of the main DSP 6 is provided; the pin 8 and the pin 9 of the connector P1 are respectively connected with the pin P3 and the pin T16 of the main DSP 6, so as to provide a user serial port; pins 1 to 7 of the connector P2 are respectively connected with pins L17, L16, L15, K14, C17, R16 and L14 of the slave DSP processor 7, and a JTAG debugging port of the slave DSP processor 7 is provided;

pins

8 and 9 of the connector P2 are connected with an external direct current power supply, pins 10 are connected with an AGND _ M signal, and pins 11 are connected with a GND signal to provide a power supply interface.

By adopting the technical scheme, the utility model discloses following beneficial effect has:

(1) The utility model discloses a DSP treater unit is as control circuit and data processing's core, fine throughput has, small, make the product realize the miniaturization, the data processing mode that adopts the digitization has replaced the wave filter that comprises analogue device, the circuit has been simplified, the circuit scale has been reduced, the data processing precision has been improved, can be simultaneously according to the nimble working parameter that disposes of user's demand, effective filtering is like multiple noise interference such as single audio noise, multi-audio noise and white noise, improve short wave communication's communication quality.

(2) The utility model discloses main DSP treater all adopts TMS320VC5510 series with following the DSP treater, and the code execution rate is high and the low power dissipation.

(3) The utility model discloses the EMIF interface of main DSP treater and the HPI interface connection from the DSP treater hang on the EMIF bus to the DSP treater through the HPI interface from the DSP treater for communication between the DSP treater does not have the expense of hardware and software completely, can not interrupt the operation of DSP normal procedure, and data transmission is fast.

(4) The utility model discloses FLASH memory adopts AT45DB161D series, has the high capacity, and low pin count, the advantage of low-voltage and low-power consumption is favorable to the hardware overall arrangement, has strengthened system reliability, falls to the minimum with switching noise to dwindle the size of encapsulation, be favorable to the product to realize the miniaturization more.

(5) The utility model discloses a type modulus converting circuit adopts TLV320AIC20 audio frequency codec, has high-quality sound source support, and the fidelity is high, and conversion efficiency is high.

(6) The utility model discloses the crystal oscillator circuit is succinct, can provide stable, accurate single-frequency oscillation to provide essential clock signal for whole circuit system.

(7) The utility model discloses a set up power supply circuit, adopt power chip U9 and power chip U10 to convert outside DC power supply into the required working power supply of analog-to-digital conversion circuit and DSP treater unit.

(8) The utility model discloses a set up external interface circuit, conveniently connect.

Drawings

In order that the present invention may be more readily and clearly understood, the following detailed description of the present invention is provided in connection with the accompanying drawings, in which:

fig. 1 is a schematic block diagram of the circuit of the present invention.

Fig. 2 is a circuit diagram of the main DSP processor of the present invention.

Fig. 3 is a circuit diagram of the slave DSP processor of the present invention.

Fig. 4 is a circuit diagram of a FLASH memory according to the present invention.

Fig. 5 is a circuit diagram of the analog/digital conversion circuit of the present invention.

Fig. 6 is a circuit diagram of the crystal oscillator of the present invention.

Fig. 7 is a power supply circuit diagram of the present invention.

Fig. 8 is a circuit diagram of an external interface of the present invention.

The reference numbers in the drawings are:

the digital-to-analog conversion circuit comprises an analog-to-digital conversion circuit 1, a FLASH memory 2, a crystal oscillator circuit 3, a power supply circuit 4, an external interface circuit 5, a master DSP processor 6 and a slave DSP processor 7.

Detailed Description

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

(example 1)

The DSP-based short-wave baseband signal filtering control circuit shown in FIGS. 1 to 8 comprises an analog/digital conversion circuit 1, a DSP processor unit, a FLASH memory 2, a crystal oscillator circuit 3, a power supply circuit 4 and an external interface circuit 5, wherein the DSP processor unit comprises a master DSP processor 6 and a slave DSP processor 7 which are electrically connected, the analog/digital conversion circuit 1, the master DSP processor 6 and the FLASH memory 2 are electrically connected in sequence, and the analog/digital conversion circuit 1, the master DSP processor 6 and the slave DSP processor 7 are electrically connected with the crystal oscillator circuit 3. The input end of the power circuit 4 is connected with an external direct current power supply, the output end is respectively connected with the analog/digital conversion circuit 1 and the DSP processor unit, and the external interface circuit 5 is electrically connected with the main DSP processor 6, the slave DSP processor 7, the analog/digital conversion circuit 1 and the external direct current power supply and is suitable for providing a JTAG debugging interface, a user serial port, an analog input/output interface and a power supply interface.

By adopting the DSP unit as the core of the control circuit and the data processing, the device has good processing capacity and small volume, the miniaturization of the product is realized, a filter formed by analog devices is replaced by a digital data processing mode, the circuit is simplified, the circuit scale is reduced, the data processing precision is improved, meanwhile, the working parameters can be flexibly configured according to the user requirements, various noise interferences such as single audio noise, multi-audio noise, white noise and the like are effectively filtered, and the communication quality of short-wave communication is improved.

Specifically, the external dc power supply of this embodiment is 3.3V (D3V 3A terminal), the required working power supply of the DSP unit is 1.6V (D1V 6A terminal), and the working power supply of the analog/digital conversion circuit 1 is 1.8V (D1V 8A terminal).

The power supply circuit 4 comprises a power supply chip U9, a power supply chip U10, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C60, an inductor L3 and an inductor L4. The model of the power supply chip U9 is TPS62224, and the model of the power supply chip U10 is TPS62222DDC. One end of the capacitor C45 and the pin 3 and the pin 1 of the power chip U9 are connected with the end D3V3A, and the other end of the capacitor C45 is connected with a GND signal; one end of the inductor L3 is connected with a pin 5 of the power supply chip U9, and the other end of the inductor L3, one end of the capacitor C46, one end of the capacitor C47 and a pin 4 of the power supply chip U9 are connected with a D1V6A end; the other end of the capacitor C46 is connected with a GND signal; the other end of the capacitor C47 is connected with a GND signal; one end of the capacitor C48 and the

pins

3 and 1 of the power supply chip U10 are connected with the end D3V3A, and the other end is connected with a GND signal; one end of the inductor L4 is connected with the pin 5 of the power supply chip U10, and the other end of the inductor L4, one end of the capacitor C48, one end of the capacitor C60 and the pin 4 of the power supply chip U10 are connected with the end D1V 8A; the other end of the capacitor C48 is connected with a GND signal; the other end of the capacitor C60 is connected with the GND signal. Through power chip U9 and power chip U10, convert the 3.3V power into 1.6V and 1.8V working power, provide stable working power for whole circuit system.

The external interface circuit 5 comprises a connector P1 and a connector P2, pins 1 to 7 of the connector P1 are respectively connected with a K14 pin, a C17 pin, an L16 pin, an L15 pin, an L17 pin, an R16 pin and an L14 pin of the main DSP processor 6, and a JTAG debugging port of the main DSP processor 6 is provided; the pin 8 and the pin 9 of the connector P1 are respectively connected with the pin P3 and the pin T16 of the main DSP 6, so as to provide a user serial port; pins 1 to 7 of the connector P2 are respectively connected with a pin K14, a pin C17, a pin L16, a pin L15, a pin L17, a pin R16 and a pin L14 of the slave DSP processor 7, and a JTAG debugging port of the slave DSP processor 7 is provided;

pins

8 and 9 of the connector P2 are connected to the terminal D3V3A, pin 10 is connected to AGND _ M (analog ground) signal, and pin 11 is connected to GND (ground) signal, so as to provide a power interface. Through setting up external interface circuit 5, conveniently connect.

The master DSP processor 6 and the slave DSP processor 7 both adopt TMS320VC5510 series, and have high code execution rate and low power consumption. The main DSP processor 6 comprises a chip U1, and a resistor R7, a resistor R6, a resistor R5, a resistor R4, a resistor R3, a resistor R2 and a resistor R1 which are respectively and electrically connected with a R16 pin, a L14 pin, a P1 pin, a T2 pin, a M4 pin, a k4 pin and an E5 pin of the chip U1, and the slave DSP processor 7 comprises a chip U6, and a resistor R35, a resistor R34, a resistor R33, a resistor R32, a resistor R31 and a resistor R30 which are respectively and electrically connected with the R16 pin, the L14 pin, the P1 pin, the T2 pin, the M4 pin and the E5 pin of the chip U6.

The EMIF interface of the main DSP processor 6 is in bidirectional electrical connection with the HPI interface of the slave DSP processor 7, the slave DSP processor 7 is hung on an EMIF bus of the main DSP processor 6 through the HPI interface and used for communication between the DSP processors, the overhead of hardware and software is completely avoided, the normal program operation of the DSP cannot be interrupted, and the data transmission is fast. Specifically, the pin J4, the pin H3, the pin H4, the pin G2, the pin F4, the pin G3, the pin G4, the pin F2, the pin F3, the pin E1, the pin C1, the pin A2, the pin A4, the pin C5, the pin C4, the pin C6, the pin A6, the pin C7, the pin B7, the pin D8, the pin E2, the pin D2, the pin C2, the pin E3, the pin D3, the pin C3, the pin B3, the pin D4, the pin B4, the pin D5, the pin B5, the pin D6, the pin B6, the pin A8, the pin D7, the pin C8, the pin G1, the pin J3, the pin R14, the pin T13, the pin P13 of the chip U1, the pin N17 of the chip U6 respectively, the M14 pin, the M15 pin, the K16 pin, the J15 pin, the H16 pin, the G17 pin, the E14 pin, the D15 pin, the E15 pin, the F14 pin, the G14 pin, the J16 pin, the K17 pin, the J14 pin, the H14 pin, the G15 pin, the F15 pin, the E16 pin, the D9 pin, the D10 pin, the D11 pin, the D12 pin, the D13 pin, the A15 pin, the C14 pin, the C13 pin, the C12 pin, the C11 pin, the C10 pin, the C9 pin, the B15 pin, the B11 pin, the B13 pin, the B16 pin, the C15 pin, the B17 pin, the D14 pin and the B14 pin are connected.

A5 pin, N6 pin, N10 pin, A14 pin, E6 pin, E10 pin, F5 pin, K5 pin, E7 pin, F17 pin, L1 pin, P17 pin, R1 pin, U4 pin and U12 pin of the chip U1 are connected with the end D1V 6A; the F1 pin, the A3 pin, the A7 pin, the M17 pin, the A12 pin, the D1 pin, the D17 pin, the N1 pin, the U6 pin and the U14 of the chip U1 are connected with a D3V3A end; a pin A1, a pin A9, a pin A17, a pin J17, a pin A10, a pin B1, a pin H17, a pin A16, a pin J1, a pin U2, a pin U10, a pin T17, a pin U1, a pin U9 and a pin U17 of the chip U1 are connected with a GND end.

A5 pin, an N6 pin, an N10 pin, an A14 pin, an E6 pin, an E10 pin, an F5 pin, a K5 pin, an E7 pin, an F17 pin, an L1 pin, a P17 pin, an R1 pin, a U4 pin and a U12 pin of the chip U6 are connected with a D1V6A end; the F1 pin, the A3 pin, the A7 pin, the M17 pin, the A12 pin, the D1 pin, the D17 pin, the N1 pin, the U6 pin and the U14 of the chip U6 are connected with a D3V3A end; a pin A1, a pin A9, a pin A17, a pin J17, a pin A10, a pin B1, a pin H17, a pin A16, a pin J1, a pin U2, a pin U10, a pin T17, a pin U1, a pin U9 and a pin U17 of the chip U6 are connected with a GND end.

The FLASH memory 2 adopts AT45DB161D series, has the advantages of high capacity, low pin count, low voltage and low power consumption, is beneficial to hardware layout, enhances the reliability of the system, reduces the switching noise to the minimum, reduces the size of the package, and is more beneficial to realizing miniaturization of the product. Specifically, the FLASH memory 2 includes a chip U3, a capacitor C11, a capacitor C12, a resistor R9, and a resistor R10, where one end of the capacitor C11 is connected to the GND terminal, the other end is connected to pin 6 of the chip U3, both the capacitor C12 and the resistor R10 are connected to pin 3 of the chip U3, and the resistor R9 is connected to pin 5 of the chip U3. The FLASH memory 2 is in bidirectional electrical connection with the main DSP processor 6 by adopting an McBSP bus, wherein

pins

1, 2, 3, 4 and 8 of the chip U3 are respectively connected with pins R10, U7, G16, N2 and T6 of the chip U1. A pin 6 of the chip U3 is connected with a terminal D3V3A, and a pin 7 is connected with GND.

The analog/digital conversion circuit 1 adopts TLV320AIC20 audio codec, and comprises a chip U5, a resistor R501, a resistor R502, a resistor R503, a resistor R504, a resistor R505, a capacitor C501, a capacitor C502, a capacitor C503, a capacitor C504, a capacitor C505, a capacitor C506 and a capacitor C507, wherein one end of the resistor R501, the resistor R502, the resistor R503 and the resistor R504 is respectively connected with the capacitor C501, the capacitor C502, the capacitor C503 and the capacitor C504, the other end of the resistor R501, the resistor R502 and the resistor R504 is respectively connected with the 45 pin, the 44 pin, the 46 pin and the 47 pin of the chip U5, the other ends of the capacitor C502 and the capacitor C504 are respectively a signal input end and a signal output end, two ends of the resistor R505 are respectively connected with the 14 pin and the 9 pin of the chip U5, and the other ends of the capacitor C505, the capacitor C506 and the capacitor C507 are respectively connected with the 15 pin, the 12 pin and the 27 pin of the chip U5. The analog/digital conversion circuit 1 is also in bidirectional electrical connection with the main DSP processor 6 by adopting an McBSP bus, wherein the pin R5 and the pin U8 of the chip U1 are both connected with the pin 20 of the chip U5, the pin R6 and the pin R9 of the chip U1 are both connected with the pin 19 of the chip U5, and the pin U11 and the pin R7 of the chip U1 are respectively connected with the pin 18 and the pin 17 of the chip U5.

Pins

21, 11, 9, 12, 27, 33, 5 and 42 of the chip U5 are connected with the end D3V 3A; a pin 15 of the chip U5 is connected with a terminal D1V 8A; pins 43, 32 and 6 of the chip U5 are connected with an AGND _ M end; pins 13, 25, 29, 24 and 16 of the chip U5 are connected with the GND terminal.

The crystal oscillator circuit 3 comprises a chip X1, a capacitor C14, an NOT gate logic gate circuit chip U11, a resistor R12, a resistor R13, a resistor R14 and a resistor R15. The model of the NOT gate logic gate circuit chip U11 is SN74LV04A, one end of a capacitor C14 is connected with a pin 3 of the chip X1, the other end of the capacitor C14, a resistor R11, a resistor R12 and a resistor R13 are all connected with a pin 1 of the NOT gate logic gate circuit chip U11, the other end of the resistor R12 is grounded, and the other end of the resistor R13 is connected with a pin 2 of the NOT gate logic gate circuit chip U11; one end of the resistor R15 is connected with a pin 4 of the NOT gate logic gate circuit chip U11, and the other end of the resistor R is connected with a pin 22 of the chip U5; one end of the resistor R14 is connected with the pin 6 of the NOT gate logic gate circuit chip U11, and the other end is simultaneously connected with the pin F16 of the chip U1 and the pin F16 of the chip U6. The 4 pins of the chip X1 are connected with the D3V3A end. The circuit is simple, and can provide stable and accurate single-frequency oscillation, thereby providing a basic clock signal for the whole circuit system.

The working principle of this embodiment is that a user performs working parameter configuration through a serial port, that is, a P3 pin and a T16 pin of a chip U1, frequency information of 8 frequency points in a short-wave baseband signal can be configured at most, parameters of a plurality of band-pass digital filters are stored in a DSP processing unit, the DSP processing unit selects a suitable band-pass digital filter according to the frequency information, an analog signal is sampled by an analog/digital conversion circuit 1 and then converted into digital signal data, the DSP processing unit filters the signal data through the plurality of band-pass digital filters, then the calculation result of each digital band-pass filter is calculated through AGC (automatic gain control) to perform signal synthesis, and then the analog/digital conversion circuit restores the digital signal data into an analog signal, thereby effectively filtering noise in an original signal, adjusting the size of the signal, and improving the receiving effect.

The embodiment adopts the DSP processor unit as the core of control circuit and data processing, has good processing capacity and small volume, realizes miniaturization of products, adopts a digital data processing mode to replace a filter consisting of analog devices, simplifies circuits, reduces circuit scale, improves data processing precision, can flexibly configure working parameters according to user requirements, effectively filters various noise interferences such as single audio noise, multi-audio noise, white noise and the like, and improves the communication quality of short-wave communication.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. The utility model provides a shortwave baseband signal filtering control circuit based on DSP which characterized in that: the digital signal processor comprises an analog-to-digital conversion circuit (1), a DSP processor unit, a FLASH memory (2), a crystal oscillator circuit (3), a power circuit (4) and an external interface circuit (5), wherein the DSP processor unit comprises a master DSP processor (6) and a slave DSP processor (7) which are electrically connected, the analog-to-digital conversion circuit (1), the master DSP processor (6) and the FLASH memory (2) are sequentially and electrically connected, the analog-to-digital conversion circuit (1), the master DSP processor (6) and the slave DSP processor (7) are electrically connected with the crystal oscillator circuit (3), the input end of the power circuit (4) is connected with an external direct current power supply, the output end of the power circuit is respectively connected with the analog-to-digital conversion circuit (1) and the DSP processor unit, and the external interface circuit (5) is electrically connected with the master DSP processor (6), the slave DSP processor (7), the analog-to-digital conversion circuit (1) and the external direct current power supply and is suitable for providing a JTAG debugging interface, a user serial port, an analog input and an analog output interface.

2. The DSP-based short-wave baseband signal filtering control circuit of claim 1, wherein: the master DSP processor (6) and the slave DSP processor (7) both adopt TMS320VC5510 series.

3. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the EMIF interface of the main DSP processor (6) is in bidirectional electrical connection with the HPI interface of the slave DSP processor (7), and the slave DSP processor (7) is mounted on the EMIF bus of the main DSP processor (6) through the HPI interface.

4. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the FLASH memory (2) adopts AT45DB161D series and is in bidirectional electric connection with the main DSP processor (6) by adopting an McBSP bus.

5. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the analog/digital conversion circuit (1) adopts TLV320AIC20 audio codec, and is in bidirectional electrical connection with the main DSP processor (6) by adopting McBSP bus.

6. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the crystal oscillator circuit (3) comprises a chip X1, a capacitor C14, a NOT gate logic gate circuit chip U11, a resistor R12, a resistor R13, a resistor R14 and a resistor R15; one end of the capacitor C14 is connected with a pin 3 of the chip X1, the other end of the capacitor C14, the resistor R11, the resistor R12 and the resistor R13 are all connected with a pin 1 of the NOT gate logic gate circuit chip U11, the other end of the resistor R12 is grounded, and the other end of the resistor R13 is connected with a pin 2 of the NOT gate logic gate circuit chip U11; one end of the resistor R15 is connected with a pin 4 of the NOT gate logic gate circuit chip U11, and the other end is connected with the analog/digital conversion circuit (1); one end of the resistor R14 is connected with a pin 6 of the NOT gate logic gate circuit chip U11, and the other end is simultaneously connected with the master DSP processor (6) and the slave DSP processor (7).

7. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the power supply circuit (4) comprises a power supply chip U9, a power supply chip U10, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, a capacitor C49, a capacitor C60, an inductor L3 and an inductor L4; pins 1 and 3 of the power chip U9 are connected with an external direct-current power supply, one end of the capacitor C45 is connected with the pin 1 of the power chip U9, and the other end of the capacitor C45 is connected with a GND signal; one end of the inductor L3 is connected with a pin 5 of the power supply chip U9, the other end of the inductor L3 is simultaneously connected with a pin 4 of the power supply chip U9, the capacitor C46, the capacitor C47 and the DSP processor unit, and the other ends of the capacitor C46 and the capacitor C47 are connected with GND signals; pins 1 and 3 of the power supply chip U10 are both connected with an external direct-current power supply, one end of the capacitor C48 is connected with pin 1 of the power supply chip U10, and the other end of the capacitor C48 is connected with a GND signal; one end of the inductor L4 is connected with a pin 5 of the power supply chip U10, the other end of the inductor L4 is simultaneously connected with a pin 4 of the power supply chip U10, the capacitor C60, the capacitor C49 and the analog/digital conversion circuit (1), and the other ends of the capacitor C60 and the capacitor C49 are connected with GND signals.

8. The DSP-based shortwave baseband signal filtering control circuit of claim 1, wherein: the external interface circuit comprises a connector P1 and a connector P2, wherein the connector P1 is connected with the main DSP (6) and the analog/digital conversion circuit (1) and provides a user serial port, a JTAG debugging port of the main DSP (6) and an analog input/output interface for the outside; the connector P2 is connected with the slave DSP processor (7) and an external direct current power supply, and provides a JTAG debugging port and a power supply interface of the slave DSP processor (7) for the outside.