CN218162208U - Multi-path pulse width modulation comparator applied to buck DC-DC converter - Google Patents

Multi-path pulse width modulation comparator applied to buck DC-DC converter Download PDF

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CN218162208U
CN218162208U CN202222228876.4U CN202222228876U CN218162208U CN 218162208 U CN218162208 U CN 218162208U CN 202222228876 U CN202222228876 U CN 202222228876U CN 218162208 U CN218162208 U CN 218162208U
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pmos tube
tube
pmos
drain electrode
current
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不公告发明人
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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Xi'an Shuimuxinbang Semiconductor Design Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The utility model discloses a multichannel pulse width modulation comparator mainly solves current converter and needs three comparator and two sampling current just can accomplish converter control problem under the various load condition. The utility model comprises a comparison voltage generation module (11) and a multi-path pulse width modulation comparison module (12), wherein the module (11) generates an addition signal, an overcurrent protection reference voltage after modulation and a light load peak current control reference voltage after modulation according to an inductance sampling current and a slope compensation current; the module (12) can automatically compare the added signal with a corresponding reference signal according to the output value of the error amplifier under different load conditions, and the stable control of the converter is completed. On the premise of not influencing various performances and functions of the converter, the processing of the inductive current information can be completed only by one sampling current and one comparator, the converter is controlled under various load states, and the power consumption and the area of the converter are reduced.

Description

Multi-path pulse width modulation comparator applied to buck DC-DC converter
Technical Field
The utility model relates to a be applied to electronic circuit technical field, relate to analog integrated circuit, especially a be applied to multichannel pulse width modulation comparator of step-down DC-DC converter.
Background
With the rapid development of power supply systems in the fields of industry, automobiles, and communications, the step-down DC-DC converter is widely used by virtue of its higher efficiency and greater on-load capability. In the constant frequency control technology of the step-down DC-DC converter, a voltage mode and a current mode are two mainstream control architectures. The voltage mode has only a single voltage feedback loop, so when the load current or the input voltage changes, the system must detect the change of the output voltage and then adjust through the feedback loop, which undoubtedly slows down the response speed of the system. Therefore, the current mode of adding a current feedback loop in addition to the voltage feedback loop is becoming a more popular control architecture. The current feedback loop may sample the inductor current and convert it to a voltage signal, which then participates in the control of the converter along with the output feedback voltage of the voltage feedback loop. Depending on the way the current feedback is implemented, the current modes can be divided into three categories: peak current mode, valley current mode, and average current mode. The peak current mode is the most common and the widest application range, and therefore, the invention is provided based on the peak current mode.
Fig. 1 shows a main block diagram of a conventional peak current mode step-down DC-DC converter. It can be seen that in the module related to the inductor current, the control architecture uses three independent comparators in common and generates two independent sampling currents to cope with the control of the converter under various load conditions. In medium/heavy load conditions, the converter operates in a PWM mode. In this mode, the oscillator generates a clock signal and initiates a switching cycle, and the logic module immediately controls the driver module to turn on the high-side power MOSFET M H And turns off low side power MOSFET M L . Subsequently, the current I is sampled CS1 On-the-slope compensation signal I RAMP Is added and converted into V SUM In the pulseV in wide modulation comparator SUM Will be in contact with the output signal V of the error amplifier COMP A comparison is made. Once V is turned on SUM Increase to and V COMP If they are equal, the logic module will control the driving module to drive M H Turn off and turn M off L And is turned on until the next clock signal generated by the oscillator arrives. At the same time, another sample current I CS2 Is converted into a voltage signal V CS2 And is compared with an overcurrent protection reference voltage V in an overcurrent comparator TH_OC A comparison is made to detect the inductor current cycle by cycle and limit the peak inductor current. Once V is turned on CS2 Increase to and V TH_OC When equal, M H It will be immediately turned off. On the other hand, as the load decreases, the converter enters a standby mode. In this mode, V COMP Monitored by a standby mode comparator. Once V is turned on COMP Down to the standby reference voltage V TH_SBM Thereafter, the converter will exit the standby mode and turn on M H 。M H After conduction, the inductor current starts to rise, and in the light-load current comparator, V CS2 Reference voltage V controlled by preset light load peak current TH_LLC A comparison is made. At V CS2 Increase to and V TH_LLC At equal time, M H Is turned off. Therefore, the conventional peak current mode control architecture generates two independent sampling currents, and uses the over-current comparator, the pwm comparator and the light load current comparator to process the information related to the inductor current, which undoubtedly consumes more quiescent current and chip area.
Disclosure of Invention
The utility model aims at providing a multichannel pulse width modulation comparator to having not enough of peak current mode step-down type DC-DC converter for only need a sampling current and a comparator just can accomplish the processing of inductive current information, and carry out the control of converter under various load condition. The multi-path pulse width modulation comparator reduces the static current and the chip area of the converter, and meanwhile, the problem that the current limit threshold value changes along with the duty ratio is avoided, so that the DC-DC converter can be used in more application environments.
In order to achieve the purpose, the utility model comprises a comparison voltage generation module and a multi-path pulse width modulation comparison module;
the comparison voltage generation module samples the current I of the inductive current according to the inductive current sampling module CS And a slope compensation current I generated by the slope compensation module RAMP1 、I RAMP2 Generating an added signal V SUM And the modulated over-current protection reference voltage V THOC_MOD Modulated light load peak current control reference voltage V THLLC_MOD And output to the multi-channel pulse width modulation comparison module; the power supply comprises 15 PMOS tubes PM1- PM 15, 10 resistors R1-R3, R5-R11 and a bias current source; wherein:
the first PMOS tube PM1 to the fourteenth PMOS tube PM12 jointly form a cascode current mirror structure, wherein source electrodes of the first PMOS tube PM1, the third PMOS tube PM3, the fifth PMOS tube PM5, the seventh PMOS tube PM7, the ninth PMOS tube PM9 and the eleventh PMOS tube PM11 are jointly connected to a power supply voltage VCC, and grid electrodes of the first PMOS tube PM1 and the ninth PMOS tube PM7 are connected to a drain electrode of the first PMOS tube PM 1; the grid electrodes of the second PMOS tube PM2, the fourth PMOS tube PM4, the sixth PMOS tube PM6, the eighth PMOS tube PM8, the tenth PMOS tube PM10 and the twelfth PMOS tube PM12 are connected with the drain electrode of the second PMOS tube PM 2;
the source electrode of the second PMOS tube PM2 is connected with the drain electrode of the first PMOS tube PM1, and the drain electrode of the second PMOS tube PM2 is connected with the bias current source IB1;
the source electrode of the fourth PMOS transistor PM4 is connected to the drain electrode of the third PMOS transistor PM3, the drain electrode of the fourth PMOS transistor PM4 is connected to one end of an eleventh resistor R11, the other end of the eleventh resistor R11 is connected to one end of a ninth resistor R9 through a tenth resistor R10, and the other end of the ninth resistor R9 is connected to the ground GND; the common end of the eleventh resistor R11 and the tenth resistor R10 is connected with a slope compensation current I RAMP1 (ii) a The common end of the tenth resistor R10 and the ninth resistor R9 is connected with an inductive current sampling current I CS ；
The source of the sixth PMOS transistor PM6 is connected to the drain of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6 is connected to one end of an eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the sixth resistor R6 through a seventh resistor R7, and the sixth resistorThe other end of the R6 is connected to the ground GND through a fifth resistor R5; the common end of the eighth resistor R8 and the seventh resistor R7 is connected with the grid electrode of a fifteenth PMOS tube PM 15; the common end of the seventh resistor R7 and the sixth resistor R6 is connected with a slope compensation current I RAMP2 ；
The source electrode of the eighth PMOS tube PM8 is connected with the drain electrode of the seventh PMOS tube PM7, the drain electrode of the eighth PMOS tube PM8 is connected with the source electrode of the thirteenth PMOS tube PM13, and the eighth PMOS tube PM8 outputs the modulated overcurrent protection reference voltage V THOC_MOD (ii) a The grid electrode of the thirteenth PMOS pipe PM13 is connected with the drain electrode of the sixth PMOS pipe PM6, and the drain electrode of the thirteenth PMOS pipe PM13 is connected to the ground GND through a third resistor R3;
the source electrode of the tenth PMOS transistor PM10 is connected with the drain electrode of the ninth PMOS transistor PM9, the drain electrode of the tenth PMOS transistor PM10 is connected with the source electrode of the fifteenth PMOS transistor PM15, and the tenth PMOS transistor PM10 outputs the modulated light-load peak current control reference voltage V THLLC_MOD (ii) a The drain of the fifteenth PMOS transistor PM15 is connected to the ground GND through a third resistor R2;
the source of the twelfth PMOS transistor PM12 is connected to the drain of the eleventh PMOS transistor PM11, and the drain of the twelfth PMOS transistor PM12 is connected to the source of the fourteenth PMOS transistor PM14 and outputs an output addition signal V SUM (ii) a The gate of the fourteenth PMOS transistor PM14 is connected to the drain of the fourth PMOS transistor PM4, and the source thereof is connected to the ground GND through the first resistor R1.
The multi-channel PWM comparison module can be used for comparing the output V of the error amplifier under different load conditions COMP Automatically adding the signal V SUM And compared with the corresponding reference signal, thereby completing the stable control of the converter. The device comprises 4 PMOS tubes PM1-PM 4,8 NMOS tubes NM 1-NM 8 and a bias current source; wherein:
the fifth NMOS tube NM5 and the sixth NMOS tube NM6 form a current mirror structure, the sources of the current mirror structure are commonly connected with the ground GND, and the grids of the current mirror structure are connected with the drain of the fifth NMOS tube NM5 and the power supply VCC through the bias current IB 2; the drain electrode of the sixth NMOS tube NM6 provides tail current for the comparison stage;
the source electrodes of the first NMOS tube NM1, the second NMOS tube NM2 and the third NMOS tube NM3 are connected with the drain electrode of the sixth NMOS tube NM6 to form a comparison stage structure; grid and sum signal of the first NMOS tube NM1Number V SUM The drain electrode of the PMOS tube is connected with the drain electrode of the second PMOS tube PM 2; grid of second NMOS tube NM2 and error amplifier output signal V COMP The drain electrode of the NMOS transistor is connected with the source electrode of the fourth NMOS transistor NM 4; the grid electrode of the third NMOS tube NM3 and the modulated light load peak current control reference voltage V THLLC_MOD The drain electrode of the NMOS transistor is connected with the drain electrode of the second NMOS transistor NM 2;
the grid of the fourth NMOS tube NM4 and the modulated over-current protection reference voltage V THOC_MOD The drain electrode of the PMOS tube is connected with the drain electrode of the third PMOS tube PM 3;
the first PMOS tube PM1 and the second PMOS tube PM2 form a current mirror structure, the source electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with a power supply voltage VCC, and the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected to the drain electrode of the second PMOS tube PM 2; the drain electrode of the first PMOS pipe PM1 is connected with the drain electrode of the seventh NMOS pipe NM 7;
the seventh NMOS tube NM7 and the eighth NMOS tube NM8 form a current mirror structure, the sources of the current mirror structure are connected to the GND in common, and the gates of the current mirror structure are connected to the drain of the seventh NMOS tube NM 7;
the third PMOS tube PM3 and the fourth PMOS tube PM4 form a current mirror structure, the source electrodes of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with a power supply voltage VCC, and the grid electrodes of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected to the drain electrode of the third PMOS tube PM 3; the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the first NMOS tube NM8 and outputs an output signal PWM of the multi-path pulse width modulation comparison module.
Compared with the prior art, the utility model has the following advantage:
1. the utility model discloses owing to added multichannel pulse width modulation comparison module for only need a sampling current and a comparator just can accomplish the processing of inductive current information, and carry out the control of converter under various load condition.
2. The utility model discloses because the multichannel pulse width modulation comparison module who adopts can be according to load condition automatic switch-over and add signal V SUM Compared voltage, therefore, an extra control circuit is not needed to switch the compared voltage of the comparator, and the design of the circuit is greatly simplified.
3. The utility model discloses owing to adopt this kind of single comparator framework, overcurrent protection and light load down peak current control's response speed have also obtained the assurance under the condition that does not increase extra consumption. Therefore, on the premise of not influencing various performances and functions of the peak current mode step-down DC-DC converter, the power consumption and the area of the converter are reduced.
Drawings
Fig. 1 is an architecture diagram of a conventional peak current mode buck DC-DC converter;
fig. 2 is an architecture diagram of a peak current mode buck DC-DC converter with the addition of the multi-path pwm comparator of the present invention;
fig. 3 is a circuit diagram of a comparison voltage generation module in the multi-channel pwm comparator of the present invention;
fig. 4 is a circuit diagram of the multi-channel pwm comparator module of the multi-channel pwm comparator of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, the multi-path pwm comparator of the present invention comprises: a comparison voltage generation module 11 and a multi-channel pulse width modulation comparison module 12. Wherein, the comparison voltage generation module samples the current I of the inductive current according to the inductive current sampling module CS And a slope compensation current I generated by the slope compensation module RAMP1 、I RAMP2 Generating an added signal V SUM And the modulated over-current protection reference voltage V THOC_MOD And the modulated light load peak current control reference voltage V THLLC_MOD And outputs it to the multi-channel pulse width modulation comparison module 12; the multi-path PWM comparing module can be based on the output V of the error amplifier under different load conditions COMP Automatically adding the signal V SUM And compared with the corresponding reference signal, thereby completing the stable control of the converter.
As shown in fig. 3, the comparative voltage generation module includes 18 PMOS transistors PM1 to PM15, 10 resistors R1 to R3, R5 to R11, and a bias current source; wherein: the first PMOS tube PM1 to the fourteenth PMOS tube PM12 form a cascode current mirror structure and provide bias current for each branch of the circuit; the drain electrode of a first PMOS tube PM1 is connected with the source electrode of a second PMOS tube PM2, the drain electrode of a third PMOS tube PM3 is connected with the source electrode of a fourth PMOS tube PM4, the drain electrode of a fifth PMOS tube PM5 is connected with the source electrode of a sixth PMOS tube PM6, the drain electrode of a seventh PMOS tube PM7 is connected with the source electrode of an eighth PMOS tube PM8, the drain electrode of a ninth PMOS tube PM9 is connected with the source electrode of a tenth PMOS tube PM10, the drain electrode of an eleventh PMOS tube PM11 is connected with the source electrode of a twelfth PMOS tube PM12, PM1, PM3, PM5, PM7, PM9 and PM11 are connected with the gate electrode of a PM13, and the gate electrodes of PM2, PM4, PM6, PM8, PM10 and PM12 are connected with the gate electrode of a PM 14; the grid electrode of the first PMOS tube PM1 is connected with the drain electrode, the grid electrode of the second PMOS tube PM2 is connected with the drain electrode, and the drain electrode of the second PMOS tube PM2 is connected with the ground GND through the bias current IB1;
the ninth resistor R9 to the eleventh resistor R11 sample the inductive current I CS And a slope compensation current I RAMP1 Adding the voltage signals to the voltage signal and completing the conversion of the current voltage signal, connecting an eleventh resistor R11 and a tenth resistor R10 in series, and terminating the slope compensation current signal I by the common end of the R11 and the R10 RAMP1 The other end of the eleventh resistor R11 is connected with the drain electrode of the fourth PMOS tube PM4, and the other end of the tenth resistor R10 is connected with the ninth resistor R9; the resistors R10 and R9 are connected in series, and the common end of the resistors is connected with an inductive current sampling current signal I CS The other end of the R9 is connected with the ground GND;
the fifth resistor R5 to the eighth resistor R8 finish slope compensation current I RAMP2 Conversion to a voltage signal; the eighth resistor R8 and the eighth resistor R7 are connected in series, the other end of the eighth resistor R8 is connected with the drain electrode of the PMOS tube PM4, and the other end of the seventh resistor R7 is connected with the sixth resistor R6; resistors R7 and R6 are connected in series, and the common end of the resistors is connected with a slope compensation current signal I RAMP2 (ii) a The other end of the sixth resistor R6 is connected with the fifth resistor R5; the resistors R6 and R5 are connected in series, and the other end of the fifth resistor R5 is connected with the ground GND;
the thirteenth PMOS tube PM13 to the fifteenth PMOS tube PM15 and the first resistor R1 to the third resistor R3 are adjusted together to be output to a direct current working point of the input stage of the multi-path pulse width modulation comparison module; the grid electrode of the thirteenth PMOS pipe PM13 is connected with the drain electrode of the sixth PMOS pipe PM6, the drain electrode of the thirteenth PMOS pipe PM13 is connected to the ground through a resistor R3, and the source electrode of the thirteenth PMOS pipe PM13Connected with the drain electrode of the eighth PM8 and outputting a modulated over-current protection reference voltage V THOC_MOD (ii) a The gate of the fifteenth PMOS tube PM15 is connected with the common end of the resistors R7 and R8, the drain of the fifteenth PMOS tube PM15 is connected to the ground through the resistor R2, the source of the fifteenth PMOS tube PM15 is connected with the drain of the tenth PMOS tube PM10, and the fifteenth PMOS tube PM15 outputs the modulated light-load peak current control reference voltage V THLLC_MOD (ii) a The grid electrode of the fourteenth PMOS tube PM14 is connected with the drain electrode of the fourth PMOS tube PM4, the drain electrode of the fourteenth PMOS tube PM is connected to the ground through a resistor R1, the source electrode of the fourteenth PMOS tube PM is connected with the drain electrode of the twelfth PMOS tube PM12, and the added signal V is output SUM 。
As shown in fig. 4, the multi-channel pwm comparing module includes 4 PMOS transistors PM1 to PM4,8 NMOS transistors NM1 to NM8, and a bias current; wherein: the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 form a current mirror structure, so that a tail current is provided for an input stage of the comparator; the grid electrode and the drain electrode of the fifth NMOS tube NM5 are connected, and the fifth NMOS tube NM5 is connected with a power supply VCC through a bias current IB 2; the grid electrode of the sixth NMOS tube NM6 is connected with the grid electrode of the fifth NMOS tube NM5, and the drain electrode is connected with the source electrodes of the first NMOS tube NM1 and the second NMOS tube NM2, so that a current mirror structure is formed to provide tail current for the comparison stage;
the first NMOS tube NM1 to the fourth NMOS tube NM4 are 4 input stages of the multi-path pulse width modulation comparison module, and the output signal V of the error amplifier COMP The multi-path pulse width modulation comparison module can automatically switch and add the signal V according to the output voltage change of the converter and different load conditions SUM The reference signals are compared to control the converter under different load conditions. The grid electrode of the first NMOS tube NM1 and an addition signal V SUM The source electrode is connected with the source electrode of a second NMOS transistor NM2, and the drain electrode is connected with the drain electrode of a second PMOS transistor PM 2; grid of second NMOS tube NM2 and error amplifier output signal V COMP The source electrode is connected with the source electrode of the first NMOS tube NM1, and the drain electrode is connected with the source electrode of the fourth NMOS tube NM 4; grid of third NMOS tube NM3 and modulated light load peak current control reference voltage V THLLC_MOD The source electrode is connected with the source electrode of the second NMOS tube NM2, and the drain electrode is connected with the drain electrode of the second NMOS tube NM 2; fourth NMOS transistor NM4 grid and modulated overcurrent protection reference voltage V THC_MOD The source electrode is connected with the drain electrode of the second NMOS tube NM2, and the drain electrode is connected with the drain electrode of the third PMOS tube PM 3;
the first PMOS tube PM1 to the fourth PMOS tube PM4 and the NMOS tubes NM7 and NM8 convert double-end input of the multi-channel pulse width modulation comparison module into single-end output, and finally output a comparison result signal PWM. The grid electrode of the second PMOS tube PM2 is connected with the drain electrode, and the grid electrode of the third PMOS tube PM3 is connected with the drain electrode to form a diode connection structure; the grid electrode of the first PMOS tube PM1 is connected with the second PMOS tube PM2, and the drain electrode of the first PMOS tube PM1 is connected with the drain electrode of the NMOS tube NM 7; the grid electrode of the fourth PMOS tube PM4 is connected with the third PMOS tube PM3, and the drain electrode is connected with the NMOS tube NM 8; the grid electrode of the NMOS tube NM7 is connected with the drain electrode, and the drain electrode is connected with the drain electrode of the PMOS tube PM 1; the grid electrode of the NMOS tube NM8 is connected with the grid electrode of the NM7, and the drain electrode of the NMOS tube NM8 is connected with the drain electrode of the PMOS tube PM 4; the source electrodes of the PMOS tubes PM1, PM2, PM3 and PM4 are connected with a direct current power supply VCC; the sources of the NMOS tubes NM5, NM6, NM7 and NM8 are connected with the ground GND; and the drain electrode of the NMOS tube is the output signal PWM of the multi-path pulse width modulation comparison module.
The following briefly describes the multi-channel pulse width modulation comparison principle of the present invention:
firstly, the comparison voltage generation module respectively samples the current I CS And a slope compensation signal I RAMP1 And I RAMP2 Are converted into a voltage signal V together SUM 、V THOC_MOD And V THLLC_MOD To reduce errors due to temperature and device mismatch. The circuit comprises a zero temperature coefficient bias current IB1, cascode current mirrors PM1-PM6 and resistors R5-R11. Transistors PM7-PM15 and resistors R1-R3 are used to adjust the DC operating point of the output voltage signal. Based on this, V SUM 、V THOC_MOD And V THLLC_MOD Have the same temperature coefficient and contain the same slope compensation information, which can be respectively expressed as:
V SUM ＝I B1 ·(R 9 +R 10 +R 11 )+I RAMP1 ·(R 9 +R 10 )+I CS ·R 9 +V GS14
V THOC_MOD ＝I B1 ·(R 5 +R 6 +R 7 +R 8 )+I RAMP2 ·(R 5 +R 6 )+V GS13
V THLLC_MOD ＝I B1 ·(R 5 +R 6 +R 7 )+I RAMP2 ·(R 5 +R 6 )+V GS15
adding signal V is completed by multi-path pulse width modulation comparison module SUM And multiple reference signals (V) COMP /V THOC_MOD /V THLLC_MOD ) Comparison of (1). Through the automatic path selection characteristic of the bias current, the multipath comparator can cut off the tail current of the path which is not compared, thereby realizing V under different load conditions SUM And V COMP /V THOC_MOD /V THLLC_MOD The automatic comparison of (1). In medium/heavy load condition, V SUM Will be in contact with the output signal V of the error amplifier COMP Comparing to complete the regulation of the output voltage; in the fault state of over-large load current or short circuit output SUM Will and the modulated overcurrent protection reference voltage V THOC_MOD Comparing to prevent the damage of the chip caused by the overlarge inductive current; under light load condition, V SUM Will control the reference voltage V with another modulated light load peak current THLLC_MOD The comparison is made to limit the lowest value of the inductor current peak at light load conditions, thereby improving the efficiency of the converter. The output signal PWM of the multi-path pulse width modulation comparator is triggered when the following conditions are met:
V SUM ≥MIN[MAX(V COMP ，VT HLLC_MOD )，VT HOC_MOD
the above is only a preferred embodiment of the present invention, and does not constitute any limitation to the present invention, and it is obvious that various changes and modifications can be made to the circuit thereof under the concept of the present invention, but these are all protected by the present invention.

Claims (3)

1. A multi-path pulse width modulation comparator applied to a step-down DC-DC converter is characterized in that: the device comprises a comparison voltage generation module and a multi-path pulse width modulation comparison module;
the comparison voltage generation module samples the current I of the inductive current according to the inductive current sampling module CS And a slope compensation current I generated by the slope compensation module RAMP1 、I RAMP2 Generating an added signal V SUM Modulated over-current protection reference voltage V THOC_MOD Modulated light load peak current control reference voltage V THLLC_MOD And output to the multi-channel pulse width modulation comparison module;
the multi-path pulse width modulation comparison module can be used for outputting V according to the error amplifier under different load conditions COMP Automatically adding the signal V SUM And comparing with corresponding reference signals, thereby completing stable control of the converter.
2. The multi-channel PWM comparator applied to the buck DC-DC converter as claimed in claim 1, wherein the comparison voltage generation module comprises 15 PMOS transistors PM1 to PM15, 10 resistors R1 to R3, R5 to R11 and a bias current source;
the first PMOS tube PM1 to the fourteenth PMOS tube PM12 jointly form a cascode current mirror structure, wherein source electrodes of the first PMOS tube PM1, the third PMOS tube PM3, the fifth PMOS tube PM5, the seventh PMOS tube PM7, the ninth PMOS tube PM9 and the eleventh PMOS tube PM11 are jointly connected to a power supply voltage VCC, and grid electrodes of the first PMOS tube PM1 and the ninth PMOS tube PM7 are connected to a drain electrode of the first PMOS tube PM 1; the grid electrodes of the second PMOS tube PM2, the fourth PMOS tube PM4, the sixth PMOS tube PM6, the eighth PMOS tube PM8, the tenth PMOS tube PM10 and the twelfth PMOS tube PM12 are connected with the drain electrode of the second PMOS tube PM 2;
the source electrode of the second PMOS tube PM2 is connected with the drain electrode of the first PMOS tube PM1, and the drain electrode of the second PMOS tube PM2 is connected with the bias current source IB1;
the source of the fourth PMOS transistor PM4 is connected to the drain of the third PMOS transistor PM3, the drain of the fourth PMOS transistor PM4 is connected to one end of an eleventh resistor R11, the other end of the eleventh resistor R11 is connected to one end of a ninth resistor R9 through a tenth resistor R10, and the other end of the ninth resistor R9 is connected to ground GND; the common end of the eleventh resistor R11 and the tenth resistor R10 is connected with a slope compensation current I RAMP1 (ii) a The common end of the tenth resistor R10 and the ninth resistor R9 is connected with an inductive current sampling current I CS ；
The source of the sixth PMOS transistor PM6 is connected to the drain of the fifth PMOS transistor PM5, the drain of the sixth PMOS transistor PM6 is connected to one end of an eighth resistor R8, the other end of the eighth resistor R8 is connected to one end of the sixth resistor R6 through a seventh resistor R7, and the other end of the sixth resistor R6 is connected to the ground GND through the fifth resistor R5; the common end of the eighth resistor R8 and the seventh resistor R7 is connected with the grid electrode of a fifteenth PMOS tube PM 15; the common end of the seventh resistor R7 and the sixth resistor R6 is connected with a slope compensation current I RAMP2 ；
The source electrode of the eighth PMOS tube PM8 is connected with the drain electrode of the seventh PMOS tube PM7, the drain electrode of the eighth PMOS tube PM8 is connected with the source electrode of the thirteenth PMOS tube PM13, and the eighth PMOS tube PM8 outputs the modulated overcurrent protection reference voltage V THOC_MOD (ii) a The grid electrode of the thirteenth PMOS pipe PM13 is connected with the drain electrode of the sixth PMOS pipe PM6, and the drain electrode of the thirteenth PMOS pipe PM13 is connected to the ground GND through a third resistor R3;
the source electrode of the tenth PMOS tube PM10 is connected with the drain electrode of the ninth PMOS tube PM9, the drain electrode of the tenth PMOS tube PM10 is connected with the source electrode of the fifteenth PMOS tube PM15, and the tenth PMOS tube PM outputs the modulated light-load peak current control reference voltage V THLLC_MOD (ii) a The drain of the fifteenth PMOS transistor PM15 is connected to the ground GND through a third resistor R2;
the source electrode of the twelfth PMOS tube PM12 is connected with the drain electrode of the eleventh PMOS tube PM11, the drain electrode of the twelfth PMOS tube PM12 is connected with the source electrode of the fourteenth PMOS tube PM14, and the twelfth PMOS tube PM outputs an output addition signal V SUM (ii) a The gate of the fourteenth PMOS transistor PM14 is connected to the drain of the fourth PMOS transistor PM4, and the source thereof is connected to the ground GND through the first resistor R1.
3. The multi-channel PWM comparator applied to the buck DC-DC converter according to claim 1, wherein the multi-channel PWM comparison module comprises 4 PMOS transistors PM1 to PM4,8 NMOS transistors NM1 to NM8 and a bias current source;
the fifth NMOS tube NM5 and the sixth NMOS tube NM6 form a current mirror structure, the sources of the current mirror structure are commonly connected with the ground GND, and the grids of the current mirror structure are connected with the drain of the fifth NMOS tube NM5 and the power supply VCC through the bias current IB 2; the drain electrode of the sixth NMOS tube NM6 provides tail current for the comparison stage;
the source electrodes of the first NMOS tube NM1, the second NMOS tube NM2 and the third NMOS tube NM3 are connected with the drain electrode of the sixth NMOS tube NM6 to form a comparison stage structure; the grid electrode of the first NMOS tube NM1 and an addition signal V SUM The drain electrode of the PMOS tube is connected with the drain electrode of the second PMOS tube PM 2; grid of second NMOS tube NM2 and error amplifier output signal V COMP The drain electrode of the NMOS transistor is connected with the source electrode of a fourth NMOS transistor NM 4; the grid electrode of the third NMOS tube NM3 and the modulated light load peak current control reference voltage V THLLC_MOD The drain electrode of the NMOS transistor is connected with the drain electrode of the second NMOS transistor NM 2;
the grid of the fourth NMOS tube NM4 and the modulated over-current protection reference voltage V THOC_MOD The drain electrode of the PMOS tube is connected with the drain electrode of the third PMOS tube PM 3;
the first PMOS tube PM1 and the second PMOS tube PM2 form a current mirror structure, the source electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected with a power supply voltage VCC, and the grid electrodes of the first PMOS tube PM1 and the second PMOS tube PM2 are connected to the drain electrode of the second PMOS tube PM 2; the drain electrode of the first PMOS pipe PM1 is connected with the drain electrode of the seventh NMOS pipe NM 7;
the seventh NMOS tube NM7 and the eighth NMOS tube NM8 form a current mirror structure, the source electrodes of the seventh NMOS tube NM7 and the eighth NMOS tube NM8 are connected with the ground GND in common, and the grid electrodes of the seventh NMOS tube NM7 and the eighth NMOS tube NM8 are connected with the drain electrode of the seventh NMOS tube NM 7;
the third PMOS tube PM3 and the fourth PMOS tube PM4 form a current mirror structure, the source electrodes of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected with a power supply voltage VCC, and the grid electrodes of the third PMOS tube PM3 and the fourth PMOS tube PM4 are connected to the drain electrode of the third PMOS tube PM 3; the drain electrode of the fourth PMOS tube PM4 is connected with the drain electrode of the first NMOS tube NM8 and outputs an output signal PWM of the multi-path pulse width modulation comparison module.
CN202222228876.4U 2022-08-24 2022-08-24 Multi-path pulse width modulation comparator applied to buck DC-DC converter Active CN218162208U (en)

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