CN218103477U

CN218103477U - Audio device and communication terminal based on FPGA technology

Info

Publication number: CN218103477U
Application number: CN202221927494.4U
Authority: CN
Inventors: 张俊
Original assignee: Fibocom Wireless Inc
Current assignee: Fibocom Wireless Inc
Priority date: 2022-07-20
Filing date: 2022-07-20
Publication date: 2022-12-20
Anticipated expiration: 2032-07-20

Abstract

The application provides an audio device and a communication terminal based on an FPGA technology. The audio device comprises at least two codecs, an FPGA processor and a main processor; each coder-decoder comprises a control signal line and is used for acquiring an analog audio signal and converting the analog audio signal into a digital audio signal; each coder-decoder is respectively connected with an FPGA processor, and the FPGA processor is used for presetting the received digital audio signals; each codec is respectively connected with a main processor through a control signal wire of the codec, the FPGA processor is connected with the main processor, the sampling frequency of the main processor is n times of the sampling frequency of the FPGA processor, n is an integer greater than or equal to 2, and the main processor is used for receiving and storing the digital audio signals after the preset processing. The method and the device allow more audio acquisition paths to be input, and are favorable for improving the sound source acquisition effect.

Description

Audio device and communication terminal based on FPGA technology

Technical Field

The present application relates to the Field of audio acquisition, and in particular, to an audio device and a communication terminal based on an FPGA (Field-Programmable Gate Array) technology.

Background

Generally, the more sound source collecting paths, the more favorable the multipath reflection for reducing the environmental noise, the better the noise reduction effect, and the higher the sound source collecting quality. In the current audio device, the main processor (chip) allows fewer paths of digital audio signals to be input at the same time, for example, only allows maximum 4 paths of data to be input simultaneously, which greatly limits the number of sound source collecting paths and obviously is not beneficial to sound source collection.

SUMMERY OF THE UTILITY MODEL

In view of this, the present application provides an audio device and a communication terminal based on the FPGA technology, which improve the problem that the audio acquisition effect is affected due to fewer audio acquisition paths caused by the limitation of the input signal path.

The audio device based on the FPGA technology comprises at least two codecs, an FPGA processor and a main processor; each coder-decoder comprises a control signal line and is used for collecting analog audio signals and converting the analog audio signals into digital audio signals; each coder-decoder is respectively connected with an FPGA processor, and the FPGA processor is used for presetting the received digital audio signals; each codec is connected with a main processor through a control signal line of the codec, the FPGA processor is connected with the main processor, the sampling frequency of the main processor is n times of the sampling frequency of the FPGA processor, n is an integer greater than or equal to 2, and the main processor is used for receiving and storing the digital audio signals after the preset processing.

Optionally, the FPGA processor is provided with a PCM interface, and the FPGA processor is connected to each codec and the main processor through the corresponding PCM interfaces.

Optionally, the control signal line of the codec is a serial communication bus.

Optionally, the at least two codecs include a first codec and a second codec, the first codec being connected with the main processor, the second codec being a codec other than the first codec, the second codec being connected with the serial communication bus of the first codec to be connected with the main processor.

Alternatively, the serial communication bus of each codec is directly connected to the main processor.

Optionally, the sampling frequency of the main processor is 2 times the sampling frequency of the FPGA processor. For example, the sampling frequency of the main processor is 96kHz and the sampling frequency of the FPGA processor is 48kHz.

Optionally, four serial communication buses are provided between the FPGA processor and the main processor, and two serial communication buses are provided between the FPGA processor and a single codec.

Optionally, the main processor includes a data reorganization unit, and the data reorganization unit is connected to the FPGA processor and is configured to reorganize the digital audio signal after the preset processing into a preset format.

The application provides a communication terminal, which comprises the audio device.

As described above, the audio device of the present application includes at least two codecs, an FPGA processor, and a main processor, where a sampling frequency of the main processor is even times of a sampling frequency of the FPGA processor, and the main processor allows the FPGA processor to input digital audio signals of even paths at the same time, a sampling output of the FPGA processor is high, and can receive audio signals acquired by more codecs, and the number of codecs is increased to increase audio acquisition paths, thereby facilitating improvement of an audio source acquisition effect.

Drawings

Fig. 1 is a schematic structural diagram of an audio device according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of another audio device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of another audio device according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described below in detail with reference to specific embodiments and accompanying drawings. It should be apparent that the embodiments described below are only some embodiments of the present application, and not all embodiments. In the following embodiments and technical features thereof, all of which are described below may be combined with each other without conflict, and also belong to the technical solutions of the present application.

It should be understood that in the description of the embodiments of the present application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only used for convenience of describing technical solutions and simplifying the description of the respective embodiments of the present application, but do not indicate or imply that a device or an element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.

Referring to fig. 1, an audio device 1 according to an embodiment of the present disclosure includes at least two codecs 10, an FPGA processor 20, and a main processor 30.

Each codec 10 is configured to collect an analog audio signal and perform analog-to-digital conversion on the collected analog audio signal to obtain a digital audio signal. In some scenarios, the audio apparatus 1 may be provided with several audio pickup units, e.g. a microphone array, which capture analog audio signals, each codec 10 being connected to a corresponding one of the audio pickup units and obtaining analog audio signals from the connected audio pickup units. Optionally, the Codec 10 is a Codec (Coder-Decoder, a Codec supporting video and audio Compression (CO) and Decompression (DEC)), and the Codec can reduce CPU resources occupied by digital-to-analog signal registration and analog-to-digital conversion, which is beneficial to improving the overall operating efficiency of the audio apparatus 1. In other scenarios, codec 10 may be self-contained with an audio pick-up unit.

The number of codecs 10 included in the audio device 1 is not limited in the present application, and may be set according to the actual required adaptation, and fig. 1 and 2 are only shown for exemplary purposes.

Triggering each codec 10 to perform acquisition of an analog audio signal is achieved by a control signal issued by the main processor 30. The main processor 30 may be connected to each structural element including each codec 10 through, for example, various wirings as a core control unit of the audio device 1, and transmit and receive corresponding control instructions to and data from each structural element.

For example, in one scenario, the codecs 10 and the host processor 30 are connected via a serial communication bus (IIC), as shown in fig. 1, a first control signal line (i.e., a clock line SCL) and a second control signal line (i.e., a bidirectional data line SDA) are respectively provided, the first control signal line SCL is used to control the time when the host processor 30 and the codecs 10 transmit data (e.g., control commands), the second control signal line SDA is used for the host processor 30 to transmit control commands to the codecs 10, and the codecs 10 transmit relevant data, e.g., feedback information about the control commands, to the host processor 30.

Referring to fig. 1, the serial communication bus of each codec 10 may be directly connected to the main processor 30, and the main processor 30 may be provided with a number of control units equal to the number of codecs 10, so as to individually control each codec 10.

Alternatively, as shown in fig. 2, only one codec 10 has its serial communication bus directly connected to the main processor 30, the codec 10 is referred to as a first codec 10, the codecs 10 other than the first codec are referred to as a second codec 10, and the second codec 10 is connected to the serial communication bus of the first codec 10 to be connected to the main processor.

Still alternatively, the audio apparatus 1 comprises a plurality of first codecs 10, for example, referring to fig. 3, the audio apparatus 1 comprises 2 first codecs 10.

In the embodiments of fig. 2 and 3, the second codec 10 and the first codec 10 may share a control unit, reducing the number of setting interfaces of the main processor 30 and the control unit.

Each codec 10 is connected to an FPGA processor 20, and the FPGA processor 20 is configured to perform preset processing on the received digital audio signal. The preset treatment includes but is not limited to at least one of the following: digital Signal Processing (DSP), such as noise cancellation, echo suppression, high and low frequency filtering; and (5) frequency division processing. The crossover process may be regarded as adjusting the frequency of the digital audio signal output to the main processor 30 to be adapted to the sampling frequency of the main processor 30, thereby ensuring real-time performance of the multi-path signal output to the main processor 30, for example, the FPGA processor 20 raises (i.e., up-converts) the frequency of the received audio signal to be the same as the sampling frequency of the main processor 30. It should be understood that the order of these processes and their respective functions can be referred to in the art and are not described in detail herein.

The FPGA processor 20 is connected to the main processor 30, and the main processor 30 receives the digital audio signal after the preset processing from the FPGA processor 20 and stores the digital audio signal, so as to realize sound source collection.

The sampling frequency of the main processor 30 is n times of the sampling frequency of the FPGA processor 20, and n is an integer greater than or equal to 2, here, at the same time, the main processor 30 allows the FPGA processor 20 to input digital audio signals of n times of paths, the sampling output of the FPGA processor 20 is higher, and more audio signals collected by the codec 10 can be received, and the number of audio collecting paths is increased, thereby being beneficial to improving the sound source collecting effect.

Taking the main processor 30 as an MSM8953 chip as an example, the sampling frequency of the main processor 30 is 2 times of the sampling frequency of the FPGA processor 20. For example, in some scenarios, the MSM8953 chip has a sampling frequency of 96kHz, and correspondingly, the FPGA processor 20 has a sampling frequency of 48kHz. At the same time, the sampling output of the FPGA processor 20 may be doubled, i.e., the path of the FPGA processor 20 transmitting the digital audio signal to the main processor 30 is doubled.

For the scenario in which the FPGA processor 20 and the main processor 30 are connected through 4 bidirectional signal traces (e.g., data-0, data-1, data-2, and data-3 shown in fig. 1), since each bidirectional signal trace can perform bidirectional data transmission, the path between the FPGA processor 20 and the main processor 30 is doubled, and then there can be (4 × 2= 16) data transmission. This indicates that the FPGA processor 20 can receive a maximum of 16 data inputs at the same time. Of course, if there are no 16 data inputs at the same time, the byte section of the input data packet may be complemented by 0, for example, the data packet includes 16 byte sections, the currently input only 12 data correspondingly occupy 12 byte sections in sequence, and the remaining 4 byte sections are complemented by 0. If a single codec 10 is connected to the FPGA processor 20 through 2 bidirectional signal traces (e.g., data-0 and data-1 shown in fig. 1), there are 4 data transmission paths between the single codec 10 and the FPGA processor 20, and the FPGA processor 20 can access at most 4 digital audio signals input by the codec 10 at the same time.

It should be noted that, instead of only setting the codec 10 with the maximum number of accesses at the same time, for example, only setting the 4 codec 10, the audio apparatus 1 may set a number of codec 10 that is more than that. In an actual usage scenario, some of the codecs 10 may be selected according to actual requirements.

In addition, a clock line (e.g., a serial clock line bclk) and a channel control signal line Ws may be further disposed between each codec 10 and the FPGA processor 20, and between the FPGA processor 20 and the main processor 30, the clock line controlling a time when the codec 10 and the FPGA processor 20 transmit data, the channel control signal line Ws controlling switching of left channel data and right channel data.

In some scenarios, the FPGA processor 20 is provided with a PCM (Pulse Code Modulation) interface, and the FPGA processor 20 and each codec 10 and the main processor 30 are connected through corresponding PCM interfaces respectively, so that the transmission expansion requirements between the FPGA processor 20 and each codec 10 and the main processor 30 can be met.

With reference to fig. 1, optionally, the main processor 30 may further include a data reorganizing unit 31, the data reorganizing unit 31 is connected to the FPGA processor 20, and after the main processor 30 receives the digital audio signal from the FPGA processor 20, the data reorganizing unit 31 reorganizes the digital audio signal into a preset format. For example, by recombining the digital audio signal into the Wav format, the sound quality is clear and lossless.

It should be understood that the encoding and decoding of the audio signal, and the unpacking and the packing of the data packet in the transmission process can refer to the prior art, and the improvement point of the embodiment of the present application is not described herein, and therefore, the description is not repeated. In addition, the connection in the whole text of the application can be direct connection or indirect connection, and only the corresponding connection requirements are needed to be realized; similarly, "transmitting" may be direct transmission or indirect transmission.

The embodiment of the present application further provides a communication terminal, which includes the audio apparatus 1 according to any of the above embodiments, and therefore can produce the beneficial effects of the audio apparatus 1 according to the corresponding embodiment.

The communication terminal may be embodied in various specific forms. For example, the communication terminal described in the present application may include mobile terminals such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and fixed terminals such as a Digital TV, a broadcast, a desktop computer, and the like.

The above description is only a part of the embodiments of the present application, and not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the present specification and the drawings will be included in the protection scope of the present application for a person skilled in the art.

Although the terms "first, second, etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. In addition, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive or meaning any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.

Claims

1. An audio apparatus based on FPGA technology, comprising:

each codec comprises a control signal line and is used for acquiring an analog audio signal and converting the analog audio signal into a digital audio signal;

the FPGA processor is used for presetting the received digital audio signals;

the main processor is connected with the FPGA processor, the sampling frequency of the main processor is n times of the sampling frequency of the FPGA processor, n is an integer greater than or equal to 2, and the main processor is used for receiving and storing the digital audio signals after the preset processing.

2. The audio device according to claim 1, wherein the FPGA processor is provided with a PCM interface, and the connection between the FPGA processor and each codec and the connection between the FPGA processor and the main processor are respectively through the corresponding PCM interfaces.

3. The audio device of claim 1, wherein the control signal line comprises a serial communication bus.

4. The audio device of claim 3, wherein the at least two codecs comprise a first codec and a second codec, the first codec being coupled to the host processor, and the second codec being coupled to a serial communication bus of the first codec for coupling to the host processor.

5. The audio device according to claim 3, wherein the serial communication bus of each of the codecs is directly connected to the main processor.

6. The audio device according to any one of claims 1 to 5, wherein the sampling frequency of the main processor is 2 times the sampling frequency of the FPGA processor.

7. The audio device according to claim 6, wherein four bidirectional signal traces are disposed between the FPGA processor and the main processor, and two bidirectional signal traces are disposed between the FPGA processor and a single codec.

8. The audio device of claim 6, wherein the sampling frequency of the main processor is 96kHz and the sampling frequency of the FPGA processor is 48kHz.

9. The audio device according to claim 1, wherein the main processor comprises a data reorganizing unit, and the data reorganizing unit is connected to the FPGA processor and is configured to reorganize the digital audio signal after the preset processing into a preset format.

10. A communication terminal, characterized in that it comprises an audio device based on FPGA technology according to any one of claims 1 to 9.