CN218038540U - GOA drive circuit of narrow frame - Google Patents
GOA drive circuit of narrow frame Download PDFInfo
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- CN218038540U CN218038540U CN202221974378.8U CN202221974378U CN218038540U CN 218038540 U CN218038540 U CN 218038540U CN 202221974378 U CN202221974378 U CN 202221974378U CN 218038540 U CN218038540 U CN 218038540U
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Abstract
The utility model provides a GOA drive circuit of narrow frame, include: the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7 and the capacitor C1; the grid electrode of the transistor T1 is connected with the first GOA control signal end, the drain electrode of the transistor T1 is connected with the first GOA input signal end, and the source electrode of the transistor T1 is connected with the node Q; the grid electrode of the transistor T2 is connected with the node Q, the drain electrode of the transistor T2 is connected with the node P, and the source electrode of the transistor T2 is connected with the second GOA input signal end; the grid electrode of the transistor T3 is connected with the node P, the drain electrode of the transistor T3 is connected with the node Q, and the source electrode of the transistor T3 is connected with the second GOA input signal end; the gate of the transistor T4 is connected to the node Q, the drain is connected to the third GOA input signal terminal, and the source is connected to the GOA output signal terminal. The utility model has the advantages that: the GOA driving circuit limits the number of the transistors to seven, and is used for driving a row of pixel units of the display panel, so that the design space of a frame can be reduced, and a narrow frame of the display panel is realized; the narrow-frame visual effect of the display panel is improved.
Description
Technical Field
The utility model relates to a display panel technical field specifically relates to a GOA drive circuit of narrow frame.
Background
The GOA (Gate-driver on Array) technology is to integrate a Gate driving circuit directly on an Array substrate of a display device through a photolithography process. In the GOA circuit, a plurality of GOA unit circuits are cascaded, and the output signal of the GOA unit in the previous stage can participate in the operation of the GOA unit circuit in the next stage, besides being transmitted to the display area as the gate driving signal of the pixel unit in the corresponding row.
With the increasing development of technology, the requirements of narrow frame and high screen ratio of display panel are required to optimize the visual effect of users, and the requirement of reliability is becoming more and more strict, so the requirements for stability of the GOA driving circuit are relatively increased, including noise immunity, output stability, temperature and electrical drift tolerance, and so on.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model lies in providing a GOA drive circuit of narrow frame promotes display panel's narrow frame visual effect.
The utility model discloses a realize like this: a GOA driving circuit with narrow frame comprises:
the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7 and the capacitor C1;
the grid electrode of the transistor T1 is connected with a first GOA control signal end, the drain electrode of the transistor T1 is connected with a first GOA input signal end, and the source electrode of the transistor T1 is connected with a node Q;
the grid electrode of the transistor T2 is connected with the node Q, the drain electrode of the transistor T2 is connected with the node P, and the source electrode of the transistor T2 is connected with the second GOA input signal end;
the grid electrode of the transistor T3 is connected with the node P, the drain electrode of the transistor T3 is connected with the node Q, and the source electrode of the transistor T3 is connected with the second GOA input signal end;
the grid electrode of the transistor T4 is connected with the node Q, the drain electrode of the transistor T4 is connected with the third GOA input signal end, and the source electrode of the transistor T4 is connected with the GOA output signal end;
the grid electrode of the transistor T5 is connected with the node P, the drain electrode of the transistor T5 is connected with the GOA output signal end, and the source electrode of the transistor T5 is connected with the second GOA input signal end;
the grid electrode and the drain electrode of the transistor T6 are both connected with the third GOA input signal end, and the source electrode is connected with the node P;
the grid electrode of the transistor T7 is connected with the second GOA control signal end, the drain electrode of the transistor T7 is connected with the fourth GOA input signal end, and the source electrode of the transistor T7 is connected with the node Q;
and one end of the capacitor C1 is connected with the node Q, and the other end of the capacitor C1 is connected with the GOA output signal end.
Furthermore, the first GOA input signal terminal is connected to the FW voltage signal, the second GOA input signal terminal is connected to the VGL voltage signal, the third GOA input signal terminal is connected to the CK clock signal, and the fourth GOA input signal terminal is connected to the BW voltage signal.
Further, the CK clock signal is a square wave signal.
Further, the GOA output signal terminal is for generating the output signal Gn of the nth stage, the first GOA control signal terminal is for connecting the output signal Gn-2 of the nth-2 stage, and the second GOA control signal terminal is for connecting the output signal Gn +2 of the (n + 2) th stage.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, and the transistor T7 are all TFT thin film transistors.
Further, the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the capacitor C1 are all fixedly disposed in a device region, and the device region is located on a frame of the LCD display panel.
Furthermore, the FW voltage signal, the VGL voltage signal, the CK clock signal, and the BW voltage signal are routed in a line area, and the line area is located in a frame of the LCD display panel.
The utility model has the advantages that: the GOA driving circuit limits the number of the transistors to seven, and is used for driving a row of pixel units of the display panel, so that the design space of a frame can be reduced, and a narrow frame of the display panel is realized; when the single-stage circuit does not generate the output signal Gn, the residual potential of the node Q can be continuously pulled down to a low potential, so that the situation that the transistor T4 is influenced by noise to turn on and cause repeated output of a GOA output signal end is prevented, and the reliability capability of the circuit can be relatively improved.
Drawings
The invention will be further described with reference to the following examples with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a 7T1C driving circuit in an embodiment of the present invention.
Fig. 2 is a circuit simulation waveform diagram of node Q, node P and output signal Gn of the 7T1C driving circuit in the embodiment of the present invention.
Fig. 3 is a schematic diagram of a position of the frame on the display panel according to the embodiment of the present invention.
Fig. 4 is a schematic diagram of positions of the device region and the circuit region on the frame according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a 9T1C driving circuit in an embodiment of the present invention.
Fig. 6 is a circuit simulation waveform diagram of node Q, node P and output signal Gn of the 9T1C driving circuit in the embodiment of the present invention.
Detailed Description
The embodiment of the utility model provides a through the GOA drive circuit who provides a narrow frame, solved the demand of the narrow frame of display panel among the prior art, realized promoting display panel's narrow frame visual effect and the technological effect of the dependability ability of promotion circuit.
The embodiment of the utility model provides an in technical scheme for solving above-mentioned shortcoming, the general thinking is as follows: the GOA driving circuit is formed by seven transistors and a capacitor, namely 7T1C, output signals are used for driving a row of pixel units of the display panel, the output signals of the GOA driving circuit at the upper stage also participate in the work of the GOA driving circuit at the lower stage, the GOA driving circuit is arranged on the frame of the display panel, and the wiring of CK clock signals is used, so that the wiring of CKB clock signals is not needed, the design space of the frame can be reduced, and the narrow frame of the display panel is realized; when the output signal Gn of the stage circuit is not generated, the residual potential of the node Q can be continuously pulled down to a low potential, so that the repeated output of the GOA output signal end caused by the starting of the transistor T4 influenced by noise is prevented, and the reliability capability of the circuit can be relatively improved.
For better understanding of the above technical solutions, the following detailed descriptions will be provided in conjunction with the drawings and the detailed description of the embodiments.
Referring to fig. 1 to 6, a preferred embodiment of the present invention.
A GOA driving circuit with narrow frame comprises:
the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7 and the capacitor C1; namely 7T 1C.
The grid electrode of the transistor T1 is connected with a first GOA control signal end, the drain electrode of the transistor T1 is connected with a first GOA input signal end, and the source electrode of the transistor T1 is connected with a node Q;
the grid electrode of the transistor T2 is connected with the node Q, the drain electrode of the transistor T2 is connected with the node P, and the source electrode of the transistor T2 is connected with the second GOA input signal end;
the grid electrode of the transistor T3 is connected with the node P, the drain electrode of the transistor T3 is connected with the node Q, and the source electrode of the transistor T3 is connected with the second GOA input signal end;
the grid electrode of the transistor T4 is connected with the node Q, the drain electrode of the transistor T4 is connected with the third GOA input signal end, and the source electrode of the transistor T4 is connected with the GOA output signal end;
the grid electrode of the transistor T5 is connected with the node P, the drain electrode of the transistor T5 is connected with the GOA output signal end, and the source electrode of the transistor T5 is connected with the second GOA input signal end;
the grid electrode and the drain electrode of the transistor T6 are both connected with the third GOA input signal end, and the source electrode is connected with the node P;
the grid electrode of the transistor T7 is connected with the second GOA control signal end, the drain electrode of the transistor T7 is connected with the fourth GOA input signal end, and the source electrode of the transistor T7 is connected with the node Q;
and one end of the capacitor C1 is connected with the node Q, and the other end of the capacitor C1 is connected with the GOA output signal end.
The first GOA input signal terminal is connected with FW voltage signals, the second GOA input signal terminal is connected with VGL voltage signals, the third GOA input signal terminal is connected with CK clock signals, and the fourth GOA input signal terminal is connected with BW voltage signals. In the present embodiment, FW is a high level, BW is a low level, and VGL is a low level; the CK clock signal is a square wave signal.
The GOA output signal terminal is used for generating an output signal Gn of the nth stage, the first GOA control signal terminal is used for connecting an output signal Gn-2 of the (n-2) th stage, and the second GOA control signal terminal is used for connecting an output signal Gn +2 of the (n + 2) th stage. The output signal of the previous-stage GOA driving circuit is used for driving a row of pixel units of the display panel, and also participates in the operation of the next-stage GOA driving circuit.
The transistors T1, T2, T3, T4, T5, T6 and T7 are all TFT thin film transistors. The TFT thin film transistor refers to the conduction principle of the N-type MOS transistor.
The transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9, and the capacitor C1 are all fixedly disposed in a device region 101, and the device region 101 is located on a frame 10 of the LCD display panel. The frame is located at the side of the display area 20.
The FW voltage signal, VGL voltage signal, CK clock signal, BW voltage signal are routed in the line area 102, and the line area 102 is located in the frame 10 of the LCD display panel. The line region 102 is located outside the device region 101. The circuit area 102 further has STV voltage signal traces, which are used as the start signals of the first and second levels of GOA and are connected to the first GOA control signal terminals of the first and second levels of GOA driving circuits.
The GOA driving circuit limits the number of the transistors to seven, is used for driving a row of pixel units of the display panel, can reduce the design space of a frame, and realizes a narrow frame of the display panel; fig. 2 is a circuit simulation waveform diagram of the node Q, the node P and the output signal Gn of the 7T1C driving circuit, and in combination with fig. 2, when the output signal Gn is not generated in the stage circuit, the CK clock signal periodically charges the node P through the transistor T6, pulls up the node P to a high level, makes the gate of the transistor T3 to a high level, turns on the transistor T3, and discharges the node Q through the transistor T3, thereby continuously pulling down the residual potential of the node Q to a low level, preventing the transistor T4 affected by noise from being turned on to cause repeated output of the GOA output signal terminal, and relatively improving the reliability of the circuit.
In this embodiment, another narrow-frame GOA driving circuit includes the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the capacitor C1, and the connection relationship; the circuit also comprises a transistor T8 and a transistor T9; namely a 9T1C GOA driver circuit.
The grid electrode of the transistor T8 is connected with the fifth GOA input signal end, the drain electrode of the transistor T8 is connected with the GOA output signal end, and the source electrode of the transistor T8 is connected with the second GOA input signal end;
and the gate of the transistor T9 is connected to the fifth GOA input signal terminal, the drain is connected to the node P, and the source is connected to the second GOA input signal terminal.
The second GOA input signal end is connected with a VGL voltage signal, and the fifth GOA input signal end is connected with a CKB clock signal; the CKB clock signal and the CK clock signal are shown in FIG. 6.
Fig. 6 is a circuit simulation waveform diagram of node Q, node P and output signal Gn of the 9T1C driving circuit in the embodiment of the present invention, and with reference to fig. 6 and fig. 2, the transistor T8 and the transistor T9 of the 9T1C circuit controlled by the CKB clock signal are removed through circuit simulation evaluation, and from the simulation result, the node P, the node Q and the output signal Gn hardly affect during output.
As can be seen from comparison, the 7T1C GOA driving circuit has fewer transistors in the device region, and eliminates the routing of the CKB clock signal in the line region, thereby saving the design space of the frame, making the frame of the display panel narrower, and improving the visual effect of the user and the product reliability.
Although specific embodiments of the invention have been described herein, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, as equivalent modifications and variations within the spirit of the invention are intended to be covered by the appended claims.
Claims (7)
1. A GOA driving circuit with a narrow frame is characterized by comprising:
the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7 and the capacitor C1;
the grid electrode of the transistor T1 is connected with a first GOA control signal end, the drain electrode of the transistor T1 is connected with a first GOA input signal end, and the source electrode of the transistor T1 is connected with a node Q;
the grid electrode of the transistor T2 is connected with the node Q, the drain electrode of the transistor T2 is connected with the node P, and the source electrode of the transistor T2 is connected with the second GOA input signal end;
the grid electrode of the transistor T3 is connected with the node P, the drain electrode of the transistor T3 is connected with the node Q, and the source electrode of the transistor T3 is connected with the second GOA input signal end;
the grid electrode of the transistor T4 is connected with the node Q, the drain electrode of the transistor T4 is connected with the third GOA input signal end, and the source electrode of the transistor T4 is connected with the GOA output signal end;
the grid electrode of the transistor T5 is connected with the node P, the drain electrode of the transistor T5 is connected with the GOA output signal end, and the source electrode of the transistor T5 is connected with the second GOA input signal end;
the grid electrode and the drain electrode of the transistor T6 are both connected with the third GOA input signal end, and the source electrode is connected with the node P;
the grid electrode of the transistor T7 is connected with the second GOA control signal end, the drain electrode of the transistor T7 is connected with the fourth GOA input signal end, and the source electrode of the transistor T7 is connected with the node Q;
and one end of the capacitor C1 is connected with the node Q, and the other end of the capacitor C1 is connected with the GOA output signal end.
2. The GOA driving circuit with narrow frame of claim 1, wherein the first GOA input signal terminal is connected to FW voltage signal, the second GOA input signal terminal is connected to VGL voltage signal, the third GOA input signal terminal is connected to CK clock signal, and the fourth GOA input signal terminal is connected to BW voltage signal.
3. The GOA driving circuit with narrow frame as claimed in claim 2, wherein the CK clock signal is a square wave signal.
4. The GOA driving circuit with narrow frame of claim 1, wherein the GOA output signal terminal is for generating an output signal Gn of an nth stage, the first GOA control signal terminal is for connecting an output signal Gn-2 of an nth-2 stage, and the second GOA control signal terminal is for connecting an output signal Gn +2 of an n +2 th stage.
5. The GOA driving circuit with a narrow bezel as claimed in claim 1, wherein the transistors T1, T2, T3, T4, T5, T6 and T7 are all TFT thin film transistors.
6. The GOA driving circuit with a narrow bezel as claimed in claim 2, wherein the transistor T1, the transistor T2, the transistor T3, the transistor T4, the transistor T5, the transistor T6, the transistor T7, the transistor T8, the transistor T9 and the capacitor C1 are all fixedly disposed in a device region, and the device region is located in a bezel of an LCD display panel.
7. The GOA driving circuit with narrow bezel of claim 6, wherein the trace of FW voltage signal, VGL voltage signal, CK clock signal, BW voltage signal is located in the line area, and the line area is located in the bezel of the LCD display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221974378.8U CN218038540U (en) | 2022-07-29 | 2022-07-29 | GOA drive circuit of narrow frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221974378.8U CN218038540U (en) | 2022-07-29 | 2022-07-29 | GOA drive circuit of narrow frame |
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| Publication Number | Publication Date |
|---|---|
| CN218038540U true CN218038540U (en) | 2022-12-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221974378.8U Active CN218038540U (en) | 2022-07-29 | 2022-07-29 | GOA drive circuit of narrow frame |
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| CN (1) | CN218038540U (en) |
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- 2022-07-29 CN CN202221974378.8U patent/CN218038540U/en active Active
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