CN217985086U

CN217985086U - Clock synchronization device and power terminal

Info

Publication number: CN217985086U
Application number: CN202221114335.2U
Authority: CN
Inventors: 武新旗
Original assignee: Shenzhen Clou Electronics Co Ltd
Current assignee: Shenzhen Clou Electronics Co Ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2022-12-06
Anticipated expiration: 2032-05-10

Abstract

The utility model discloses a clock synchronization device and an electric power terminal, which comprises a first circuit and a second circuit, wherein the clock synchronization device also comprises an analog switch circuit and a clock circuit; the first circuit is connected with the second circuit through a bus, and the first circuit, the second circuit and the clock circuit are respectively and independently connected with the analog switch circuit. After the clock synchronization device is started, the clock circuit generates a clock, the first circuit firstly obtains the clock from the clock circuit through the analog switch, the second circuit then switches a clock transmission channel of the analog switch circuit, and obtains the clock from the clock circuit, so that the clocks of the first circuit and the second circuit are kept synchronous.

Description

Clock synchronization device and power terminal

Technical Field

The utility model relates to a clock synchronization technical field especially relates to a clock synchronizer and power terminal.

Background

The power terminal is used for collecting data of an electric energy meter on an electricity utilization control site and controlling and managing an electricity load, generally comprises at least a power panel circuit and a core panel circuit, and a clock of the power panel circuit during working needs to be consistent with a clock of the core panel circuit during working so as to ensure the uniformity of the running time of the power terminal.

The first technical solution in the prior art is that after the power terminal is powered on, the power board circuit and the core board circuit are calibrated respectively through different interfaces by using an external clock, so that the effect of keeping clocks of the power board circuit and the core board circuit synchronous is achieved.

The second technical scheme is that after the power terminal is powered on, the power panel circuit is started first, the core panel circuit is started later, and the power panel circuit started first synchronizes the clock of the power panel circuit to the core panel circuit through the bus.

The inventor finds that in the first technical scheme, because the power panel circuit and the core panel circuit are connected with the external clock chip at the same time, the problem of current flowing backwards can occur, so that the power panel circuit is started firstly and then the core panel circuit cannot be started. Meanwhile, the inventor finds that in the second technical scheme, because the power board circuit is started before the core board circuit, before the clock synchronization process of the power board circuit and the core board circuit is completed, target data generated by the power board circuit is at risk of being lost.

SUMMERY OF THE UTILITY MODEL

An embodiment of the utility model provides a clock synchronizer to solve the problem that current counter-flow and data lost among the prior art scheme.

The embodiment of the utility model provides a clock synchronization device, which comprises a first circuit and a second circuit, and also comprises an analog switch circuit and a clock circuit connected with the analog switch circuit;

the first circuit is connected with the second circuit through a bus, and the first circuit and the second circuit are respectively connected with the analog switch circuit.

Further, the analog switch circuit comprises a first channel corresponding to the first circuit, a second channel corresponding to the second circuit and a first chip for controlling the communication of the first channel or the second channel.

Further, the clock circuit includes a clock chip for generating a clock.

Further, a first pin and a second pin of the first chip are connected with the first circuit, and the first circuit receives the clock through the first pin and the second pin.

Further, a third pin and a fourth pin of the first chip are connected to the second circuit, and the second circuit receives the clock through the third pin and the fourth pin.

Further, a fifth pin and a sixth pin of the first chip are connected to the second circuit, and the second circuit sends an instruction for switching a transmission clock channel to the first chip through the fifth pin and the sixth pin.

Furthermore, a seventh pin and an eighth pin of the first chip are connected to the clock chip, and the first chip receives the clock sent by the clock chip through the seventh pin and the eighth pin.

Furthermore, the clock circuit also comprises a clock battery, a voltage stabilizing chip and a diode; the positive pole of the clock battery is connected with the positive pole of the diode, the negative pole of the diode is connected with the input port of the voltage stabilizing chip, and the output port of the voltage stabilizing chip is connected with the power pin of the clock chip.

Further, the first circuit further comprises a memory chip, the memory chip is connected with the second circuit through the bus, and the memory chip is used for storing target data generated by the first circuit and sending the target data to the second circuit.

The utility model discloses a another technical scheme as follows: a power terminal is provided, which comprises the clock synchronization device.

The utility model discloses in, after the clock synchronizer started, clock circuit produced the clock, first circuit passed through analog switch follows clock circuit acquires the clock, the second circuit switches again analog switch circuit's clock transmission passageway follows clock circuit acquires the clock, makes first circuit with the clock of second circuit keeps the synchronization. In addition, the first circuit stores the generated target data in the memory chip, and after the clock synchronization process is finished, the first circuit sends the target data to the second circuit through the bus, so that the problem of current backflow in the circuit is avoided, and the risk of target data loss is eliminated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive labor.

Fig. 1 is a schematic structural diagram of a clock synchronization apparatus according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of an analog switch circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a clock circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another embodiment of an analog switch circuit according to the present invention;

fig. 5 is another schematic diagram of the clock circuit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The terms "first", "second" and "third" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. In the embodiments of the present invention, all directional indicators (such as up, down, left, right, front, rear \8230;) are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In one embodiment, as shown in fig. 1, a clock synchronization apparatus 100 is provided, where the clock synchronization apparatus 100 includes a first circuit 10 and a second circuit 11, and further includes an analog switch circuit 12 and a clock circuit 13 connected to the analog switch circuit 12; the first circuit 10 is connected to the second circuit 11 through a bus, and the first circuit 10 and the second circuit 11 are connected to the analog switch circuit 12, respectively. After the clock synchronization apparatus 100 is started, the clock circuit 13 generates a clock, and the first circuit 10 obtains the clock from the clock circuit 13 through the analog switch circuit 12 after being started. After the second circuit 11 is started, the analog switch circuit 12 is controlled, the clock is obtained from the clock circuit 13 through the analog switch circuit 12, the second circuit 11 obtains the same clock as the first circuit 10, and the effect of clock synchronization is achieved. Finally, the first circuit 10 and the second circuit 11 synchronize data generated before the clock synchronization process is finished through the bus, so that the risk of data loss is avoided while the clock synchronization effect is achieved, and the clock synchronization device 100 does not have the problem of current back-flow.

Specifically, referring to fig. 2, the analog switch circuit 12 includes a first channel corresponding to the first circuit 10, a second channel corresponding to the second circuit 11, and a first chip 120 controlling communication between the first channel and the second channel. The second circuit 11 controls the conduction of the first channel and the second channel through the control pin of the first chip 120, for example, when the clock synchronization apparatus 100 is started, the analog switch circuit 12 defaults that the first channel is on and the second channel is off, after the first circuit 10 obtains the clock from the clock circuit 13 through the analog switch circuit 12, the second circuit 11 controls the first chip 120 to turn off the first channel and turn on the second channel, and at this time, the second circuit 11 completes the channel switching process of the analog switch circuit 12 and can obtain the clock from the clock circuit 13.

In an alternative embodiment, referring to fig. 2, a first pin 1201 and a second pin 1202 of the first chip 120 are connected to the first circuit 10, and the first circuit 10 receives the clock through the first pin 1201 and the second pin 1202. A third pin 1203 and a fourth pin 1204 of the first chip 120 are connected to the second circuit 11, and the second circuit 11 receives the clock through the third pin 1203 and the fourth pin 1204. The fifth pin 1205 and the sixth pin 1206 of the first chip 120 are connected to the second circuit 11, and the second circuit 11 sends an instruction for switching a transmission clock channel to the first chip through the fifth pin 1205 and the sixth pin 1206. The seventh pin 1207 and the eighth pin 1208 of the first chip 120 are connected to the clock chip 134, and the clock transmitted by the clock chip 134 is received by the first chip 120 through the seventh pin 1207 and the eighth pin 1208. The first pin 1201 and the second pin 1202 form the first channel, the third pin 1203 and the fourth pin 1204 form the second channel, and the fifth pin 1205 and the sixth pin 1206 form a control port for the first chip 120 to control switching of the first channel and the second channel.

In an alternative embodiment, referring to fig. 3, the clock circuit 13 includes a clock chip 134, and the clock chip 134 is used for generating a clock. The clock circuit 13 further comprises a clock battery 131, a voltage stabilizing chip 133 and a diode 132; the anode of the clock battery 131 is connected to the anode of the diode 132, the cathode of the diode 132 is connected to the input port of the voltage regulator chip 133, and the output port of the voltage regulator chip 133 is connected to the power pin of the clock chip 134. The clock battery 131 is used for supplying power to the clock chip 134, the diode 132 reduces the voltage provided by the clock battery 131 to reach the standard working voltage of the clock chip 134, and the voltage stabilizing chip 133 provides voltage stabilizing protection for the clock chip 134, so that the clock chip 134 has a more stable working voltage.

IN a specific embodiment, please refer to fig. 4, the first chip 120 is a differential 4-CHANNEL digital control chip with a model of CD4052BM, the fifth pin 1205 and the sixth pin 1206 correspond to the a pin and the B pin of the CD4052BM chip, respectively, the first pin 1201 and the second pin 1202 correspond to the X CHANNEL IN/OUT 0 and the Y CHANNEL IN/OUT 0 of the CD4052BM chip, respectively, the third pin 1203 and the fourth pin 1204 correspond to the X CHANNEL IN/OUT 1 and the Y CHANNEL IN/OUT 1 of the CD4052BM chip, and the seventh pin 1207 and the eighth pin 1208 correspond to the COMMON "X" OUT/IN and the COMMON pin "Y" OUT/IN of the CD4052BM chip, respectively.

In a specific embodiment, referring to fig. 5, a clock battery 131 in the clock circuit 13 corresponds to a BT1M clock battery, basic parameters of the BT1M clock battery are 3.6V and 1200mAh, the diode 132 is specifically a diode of model 4148CC, the voltage stabilization chip 133 is specifically a voltage stabilization chip of model 1206B33, the clock chip 134 is specifically a RX8025T clock chip, and a high-precision 32.768K crystal oscillator is built in the RX8025T clock chip and has a temperature compensation function.

In an optional embodiment, the first circuit 10 further includes a memory chip, the memory chip is connected to the second circuit 11 through the bus, and the memory chip is configured to store target data generated by the first circuit 10 and send the target data to the second circuit 11. The first circuit 10 stores the target data before the clock synchronization process is finished in the memory chip, and the first circuit 10 sends the target data to the second circuit 11 for data synchronization after the clock synchronization process is finished, so that the risk of data loss before the clock synchronization is finished is avoided.

The embodiment of the utility model provides a still provide an electric power terminal, including foretell clock synchronizer.

The power Terminal of the embodiment includes, but is not limited to, a DTU (Distribution Terminal Unit), an FTU (Feeder Terminal Unit), an RTU (Remote Terminal Unit), and a TTU (Transformer Terminal Unit).

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.

The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A clock synchronization device comprises a first circuit and a second circuit, and is characterized by further comprising an analog switch circuit and a clock circuit connected with the analog switch circuit;

2. The clock synchronization apparatus of claim 1, wherein the analog switch circuit comprises a first channel corresponding to the first circuit, a second channel corresponding to the second circuit, and a first chip controlling communication of the first channel or the second channel.

3. The clock synchronization apparatus of claim 2, wherein the clock circuit comprises a clock chip for generating a clock.

4. The clock synchronization apparatus of claim 3, wherein a first pin and a second pin of the first chip are connected to the first circuit, and the first circuit receives the clock through the first pin and the second pin.

5. The clock synchronization apparatus of claim 3, wherein a third pin and a fourth pin of the first chip are connected to the second circuit, and the second circuit receives the clock through the third pin and the fourth pin.

6. The clock synchronization apparatus of claim 3, wherein a fifth pin and a sixth pin of the first chip are connected to the second circuit, and the second circuit sends an instruction to switch a transmission clock channel to the first chip through the fifth pin and the sixth pin.

7. The clock synchronization device according to claim 3, wherein a seventh pin and an eighth pin of the first chip are connected to the clock chip, and the first chip receives the clock transmitted by the clock chip through the seventh pin and the eighth pin.

8. The clock synchronization apparatus of claim 3, wherein the clock circuit further comprises a clock battery, a voltage regulator chip, and a diode; the positive pole of the clock battery is connected with the positive pole of the diode, the negative pole of the diode is connected with the input port of the voltage stabilizing chip, and the output port of the voltage stabilizing chip is connected with the power pin of the clock chip.

9. The clock synchronization apparatus of claim 1, wherein the first circuit further comprises a memory chip, the memory chip is connected to the second circuit via the bus, and the memory chip is configured to store the target data generated by the first circuit and send the target data to the second circuit.

10. An electrical terminal, characterized in that it comprises a clock synchronization device according to any one of claims 1 to 9.