CN217935594U

CN217935594U - Digital-to-analog conversion circuit

Info

Publication number: CN217935594U
Application number: CN202221384551.9U
Authority: CN
Inventors: 孟楠; 练悦星
Original assignee: Beijing Eswin Computing Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2022-11-29
Anticipated expiration: 2032-06-02

Abstract

The utility model discloses a digital-to-analog conversion circuit, include: the first operational amplifier is used for providing a second reference voltage which is consistent with the voltage value of the first reference voltage and has loading capacity according to the first reference voltage; and the conversion unit is connected with the output end of the first operational amplifier and used for converting the digital input signal according to the second reference voltage and outputting a corresponding analog voltage. The method can ensure that the reference voltage is not interfered by the change of load impedance, can obtain more accurate step and output voltage design under lower temperature sensitivity, is beneficial to reducing the number of devices required by DAC, reducing layout area and realizing stable and high-precision digital-to-analog conversion.

Description

Digital-to-analog conversion circuit

Technical Field

The utility model relates to an integrated circuit designs technical field, concretely relates to digital-to-analog conversion circuit.

Background

A Digital to Analog Converter (DAC) is a signal Converter capable of converting a Digital signal into an Analog signal, and is widely applied to various fields requiring signal processing. For example, the method can be used for portable wearable equipment, and can restore the information of human bodies such as heartbeat after digital processing into analog signals before introduction; the digital baseband signal processing device is also an important component of digital baseband signal processing, and mainly converts two paths of digital baseband signals into analog signals; the digital configuration code can be used for a power management control chip to adjust the output voltage according to the digital configuration code so as to realize accurate adjustable voltage output and the like.

However, in the power management control chip with a wide output range, the output accuracy of the conventional DAC may be deteriorated and difficult to adjust. In addition, the traditional resistance type DAC structure needs large device scale when realizing digital-to-analog conversion with the same function, occupies large layout area (the number of switches and the number of resistors are twice of the digit of a digital code value), and is low in precision. And the input of different digital code values can cause the load impedance of the access circuit to change, thus affecting the loop stability of the system, and in order to counteract or cover the change, a corresponding compensation network needs to be additionally designed, thereby increasing the design difficulty and complexity, increasing the layout area, improving the chip cost and simultaneously reducing the integration level.

Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model provides a digital-to-analog conversion circuit sets up the unit gain amplifier between reference voltage input and resistance network and for reference voltage provides the current driving ability, keeps apart reference voltage and rear end load simultaneously, guarantees that reference voltage does not receive the interference of load impedance change. Meanwhile, the resistor network and the switch array with the R-2R resistor ladder structure are used, the number of used resistors and the number of generated ports can be effectively reduced, the layout area occupied by the functional module is reduced, the chip integration level is improved, the resistors are additionally connected in series in the resistor network with the R-2R resistor ladder structure to achieve output, and more accurate stepping and output voltage design can be obtained under lower temperature sensitivity.

According to a first aspect of the present disclosure, there is provided a digital-to-analog conversion circuit comprising: the operational amplifier is used for providing a second reference voltage with loading capacity according to the first reference voltage, and the voltage value of the second reference voltage is the same as that of the first reference voltage;

and the conversion unit is connected with the output end of the first operational amplifier and used for converting the digital input signal according to the second reference voltage and outputting a corresponding analog voltage.

Optionally, the conversion unit includes:

a resistor network comprising an R-2R resistor ladder structure coupled between a reference voltage input and an output of the conversion unit;

a switch array comprising a plurality of first switches coupled between the resistive network and a first reference voltage input, and a plurality of second switches coupled between the resistive network and a third reference voltage input,

wherein the first reference voltage input terminal is connected to an output terminal of the first operational amplifier.

Optionally, the third reference voltage input is connected to a reference ground.

Optionally, the digital-to-analog conversion circuit further includes:

a second operational amplifier, a non-inverting input terminal of which receives a third reference voltage, an inverting input terminal of which is connected to an output terminal of the second operational amplifier, the second operational amplifier being configured to provide a fourth reference voltage with loading capability according to the third reference voltage, a voltage value of the fourth reference voltage being the same as a voltage value of the third reference voltage,

wherein the third reference voltage input terminal is connected to the output terminal of the second operational amplifier.

Optionally, an absolute value of a difference between the first reference voltage and the third reference voltage is greater than 0.

Optionally, the resistive network comprises:

a trunk resistor string including a plurality of first resistors connected in series;

a branched resistor string including a plurality of second resistors coupled and connected in parallel with the plurality of first resistors,

and the resistance value of each first resistor is half of the resistance value of any second resistor.

Optionally, the resistor network further includes a third resistor coupled between the main resistor string and the output end of the conversion unit, where the third resistor is used to adjust the step value of the digital-to-analog conversion circuit.

Optionally, the step value of the digital-to-analog conversion circuit is at least associated with a ratio of the resistance values of the third resistor and any one of the first resistors or any one of the second resistors.

Optionally, the smaller the ratio of the resistances of the third resistor and any first resistor is, and/or the larger the number of bits of the digital input signal is, the smaller the step value of the digital-to-analog conversion circuit is.

Optionally, the digital-to-analog conversion circuit further comprises a decoder circuit for decoding the digital input signal to generate a plurality of control signals for controlling the plurality of first switches and the plurality of second switches.

The beneficial effects of the utility model include at least:

adopt the technical scheme of the utility model, can guarantee that reference voltage does not receive the interference that load impedance changes, also can obtain more accurate step-by-step and output voltage design under lower temperature sensitivity, be favorable to reducing DAC required device quantity and reduce the territory area, realize the digital analog conversion of stable and high accuracy.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

Fig. 1 is a schematic structural diagram of a digital-to-analog conversion circuit according to a first embodiment of the present invention;

fig. 2 is a schematic structural diagram of a digital-to-analog conversion circuit according to a second embodiment of the present invention;

FIG. 3 shows an equivalent schematic diagram of the conversion unit of FIG. 1 for a digital input signal;

FIG. 4 shows an equivalent schematic diagram of the conversion unit of FIG. 3 for a digital input signal;

fig. 5 shows an equivalent schematic diagram of the conversion unit in fig. 4 for a certain digital input signal.

Detailed Description

In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that in the following description, when an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

The utility model discloses a digital-to-analog conversion circuit 100, as shown in fig. 1 and fig. 2, this digital-to-analog conversion circuit 100 can be used to change 4-bit digital input signal D <0,3> (including D <0>, D <1>, D <2>, D <3 >) into analog voltage Vout and carry out the output. It is understood that the digital-to-analog conversion performed by the digital-to-analog conversion circuit 100 on the 4-bit digital input signal D <0,3> in the embodiment of the present invention is only an exemplary illustration, and the technical solution of the present invention is also applicable to performing digital-to-analog conversion on more or less digital input signals to output the analog voltage Vout, which is not limited by the present invention.

The utility model discloses a digital analog conversion circuit 100 includes: a first operational amplifier 110 and a conversion unit 120.

The first operational amplifier 110 is connected as a unity gain buffer structure for providing a second reference voltage (denoted as V) with loading capability according to the first reference voltage Vref1 _A ) The second reference voltage V _A Is identical to the voltage value of the first reference voltage Vref1. The second reference voltage V _A The current driving capability can be provided for the reference voltage source, and the stability of the voltage of the output end of the first operational amplifier 110, i.e., the node a, during the code value switching is further achieved. Specifically, the power supply terminal of the first operational amplifier 110 receives the power supply voltage VDD, the non-inverting input terminal of the first operational amplifier 110 receives the first reference voltage Vref1, and the inverting input terminal of the first operational amplifier 110 is connected to the output terminal thereof to form a loop. A conversion unit 120 is connected to the output terminal of the first operational amplifier 110, the conversion unit 120 is used for converting the second reference voltage V _A For digital input signal D<0,3>Performs conversion and outputs a corresponding analog voltage Vout.

Since the first reference voltage Vref1 has no dc driving capability, if the first reference voltage Vref is directly connected to the converting unit 120 and connected to the circuit, the current generated in the circuit will damage the reference voltage loop, resulting in a change in the output value of the first reference voltage Vref1, thereby seriously affecting the performance of the analog-to-digital converting circuit. Therefore, the present invention provides a static dc bias for the first operational amplifier 110 by the power supply voltage VDD, so that the first operational amplifier 110 is in a normal operating state, and the output of the first operational amplifier 110 is connected to the inverting input thereof to form a unity gain amplifier to provide a current driving, i.e. a load carrying capability, for the first reference voltage Vref1. The inverting input terminal and the output terminal of the first operational amplifier 110 are connected to form a loop, so that the output terminal voltage, i.e. the node, of the first operational amplifier 110 can be enabled by loop feedback when the first operational amplifier is in normal operationA node voltage V _A Always equal to the first reference voltage Vref1 inputted to the non-inverting input terminal thereof. Can also play a role in comparing the first reference voltage Vref1 with the output terminal voltage V _A The isolation function of (3) ensures that the first reference voltage Vref1 is not interfered by the change of load impedance. In addition, the current driving capability of the output terminal of the first operational amplifier 110 can adaptively supply the required current according to the loop adjustment, and the driving performance is stronger and the stability is higher.

The utility model provides a digital-to-analog conversion circuit 100 structure can provide fixed impedance for the unit gain buffer loop only need work in single environment, can reduce the design degree of difficulty of unit gain buffer and simplify the compensation loop design effectively, has improved system job stabilization nature.

In some examples of the present invention, the conversion unit 120 further includes: a resistor network 121 and a switch array 122. The resistor network 121 comprises an R-2R resistor ladder structure coupled between reference voltage input terminals (including a first reference voltage input terminal and a third reference voltage input terminal) and an output terminal of the conversion unit, i.e. an output terminal of the analog voltage Vout.

The resistor network 121 includes: trunk resistor string and branch resistor string. The trunk resistor string includes a plurality of first resistors connected in series. The branch resistor string comprises a plurality of second resistors which are coupled with the plurality of first resistors and are connected in parallel. The resistance value of each first resistor is half of the resistance value of any second resistor. The embodiment of the utility model provides an in, contain n +1 parallelly connected resistance branch in the DAC of n bit, all include a second resistance on every resistance branch, n is for being greater than 1 positive integer.

Referring to fig. 1 and 2, taking a 4-bit R-2R DAC as an example, the resistor network 121 includes a plurality of second resistors (R1 to R5) and a plurality of first resistors (R6 to R9). Resistors R1-R5 form a branch resistor string of resistor network 121, and resistors R6-R9 form a trunk resistor string of resistor network 121. The first end of the resistor R1 is directly connected with the first end of the resistor R2, the first ends of the resistor R2 and the resistor R3 are connected through a resistor R6, the first ends of the resistor R3 and the resistor R4 are connected through a resistor R7, the first ends of the resistor R4 and the resistor R5 are connected through a resistor R8, and the first end of the resistor R5 is further connected with the middle node of the resistor R8 and the resistor R9.

Switch array 122 includes a plurality of switches (including switches K1, K2, K3, K4) coupled between resistor network 121 and the reference voltage input. The reference voltage input end comprises a first reference voltage input end and a third reference voltage input end. The first reference voltage input terminal corresponds to the output terminal of the first operational amplifier 110.

Exemplarily, in the first embodiment of the present invention, as shown in fig. 1, the third reference voltage input terminal is connected to the reference ground, i.e. the third reference voltage (denoted as Vref 2) corresponds to the reference ground potential. In this embodiment, the second end of the resistor R1 is connected to the reference ground, the second end of the resistor R2 is connected to the output terminal of the first operational amplifier 110 and the reference ground through the switch K1, the second end of the resistor R3 is connected to the output terminal of the first operational amplifier 110 and the reference ground through the switch K2, the second end of the resistor R4 is connected to the output terminal of the first operational amplifier 110 and the reference ground through the switch K3, and the second end of the resistor R5 is connected to the output terminal of the first operational amplifier 110 and the reference ground through the switch K4.

In the second embodiment of the present invention, as shown in fig. 2, the digital-to-analog conversion circuit 100 further includes a second operational amplifier 140, and the third reference voltage input end is connected to the output end of the second operational amplifier 140. In this embodiment, the second operational amplifier 140 is also connected to form a unity gain buffer structure for providing a fourth reference voltage (denoted as V) with loading capability according to the third reference voltage Vref2 _B ) The fourth reference voltage V _B Is identical to the voltage value of the third reference voltage Vref 2. The fourth reference voltage V _B The current driving capability can be provided for the reference voltage source, and the stability of the voltage at the output end of the second operational amplifier 140, i.e., the node B, can be further achieved during the code value switching. Specifically, the non-inverting input terminal of the second operational amplifier 140 receives the third reference voltage Vref2, and the inverting input terminal of the second operational amplifier 140 is connected to the output terminal (i.e., node B) of the second operational amplifier 140 to form a loop. It will be appreciated that the second operational amplifier 140 are similar in function and function to the first operational amplifier 110 and therefore may be understood with reference to the foregoing description of the first operational amplifier 110 and will not be described in detail herein.

In this embodiment, the absolute value of the difference between the first reference voltage Vref1 and the third reference voltage Vref2 is greater than 0. Therefore, the digital-to-analog conversion circuit 100 in this embodiment can perform digital-to-analog conversion on the digital input signal D <0,3> between the first reference voltage Vref1 and the third reference voltage Vref 2.

Optionally, in some examples of the invention, the plurality of switches in the switch array 122 includes a plurality of first switches and a plurality of second switches. A first plurality of switches is coupled between the resistor network 121 and the first reference voltage input, and a second plurality of switches is coupled between the resistor network 121 and the third reference voltage input. At this time, the plurality of first switches and the plurality of second switches are, for example, any one of bipolar transistors, thyristors, and field effect transistors. In other words, each of the plurality of switches includes one first switch and one second switch. In other examples of the present invention, the plurality of switches in the switch array 122 include a plurality of alternative selection switches, such as relay switches. At this time, the common terminal of each switch is connected to the second terminal of the corresponding second resistor in the resistor network 121, the first selection terminal of each switch is connected to the first reference voltage input terminal, and the second selection terminal of each switch is connected to the third reference voltage input terminal.

Further, the digital-to-analog conversion circuit 100 further includes a decoder circuit 130. The decoder circuit 130 is used for decoding a digital input signal to generate a plurality of control signals for controlling the plurality of switches.

When one control signal in the control signals has a first level state, the corresponding switch can be controlled to connect the second end of the corresponding second resistor with the first reference voltage input end; when one of the control signals has a second level state, the corresponding switch can be controlled to connect the second end of the corresponding second resistor and the third reference voltage input end. The utility model discloses in, the number of second resistance in digital input signal's the figure less than or equal to a plurality of second resistance. Illustratively, taking the switch K1 as an example, when a control signal corresponding to the control switch K1 in the plurality of control signals has a first level state, the switch K1 may be controlled to connect the second end of the resistor R2 with the first reference voltage input end; when the control signal has the second level state, the switch K1 is controlled to connect the second terminal of the resistor R2 to the third reference voltage input terminal.

The embodiment of the utility model provides an in, use resistance network and the switch array that has R-2R resistance ladder structure, can effectively reduce the resistance quantity and the port quantity in the circuit that uses to be favorable to reducing the territory area that this functional module occupy, improve the chip integrated level.

In a preferred embodiment of the present invention, the resistor network 121 further comprises a third resistor R10. The third resistor R10 is connected in series with the plurality of first resistors in the main resistor string, wherein a first end of the third resistor R10 is connected to the resistor R9, and a second end of the third resistor R10 is connected to the output end of the converting unit 120. The third resistor R10 is used to adjust the step value of the digital-to-analog conversion circuit 100.

Illustratively, taking the third reference voltage Vref2 equal to zero, the digital input signal D <0,3> is "0001", and the switch K1 is correspondingly controlled by the D <0> bit in the digital input signal, the switch K2 is correspondingly controlled by the D <1> bit in the digital input signal, the switch K3 is correspondingly controlled by the D <2> bit in the digital input signal, and the switch K4 is correspondingly controlled by the D <3> bit in the digital input signal as an example. When a digital input signal bit is 0, the corresponding control signal is at a low level, and can control the corresponding switch to connect the resistor network 121 and the third reference voltage input end, i.e., the reference ground, and when a digital input signal bit is 1, the corresponding control signal is at a high level, and can control the corresponding switch to connect the resistor network 121 and the first reference voltage input end. At this time, the converting unit 120 may be equivalent to fig. 3.

In the resistor network 121, the following relationship exists between the resistance values of the resistors: r1= R2= R3= R4= R5=2 × R6=2 × R7=2 × R8=2 × R9, and when the resistance value of the resistor R1 is X (X is a positive number), there are: r1= R2= R3= R4= R5=2X; r6= R7= R8= R9= X.

The circuit equivalent analysis is carried out from the node C to obtain: the equivalent impedance from the node C to the reference ground is the equivalent impedance after the resistor R2 is connected with the resistor R1 in parallel, namely R _Ceq = (R1// R2) = X; then, the equivalent impedance analysis is carried out from the node D, and the equivalent impedance from the node D to the reference ground is the equivalent impedance R of the node C to the reference ground _Ceq Equivalent impedance, i.e. R, after being connected in series with the resistor R6 and then connected in parallel with the resistor R3 _Deq ＝(R3//(R6+R _Ceq ) ) = X. In the same way, the equivalent impedances obtained by the equivalent impedance analysis of the node C, D, E are all the unit resistance value X, so the equivalent analysis of the resistance from the node F to the reference ground is performed to obtain the resistance R8 and the equivalent resistance R _Eeq In series, i.e. R _Feq ＝R8+R _Eeq =2X, as shown in fig. 4.

Equivalent voltage analysis: the following relationship exists due to resistance: r5= R8+ R _Eeq =2X, and the equivalent voltage of the node F can be obtained to be Vref1/2. Further, the equivalent circuit of the series resistance of the voltage source shown in fig. 5 can be obtained by performing wiinan equivalent analysis on the part inside the dashed box in fig. 4. In this case, the resistor network 121 in the digital-to-analog conversion circuit 100 can be equivalent to the resistor R10, the resistor R9, and the equivalent resistor R as a whole _Feq A structure in series with the voltage source V1, and thus the digital input signal "0001" at that time, results in V1= Vref1/2.

According to the above analysis, it can be deduced that the equivalent voltage of the voltage source V1 will change along with the change of the digital input signal D <0,3>, and the specific relationship is as follows:

V1＝D<0>*Vref1/16+D<1>*Vref1/8+D<2>*Vref1/4+D<3>*Vref1/2。

it can therefore be further deduced that:

Vout＝((2*R9+R10)/(2*R9))*VFB+(1-(2*R9+R10)/(2*R9)))*V1

＝(1+(R10/(2*R9)))*VFB-(R10/(2*R9))*V1

= (= (1 + (R10/(2 × R9))) + VFB- (D <0> + Vref1/16+ D < -1 > + Vref1/8+ D < -2 > + Vref1/4+ D < -3 > + Vref 1/2) (+ R10/(2 × R9)), where VFB is the voltage of the common connection node of the resistor R9 and the resistor R10.

Therefore, a linear functional relationship exists between the analog voltage Vout output by the digital-to-analog conversion circuit 100 and the VFB, and the analog voltage Vout can be configured by the code value of the digital input signal D <0,3> to obtain an accurate output result.

In addition, as can be seen from the above description, the step value of the dac circuit 100 is (R10/(2 × R9)) (Vref/16). That is, the step value of the dac circuit 100 is at least related to the ratio of the resistance values of the third resistor R10 and any one of the first resistors or any one of the second resistors (e.g., the resistor R9), and different precise step values and output voltage designs can be obtained by adjusting the ratio. Since the step value is a correlation term obtained by dividing two resistors, the temperature sensitivity is lower under the same condition, and the high-precision performance requirement of the digital-to-analog conversion circuit 100 can be maintained even if the digital-to-analog conversion circuit is in a working state with large environmental temperature change.

The smaller the ratio of the resistance values of the third resistor R10 and any one of the first resistors or any one of the second resistors is, the smaller the step value of the digital-to-analog conversion circuit 100 is, and the higher the voltage conversion accuracy of the digital-to-analog conversion circuit 100 is. It is understood that the resistance of the third resistor R10 may be any value that meets the requirement of the step value.

In addition, the step value of the digital-to-analog conversion circuit 100 is also related to the number of bits of the digital input signal. For example, in a case where the first reference voltage (or the absolute value of the difference between the first reference voltage and the third reference voltage) received by the digital-to-analog conversion circuit 100 is not changed, the larger the number of bits of the digital input signal, the smaller the step value of the digital-to-analog conversion circuit 100.

It should be understood that, when the technical solution of the present invention is applied to digital-to-analog conversion application of digital input signals with other digits to output corresponding analog voltages, it is only necessary to increase or decrease the corresponding resistor quantity and switch quantity in the conversion unit according to the same or similar conversion unit architecture, and the digital-to-analog conversion circuit structure generated thereby should be within the protection scope of the present invention.

Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications can be made without departing from the scope of the present invention.

Claims

1. A digital-to-analog conversion circuit, comprising:

the operational amplifier is used for providing a second reference voltage with loading capacity according to the first reference voltage, and the voltage value of the second reference voltage is the same as that of the first reference voltage;

2. The digital-to-analog conversion circuit according to claim 1, wherein the conversion unit includes:

3. Digital to analog conversion circuit according to claim 2, characterized in that the third reference voltage input is connected to a reference ground.

4. The digital-to-analog conversion circuit according to claim 2, further comprising:

5. The digital-to-analog conversion circuit of claim 4, wherein an absolute value of a difference between the first reference voltage and the third reference voltage is greater than 0.

6. The digital-to-analog conversion circuit of claim 2, wherein the resistor network comprises:

7. The DAC circuit of claim 6, wherein the resistor network further comprises a third resistor coupled between the trunk resistor string and the output end of the conversion unit, the third resistor being configured to adjust the step value of the DAC circuit.

8. The DAC circuit of claim 7 wherein the step value of the DAC circuit is related to at least the ratio of the third resistor to the resistance of either the first resistor or the second resistor.

9. The digital-to-analog conversion circuit according to claim 8, wherein the smaller the ratio of the resistance values of the third resistor and any one of the first resistors is, and/or the larger the number of bits of the digital input signal is, the smaller the step value of the digital-to-analog conversion circuit is.

10. The digital-to-analog conversion circuit of claim 2, further comprising a decoder circuit for decoding the digital input signal to generate a plurality of control signals that control the plurality of first switches and the plurality of second switches.