CN217935448U - Chip starting circuit, controller, electronic equipment and vehicle - Google Patents
Chip starting circuit, controller, electronic equipment and vehicle Download PDFInfo
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- CN217935448U CN217935448U CN202221502651.7U CN202221502651U CN217935448U CN 217935448 U CN217935448 U CN 217935448U CN 202221502651 U CN202221502651 U CN 202221502651U CN 217935448 U CN217935448 U CN 217935448U
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Abstract
The embodiment of the disclosure relates to a chip starting circuit, a controller, an electronic device and a vehicle. The chip starting circuit comprises a first input end, a second input end, a first output end, a second output end and an enabling circuit, wherein the first input end is connected with a first power supply end arranged outside, the second input end is connected with a second power supply end arranged outside, the first output end is connected with a power supply input end of a power supply chip arranged outside, and the second output end is connected with the enabling end of the power supply chip; the enabling circuit is respectively connected with the second input end and the second output end; and the enabling circuit is used for controlling the conduction of a second path between the second power supply end and the enabling end of the power supply chip after the first path between the first power supply end and the power supply input end of the power supply chip is conducted. By adopting the embodiment of the disclosure, the disorder of the internal control logic of the power supply chip can be avoided, and the normal opening of the power supply chip is ensured.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of power chips, in particular to a chip starting circuit, a controller, electronic equipment and a vehicle.
Background
With the rapid development of automobile technology, more and more controllers are used in automobiles, and the controllers are more and more complex. Currently, most controllers on a whole vehicle select a power chip with enable control in order to consider the quiescent current of a product.
In general, a power chip receives a supply voltage through a supply voltage input terminal, enables the voltage through an enable terminal, and needs to ensure that the supply voltage is input to the power chip before the enable voltage. However, when the supply voltage slowly rises and falls, the enable voltage is easily input to the power chip before the supply voltage, which may cause disorder of the internal control logic of the power chip and prevent the power chip from being normally turned on.
SUMMERY OF THE UTILITY MODEL
The embodiment of the disclosure provides a chip starting circuit, a controller, electronic equipment and a vehicle, which can ensure that a power supply voltage is input into a power supply chip before an enabling voltage, and avoid disorder of internal control logic of the power supply chip, so that the power supply chip is normally started.
In a first aspect, an embodiment of the present disclosure provides a chip start circuit, which includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and an enable circuit, where the first input terminal is connected to a first power supply terminal externally disposed, the second input terminal is connected to a second power supply terminal externally disposed, the first output terminal is connected to a power supply input terminal of a power supply chip externally disposed, and the second output terminal is connected to an enable terminal of the power supply chip; the enabling circuit is respectively connected with the second input end and the second output end; and the enabling circuit is used for controlling the conduction of a second path between the second power supply end and the enabling end of the power supply chip after a first path between the first power supply end and the power supply input end of the power supply chip is conducted.
In a second aspect, an embodiment of the present disclosure provides a controller, which includes a power chip and the chip start circuit described in the first aspect.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including the controller in the second aspect.
In a fourth aspect, an embodiment of the present disclosure provides a vehicle including the electronic device of the third aspect.
The chip starting circuit comprises a first input end, a second input end, a first output end, a second output end and an enabling circuit, wherein the first input end is connected with a first power supply end arranged outside, the second input end is connected with a second power supply end arranged outside, the first output end is connected with a power supply input end of a power supply chip arranged outside, and the second output end is connected with the enabling end of the power supply chip; the enabling circuit is respectively connected with the second input end and the second output end; and the enabling circuit is used for controlling the conduction of a second path between the second power supply end and the enabling end of the power supply chip after a first path between the first power supply end and the power supply input end of the power supply chip is conducted. Through the embodiment of the disclosure, the power input end of the power chip can receive voltage before the enable end, so that the internal control logic of the power chip is ensured to be normal, and the power chip can be started normally.
Drawings
FIG. 1 is a diagram illustrating an exemplary chip start-up circuit;
FIG. 2 is a second schematic diagram of an embodiment of a chip start-up circuit;
FIG. 3 is a third schematic diagram of a chip start-up circuit according to an embodiment;
FIG. 4 is a fourth schematic diagram of a chip start-up circuit according to an embodiment;
FIG. 5 is a fifth schematic diagram of the chip start-up circuit in one embodiment;
description of reference numerals:
a chip start circuit 10, an enable circuit 11, a power chip 20;
a first enable circuit 111, a second enable circuit 112, a filter circuit 12;
the circuit comprises a first resistor R1, a second resistor R2, a third resistor R2, a fourth resistor R4 and a fifth resistor R5;
the circuit comprises a first capacitor C1, a second capacitor C2, a third capacitor C3, a diode D and a ground terminal GND.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clearly understood, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the embodiments of the disclosure and that no limitation to the embodiments of the disclosure is intended.
First, before specifically describing the technical solution of the embodiment of the present disclosure, a technical background or a technical evolution context on which the embodiment of the present disclosure is based is described. Under a normal condition, the power supply chip receives a power supply voltage through the power input terminal, receives an enable voltage through the enable terminal, and needs to ensure that the power supply voltage is input into the power supply chip before the enable voltage, so that the internal control logic of the power supply chip can be ensured to be normal. However, when the supply voltage slowly increases and slowly decreases, for example, the supply voltage slowly increases but does not reach the minimum voltage required by the power input terminal of the power chip, or the supply voltage slowly decreases and then becomes lower than the minimum voltage required by the power input terminal of the power chip, the enable terminal of the power chip receives the enable voltage first, and the power input terminal receives the supply voltage later. This situation may cause disorder of internal control logic of the power chip, and the power chip may not be normally turned on. Further, the power supply chip cannot be normally started, which may cause that a more important controller in the vehicle cannot be started, thereby making it difficult to ensure the safety of the vehicle. In addition, it should be noted that, from the finding that the gradual rise and fall of the power supply voltage easily causes the disorder of the internal control logic of the power supply chip and the technical solution described in the following embodiments, the applicant has paid a lot of creative efforts.
In one embodiment, as shown in FIG. 1, a chip start-up circuit is provided. The chip starting circuit 10 comprises a first input end IN1, a second input end IN2, a first output end OUT1, a second output end OUT2 and an enabling circuit 11, wherein the first input end IN1 is connected with a first power supply end V1 arranged outside, the second input end IN2 is connected with a second power supply end V2 arranged outside, the first output end OUT1 is connected with a power supply input end SUP of a power supply chip 20 arranged outside, and the second output end OUT2 is connected with an enabling end EN of the power supply chip 20; the enable circuit 11 is connected to the second input terminal IN2 and the second output terminal OUT2, respectively; the enabling circuit 11 is configured to control a second path between the second power supply terminal V2 and the enabling terminal EN of the power chip 20 to be conducted after a first path between the first power supply terminal V1 and the power input terminal SUP of the power chip 20 is conducted.
IN the embodiment of the present disclosure, the chip start circuit 10 includes a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1, a second output terminal OUT2, and an enable circuit 11. The enable circuit 11 is connected to the second input terminal IN2 and the second output terminal OUT 2.
The chip start circuit 10 is externally provided with a first power supply terminal V1, a second power supply terminal V2 and a power supply chip 20. The first input end IN1 of the chip starting circuit 10 is connected with the first power supply end V1, the second input end IN2 of the chip starting circuit 10 is connected with the second power supply end V2, the first output end OUT1 of the chip starting circuit 10 is connected with the power supply input end SUP of the power supply chip 20, and the second output end OUT2 of the chip starting circuit 10 is connected with the enabling end EN of the power supply chip 20.
When the first power supply terminal V1 inputs a voltage to the chip start circuit 10, a first path between the first power supply terminal V1 and the power input terminal SUP of the power chip 20 is turned on, that is, the voltage input by the first power supply terminal V1 is transmitted to the power input terminal SUP of the power chip 20. Then, the enabling circuit conducts a second path between the second power supply terminal V2 and the enabling terminal EN of the power chip 20 according to the voltage input by the first power supply terminal V1 and the voltage input by the second power supply terminal V2.
It can be understood that, since the first path is directly conducted when the first power supply terminal V1 inputs a voltage, and the second path needs to be conducted according to the voltage input by the first power supply terminal V1 and the voltage input by the second power supply terminal V2, the power input terminal SUP of the power chip 20 can receive the voltage before the enable terminal EN, so as to ensure that the internal control logic of the power chip 20 is normal, and the power chip 20 can be normally started.
For example, in a case where the voltage input by the first power supply terminal V1 gradually rises or falls, the power supply input terminal SUP of the power supply chip 20 may directly receive the voltage input by the first power supply terminal V1. However, the enable terminal EN of the power chip 20 can receive the voltage only when the voltage inputted from the first power supply terminal V1 and the voltage inputted from the second power supply terminal V2 are both appropriate. Thus, even if the voltage input by the first power supply terminal V1 gradually rises and falls, the power supply input terminal SUP of the power supply chip 20 can be ensured to receive the voltage before the enable terminal EN.
When the chip start circuit 10 and the power chip 20 are applied to a vehicle, the first power supply terminal V1 may be a voltage output terminal of a vehicle battery, and the second power supply terminal V2 may be a vehicle power supply terminal. The voltage output by the power supply end of the whole vehicle is obtained by converting the battery voltage of the storage battery of the whole vehicle.
The power supply chip 20 may be a DCDC power supply chip 20. The embodiments of the present disclosure do not limit this.
In the above embodiment, the first input end of the chip start circuit is connected to a first power supply end provided outside, the second input end is connected to a second power supply end provided outside, the first output end is connected to a power supply input end of a power supply chip provided outside, the second output end is connected to an enable end of the power supply chip, and the enable circuit is respectively connected to the second input end and the second output end; and the enabling circuit controls the second path between the second power supply end and the enabling end of the power supply chip to be conducted after the first path between the first power supply end and the power supply input end of the power supply chip is conducted. Through the embodiment of the disclosure, the power input end of the power chip can receive voltage before the enable end, so that the internal control logic of the power chip is ensured to be normal, and the power chip can be started normally.
In one embodiment, as shown in fig. 2, the enabling circuit 11 includes a first enabling circuit 111 and a second enabling circuit 112 connected to each other, the first enabling circuit 111 is further connected to the second power supply terminal V2, and the second enabling circuit 112 is further connected to the first power supply terminal V1 and the enabling terminal EN of the power supply chip 20; the first enabling circuit 111 is driven by the voltage output by the second power supply terminal V2 to be conducted, and outputs the voltage to the second enabling circuit 112 after being conducted; and the second enabling circuit 112 is used for conducting under the driving of the first enabling circuit 111 and the voltage output by the first power supply terminal V1 so as to conduct the second path.
In the embodiment of the present disclosure, the enable circuit 11 includes a first enable circuit 111 and a second enable circuit 112, and the first enable circuit 111 and the second enable circuit 112 are connected to each other. The first enable circuit 111 is further connected to an externally provided second power supply terminal V2, and the second enable circuit 112 is further connected to an externally provided first power supply terminal V1 and an enable terminal EN of the power supply chip 20.
The first enabling circuit 111 receives the voltage output by the second power supply terminal V2 and is driven by the voltage to be turned on. After being turned on, the first enable circuit 111 outputs a voltage to the second enable circuit 112. The second enable voltage receives the voltage output by the first enable circuit 111 and the voltage output by the first power supply terminal V1, and is driven by the two voltages to conduct, so that the second path between the second power supply terminal V2 and the enable terminal EN of the power chip 20 is conducted.
For example, in a case where the voltage input by the first power supply terminal V1 gradually rises or falls, the power supply input terminal SUP of the power supply chip 20 may directly receive the voltage input by the first power supply terminal V1. However, after the first enabling circuit 111 is turned on, the second enabling circuit 112 is turned on only when the voltage output by the first enabling circuit 111 and the voltage output by the first power supply terminal V1 are both proper, so that the power input terminal SUP of the power chip 20 can be ensured to receive the voltage before the enabling terminal EN receives the voltage.
In the above embodiment, the enable circuit includes a first enable circuit and a second enable circuit, the first enable circuit is turned on by the driving of the voltage output by the second power supply terminal, and outputs the voltage to the second enable circuit after being turned on; the second enabling circuit is driven by the first enabling circuit and the voltage of the first power supply output to be conducted, so that the second path is conducted. By adopting the first enabling circuit and the second enabling circuit of the embodiment of the disclosure, the time for the enabling end of the power chip to receive the voltage can be delayed, so that the power input end of the power chip receives the voltage before the enabling end, the internal control logic of the power chip is ensured to be normal, and the power chip can be started normally.
In one embodiment, as shown in fig. 3, the first enabling circuit 111 includes a first transistor Q1, a first resistor R1, and a second resistor R2; a base b1 of the first triode Q1 is connected with a first end of the first resistor R1, a collector c1 of the first triode Q1 is connected with the second enabling circuit 112, and an emitter e1 of the first triode Q1 is connected with a ground terminal GND; the second end of the first resistor R1 is connected with the second power supply end V2; a first end of the second resistor R2 is connected to the first end of the first resistor R1, and a second end of the second resistor R2 is connected to the ground GND.
In the embodiment of the present disclosure, the first enabling circuit 111 includes a first triode Q1, a first resistor R1, and a second resistor R2, where the first resistor R1 and the second resistor R2 form a voltage dividing structure. As shown in fig. 3, the base b1 of the first transistor Q1 is connected to the first end of the first resistor R1, the collector c1 is connected to the second enable circuit 112, and the emitter e1 is connected to the ground GND. The second end of the first resistor R1 is connected to the second power supply terminal V2. The first end of the second resistor R2 is connected to the first end of the first resistor R1, and the second end is connected to the ground GND.
The second power supply terminal V2 inputs a voltage to the first enable circuit 111, and the voltage is transmitted to the base b1 of the first transistor Q1 and the first terminal of the second resistor R2 through the first resistor R1. The voltage across the second resistor R2 is a voltage difference between the base b and the emitter e1 of the first triode Q1, when the voltage difference is greater than or equal to the turn-on voltage of the first triode Q1, the first triode Q1 is turned on, and the emitter e1 of the first triode Q1 inputs a voltage to the second enable circuit 112.
The resistance values of the first resistor R1 and the second resistor R2 can be set according to actual conditions, so that the first resistor R1 provides proper current for the first triode Q1, and the second resistor R2 can limit the voltage difference between the base b1 and the emitter e1 of the first triode Q1. Moreover, when the voltage input by the second power supply terminal V2 is 0, the second resistor R2 may also limit the voltage of the base b1 of the first triode Q1 to 0, so as to ensure that the first triode Q1 is turned off, and prevent the voltage input by the second power supply terminal V2 from being transmitted to the enable terminal EN of the power chip 20.
In the above embodiment, the first enabling circuit includes the first triode, the first resistor and the second resistor, and through conduction of the first triode and voltage division of the first resistor and the second resistor, a suitable input voltage can be provided for the second enabling circuit, so that conduction conditions of the second enabling circuit are expanded, and it is avoided that the conduction conditions of the second enabling circuit are too harsh to make the enabling end of the power chip difficult to receive voltage.
In one embodiment, as shown in fig. 3, the first enabling circuit 111 further includes a first capacitor C1; the first end of the first capacitor C1 is connected to the second power supply terminal V2, and the second end of the first capacitor C1 is connected to the ground terminal GND.
In the embodiment of the present disclosure, the first enabling circuit 111 may further include a first capacitor C1, a first end of the first capacitor C1 is connected to the second power supply terminal V2, and a second end is connected to the ground terminal GND. The first capacitor C1 can play a role in electrostatic protection, and when a large amount of electrostatic charges are input to the second power supply terminal V2, the electrostatic charges are stored by the first capacitor C1, so that damage to the first triode Q1 caused by the electrostatic charges can be avoided.
In the above embodiment, the first enabling circuit further includes a first capacitor, and the first capacitor can prevent electrostatic damage, thereby protecting the chip start circuit and the power chip.
In one embodiment, as shown in fig. 3, the second enable circuit 112 includes a second transistor Q2, a third resistor R3, and a fourth resistor R4; a base b2 of the second triode Q2 is connected with the first enabling circuit 111, a collector c2 of the second triode Q2 is connected with a first end of the third resistor R3, and an emitter e2 of the second triode Q2 is connected with the first power supply end V1; a second end of the third resistor R3 is connected to the enable end EN of the power chip 20; a first end of the fourth resistor R4 is connected to the enable end EN of the power chip 20, and a second end of the fourth resistor R4 is connected to the ground GND.
In the embodiment of the present disclosure, the second enabling circuit 112 includes a second transistor Q2, a third resistor R3, and a fourth resistor R4, and the third resistor R3 and the fourth resistor R4 form a voltage dividing structure. As shown in fig. 3, a base b2 of the second transistor Q2 is connected to a collector c1 of the first transistor Q1 in the first enabling circuit 111, a collector c2 of the second transistor Q2 is connected to a first end of the third resistor R3, and an emitter e2 of the second transistor Q2 is connected to a first power supply terminal V1 provided outside. The second end of the third resistor R3 is connected to the enable terminal EN of the power chip 20, the first end of the fourth resistor R4 is connected to the enable terminal EN of the power chip 20, and the second end of the fourth resistor R4 is connected to the ground GND.
After the first transistor Q1 in the first enable circuit 111 is turned on, the collector c1 of the first transistor Q1 inputs a voltage to the base b2 of the second transistor Q2. The voltage difference between the voltage and the voltage input by the first power supply terminal V1 is the voltage difference between the base b2 and the emitter e2 of the second transistor Q2. When the voltage difference between the base b2 and the emitter e2 of the second triode Q2 is greater than or equal to the turn-on voltage of the second triode Q2, the second triode Q2 is turned on. The collector c2 of the second transistor Q2 then outputs a voltage to the third resistor R3, and the voltage is transmitted to the enable terminal EN of the power chip 20, so that the second path between the second power supply terminal V2 and the enable terminal EN of the power chip 20 is conducted.
The resistance values of the third resistor R3 and the fourth resistor R4 can be set according to actual conditions, so that the third resistor R3 can provide a suitable current for the enable terminal EN of the power chip 20, and the fourth resistor R4 can limit the voltage of the enable terminal EN of the power chip 20.
In the above embodiment, the second enabling circuit includes a second transistor, a third resistor, and a fourth resistor; the second triode can delay the time that the enable end of the power chip receives voltage, so that the power input end of the power chip receives voltage before the enable end, the internal control logic of the power chip is guaranteed to be normal, and the power chip can be started normally.
In one embodiment, as shown in FIG. 3, the second enabling circuit 112 further includes a fifth resistor R5; a first end of the fifth resistor R5 is connected to the first enable circuit 111, and a second end of the fifth resistor R5 is connected to the base b2 of the second transistor Q2.
In the embodiment of the present disclosure, the second enabling circuit 112 further includes a fifth resistor R5, a first end of the fifth resistor R5 is connected to the collector c1 of the first transistor Q1 in the first enabling circuit 111, and a second end of the fifth resistor R5 is connected to the base b2 of the second transistor Q2.
The collector c1 of the first transistor Q1 outputs a voltage, which is transmitted to the base b2 of the second transistor Q2 through the fifth resistor R5, and the voltage inputted from the first power supply terminal V1 is transmitted to the emitter e2 of the second transistor Q2. When the voltage difference between the base b2 and the emitter e2 of the second triode Q2 is greater than or equal to the turn-on voltage of the second triode Q2, the second triode Q2 is turned on.
For example, in the case that the voltage input by the first power supply terminal V1 gradually rises or falls, the voltage input by the first power supply terminal V1 can still be transmitted to the power supply input terminal SUP of the power supply chip 20. However, the voltage difference between the base b2 and the emitter e2 of the second transistor Q2 may be smaller than the turn-on voltage of the second transistor Q2, resulting in turn-off of the second transistor Q2. In this way, the voltage input by the second power supply terminal V2 cannot be transmitted to the enable terminal EN of the power chip 20, so that the power input terminal SUP of the power chip 20 is ensured to receive the voltage before the enable terminal EN.
In the above embodiment, the second enabling circuit further includes a fifth resistor, and the fifth resistor can provide a suitable current for the base of the second triode, so that the second triode can be normally turned on, and the second triode can be protected.
In one embodiment, as shown in fig. 4, the chip start circuit 10 further includes a filter circuit 12, and the filter circuit 12 is connected to the first power supply terminal V1 and the power supply input terminal SUP of the power supply chip 20.
In the embodiment of the present disclosure, the chip start circuit 10 may further include a filter circuit 12, and the filter circuit 12 is connected to the first power supply terminal V1 and the power supply input terminal SUP of the power supply chip 20, which are disposed outside. The filter circuit 12 may perform a filtering function to prevent interference signals from entering the power chip 20.
In the above embodiment, the chip start circuit further includes a filter circuit, and the filter circuit can perform a filtering function to prevent an interference signal from entering the power chip.
In one embodiment, the filter circuit 12 includes at least one second capacitor C2; a first end of the second capacitor C2 is connected to the power input terminal SUP of the power chip 20, and a second end of the second capacitor C2 is connected to the ground terminal GND.
In the disclosed embodiment, the filter circuit 12 may include one or more second capacitors C2. As shown in fig. 5, the filter circuit 12 includes two second capacitors C2, and first ends of the two second capacitors C2 are both connected to the power input terminal SUP of the power chip 20, and second ends thereof are both connected to the ground terminal GND.
The second capacitor C2 can play a role in filtering, and the capacitance values of the second capacitors C2 are different, so that interference signals with different frequencies can be filtered respectively, and a better filtering effect is realized.
In the above embodiment, the filter circuit includes at least one second capacitor, and the filtering in multiple frequency ranges can be realized through multiple second capacitors with different capacitance values, so as to achieve a better filtering effect.
In one embodiment, as shown in fig. 5, the filter circuit 12 further includes a third capacitor C3; a first end of the third capacitor C3 is connected to the first power supply terminal V1, and a second end of the third capacitor C3 is connected to the ground GND.
In the embodiment of the present disclosure, the filter circuit 12 may further include a third capacitor C3, a first end of the third capacitor C3 is connected to the first power supply terminal V1, and a second end is connected to the ground terminal GND. The third capacitor C3 can play a role in electrostatic protection, and when a large amount of electrostatic charges are input to the first power supply terminal V1, the third capacitor C3 stores the electrostatic charges, so that damage to the second triode Q2 and the power supply chip 20 by the electrostatic charges can be avoided.
In the above embodiment, the filter circuit further includes a third capacitor, and the third capacitor can prevent electrostatic damage and protect the chip start circuit and the power chip.
In one embodiment, as shown in FIG. 5, filter circuit 12 further includes a diode D; the anode of the diode D is connected to the first power supply terminal V1, and the cathode of the diode D is connected to the power supply input terminal SUP of the power supply chip 20.
In the embodiment of the present disclosure, the filter circuit 12 may further include a diode D, an anode of the diode D is connected to the first power supply terminal V1, and a cathode of the diode D is connected to the power supply input terminal SUP of the power supply chip 20. The diode D may be used for protection, that is, when the voltage input from the first power supply terminal V1 is greater than or equal to the turn-on voltage of the diode D, the diode D is turned on, and the voltage input from the first power supply terminal V1 may be transmitted to the power supply input terminal SUP of the power supply chip 20, but the diode D is connected in a manner that prevents the voltage from being reversely transmitted back to the first power supply terminal V1.
In the above embodiment, the filter circuit further includes a diode, and the diode can prevent the voltage from flowing backwards, so as to protect the chip start circuit and the power supply chip.
In one embodiment, a controller is provided, and the controller comprises a power supply chip and the chip starting circuit in the above embodiment.
In the embodiment of the disclosure, the controller comprises a power chip and a chip starting circuit, the chip starting circuit can enable the power input end of the power chip to receive voltage before the enable end, even if the voltage input by the first power supply end slowly rises and slowly falls, the internal control logic of the power chip can be ensured to be normal, the power chip is normally started, and the controller normally works. Furthermore, the success of the power supply voltage slow-rising and slow-falling test on the power supply chip can be ensured, and the test efficiency is improved.
In one embodiment, an electronic device is provided, the electronic device comprising the controller of the above embodiments.
In the embodiment of the present disclosure, the electronic device may include a plurality of controllers, each of which includes a power supply chip and a chip start-up circuit. The chip starting circuit can enable the power supply input end of the power supply chip to receive voltage prior to the enabling end, even if the voltage input by the first power supply end slowly rises and slowly falls, normal starting of the power supply chip can be guaranteed, and the controller and the electronic equipment can normally work.
In one embodiment, a vehicle is provided, the vehicle comprising the electronic device of the above embodiment.
In the disclosed embodiment, the vehicle may include one or more electronic devices, and the electronic devices may include a plurality of controllers, each of which includes a power supply chip and a chip start circuit. The chip starting circuit can enable the power input end of the power chip to receive voltage prior to the enabling end, even if the voltage input by the first power supply end slowly rises and slowly falls, the normal starting of the power chip can be guaranteed, and the controller and the electronic equipment can normally work, so that the vehicle can normally work.
In the vehicle, the controller can be a controller in a hydraulic system, can also be a controller in a cockpit driving domain, and can also be a controller in a power supply of the whole vehicle; the electronic device including the controller may be a vehicle-mounted central controller, a vehicle machine, a power supply system, and the like, and the controller and the electronic device are not limited in the embodiment of the disclosure.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several implementation manners of the embodiments of the present disclosure, and the descriptions thereof are specific and detailed, but cannot be understood as limiting the scope of the utility model patent. It should be noted that various changes and modifications can be made by those skilled in the art without departing from the spirit of the embodiments of the disclosure, and these changes and modifications are all within the scope of the embodiments of the disclosure. Therefore, the protection scope of the patent of the embodiment of the disclosure should be subject to the appended claims.
Claims (13)
1. A chip starting circuit is characterized by comprising a first input end, a second input end, a first output end, a second output end and an enabling circuit, wherein the first input end is connected with a first power supply end arranged outside, the second input end is connected with a second power supply end arranged outside, the first output end is connected with a power supply input end of a power supply chip arranged outside, and the second output end is connected with the enabling end of the power supply chip; the enabling circuit is respectively connected with the second input end and the second output end;
and the enabling circuit is used for controlling the conduction of a second path between the second power supply end and the enabling end of the power supply chip after the first path between the first power supply end and the power supply input end of the power supply chip is conducted.
2. The chip start circuit of claim 1, wherein the enable circuit comprises a first enable circuit and a second enable circuit connected to each other, the first enable circuit further connected to the second power supply terminal, the second enable circuit further connected to the first power supply terminal and the enable terminal of the power chip;
the first enabling circuit is used for being conducted under the driving of the voltage output by the second power supply end and outputting the voltage to the second enabling circuit after being conducted;
the second enabling circuit is used for conducting under the driving of the first enabling circuit and the voltage output by the first power supply end, so that the second path is conducted.
3. The chip start-up circuit of claim 2, wherein the first enable circuit comprises a first transistor, a first resistor and a second resistor;
the base electrode of the first triode is connected with the first end of the first resistor, the collector electrode of the first triode is connected with the second enabling circuit, and the emitting electrode of the first triode is connected with the ground terminal;
the second end of the first resistor is connected with the second power supply end;
the first end of the second resistor is connected with the first end of the first resistor, and the second end of the second resistor is connected with the grounding end.
4. The chip start-up circuit of claim 3, wherein the first enable circuit further comprises a first capacitor;
the first end of the first capacitor is connected with the second power supply end, and the second end of the first capacitor is connected with the grounding end.
5. The chip start-up circuit of claim 2, wherein the second enable circuit comprises a second transistor, a third resistor and a fourth resistor;
the base electrode of the second triode is connected with the first enabling circuit, the collector electrode of the second triode is connected with the first end of the third resistor, and the emitter electrode of the second triode is connected with the first power supply end;
the second end of the third resistor is connected with the enabling end of the power supply chip;
the first end of the fourth resistor is connected with the enable end of the power supply chip, and the second end of the fourth resistor is connected with the ground end.
6. The chip start-up circuit of claim 5, wherein the second enable circuit further comprises a fifth resistor;
the first end of the fifth resistor is connected with the first enabling circuit, and the second end of the fifth resistor is connected with the base electrode of the second triode.
7. The chip start-up circuit of any one of claims 1 to 6, further comprising a filter circuit, wherein the filter circuit is connected to the first power supply terminal and the power supply input terminal of the power supply chip.
8. The chip start-up circuit of claim 7, wherein the filter circuit comprises at least one second capacitor;
the first end of the second capacitor is connected with the power input end of the power supply chip, and the second end of the second capacitor is connected with the grounding end.
9. The chip start-up circuit of claim 7, wherein the filter circuit further comprises a third capacitor;
the first end of the third capacitor is connected with the first power supply end, and the second end of the third capacitor is connected with the grounding end.
10. The chip start-up circuit of claim 7, wherein the filter circuit further comprises a diode;
the anode of the diode is connected with the first power supply end, and the cathode of the diode is connected with the power supply input end of the power supply chip.
11. A controller, characterized in that the controller comprises a power supply chip and a chip start-up circuit according to any one of claims 1 to 10.
12. An electronic device, characterized in that the electronic device comprises a controller according to claim 11.
13. A vehicle characterized in that it comprises an electronic device according to claim 12.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221502651.7U CN217935448U (en) | 2022-06-16 | 2022-06-16 | Chip starting circuit, controller, electronic equipment and vehicle |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221502651.7U CN217935448U (en) | 2022-06-16 | 2022-06-16 | Chip starting circuit, controller, electronic equipment and vehicle |
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| CN217935448U true CN217935448U (en) | 2022-11-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210397053A1 (en) * | 2019-03-13 | 2021-12-23 | HKC Corporation Limited | Display panel static electricity protection device, static electricity protection method, and display device |
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2022
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210397053A1 (en) * | 2019-03-13 | 2021-12-23 | HKC Corporation Limited | Display panel static electricity protection device, static electricity protection method, and display device |
| US11966128B2 (en) * | 2019-03-13 | 2024-04-23 | HKC Corporation Limited | Display panel static electricity protection device, static electricity protection method, and display device |
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