CN217933180U - Memory computing circuit - Google Patents
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- CN217933180U CN217933180U CN202221696231.7U CN202221696231U CN217933180U CN 217933180 U CN217933180 U CN 217933180U CN 202221696231 U CN202221696231 U CN 202221696231U CN 217933180 U CN217933180 U CN 217933180U
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Abstract
The utility model discloses a memory calculation circuit, the circuit includes: the memory cell array is arranged in n rows and n columns; each column includes: the device comprises a plurality of storage units, a digital-time domain pulse signal converter, a charging unit, an analog-to-digital converter and a resetting unit which are connected in parallel; the storage unit is a multi-bit resistance variable storage unit; the digital-time domain pulse signal converter is used for converting the received input operation number into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the charging unit is used for receiving the current flowing through each storage unit to charge so as to obtain a charging voltage and outputting the charging voltage to the analog-to-digital converter; the charging voltage represents the multiplication and addition operation result of n input time domain pulse signals and n storage unit conductance values; the analog-to-digital converter is used for converting the multiplication and addition operation result into a digital code and outputting the digital code; the reset unit is used for discharging the charging voltage of the charging unit to reset the operation period. The utility model discloses can realize the calculation of multibit memory in single memory cell, save area, reduce the consumption.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, what especially relate to is an in-memory computing circuit.
Background
In recent years, with the rapid development of the application of artificial intelligence algorithms, the scale of a neural network is continuously enlarged, model parameters are more and more, and the scale of operation data is more and more huge, so that the data-intensive operation brings huge pressure to a traditional von neumann architecture computer. In the conventional von neumann architecture, computation and storage are separated, data transmission between storage and computation becomes an important factor influencing performance, the computing capability of the current computing module is far developed beyond the speed of data storage in a Memory module, a large amount of resources are consumed for data access in the Memory, and the overhead of frequent Memory access of a processor forms a Memory Wall (Memory Wall). On the other hand, in the specific calculation of the artificial intelligence algorithm, the Power consumption of memory access and data transportation is much higher than that of the actual calculation unit, and under the data-intensive calculation, the Power consumption caused by data transportation and memory access is increased, so that a Power Wall is formed. Therefore, only optimizing the speed and power consumption of the Computing unit is very little effective for the artificial intelligence algorithm running under the von neumann architecture, and In order to overcome the bottleneck of the traditional von neumann architecture "Memory wall" and "power consumption wall", the prior art proposes a method of fusing a Computing unit and a Memory unit into a Memory (CIM), thereby reducing the frequency of accessing the Memory by the Computing unit, increasing the speed and reducing the power consumption.
The Resistive Random Access Memory (RRAM) is a storage medium which has the advantages of non-volatility, low power consumption, small area, compatibility with a CMOS integrated circuit process and the like, and is considered to have the most potential for realizing internal calculation, and the current internal calculation based on the RRAM is mainly realized by a single bit RRAM Memory cell, that is, the RRAM Memory cell only has two states of a High Resistance State (HRS) and a Low Resistance State (LRS) to express 1bit information. If the current memory computing circuit needs to execute multi-bit computation, a plurality of single-bit RRAM storage units are needed to participate in the computation, and a subsequent complex weight recovery circuit is needed to ensure the correctness of the multi-bit computation, so that the occupied area is large, and the computing power consumption is large.
Accordingly, the prior art is yet to be improved and developed.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a memory computing circuit, so as to solve the problems that the memory computing circuit needs to use a plurality of single-bit RRAM storage units to participate in the computation if multi-bit computation is to be performed, and a subsequent complex weight recovery circuit is needed to ensure that the occupied area is large and the computation power consumption is large due to the correctness of the multi-bit computation.
The technical scheme of the utility model as follows:
an in-memory computation circuit, comprising: a memory cell array arranged in n rows and n columns; wherein each column comprises: the device comprises a plurality of storage units, a digital-time domain pulse signal converter, a charging unit, an analog-digital converter and a resetting unit which are connected in parallel; the memory unit is a multi-bit resistance variable memory unit; the magnitude of the conductance value of the storage unit represents the magnitude of the stored neural network weight, and determines the magnitude of the charging current of the charging unit;
the digital-time domain pulse signal converter is connected with the corresponding storage unit and used for converting the received input operation number into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the width of the time domain pulse signal determines the duration of the charging current of the charging unit and is in direct proportion to the size of an input operand;
the charging unit is connected with the storage units and used for receiving current flowing through each storage unit to charge so as to obtain charging voltage and outputting the charging voltage to the analog-to-digital converter; wherein the charging voltage represents a result of multiply-add operation of n input time-domain pulse signals and n memory cell conductance values;
the analog-to-digital converter is connected with the charging unit and used for converting a multiplication and addition operation result into a digital code and outputting the digital code;
the reset unit is connected with the charging unit and used for discharging the charging voltage of the charging unit so as to reset the operation period.
The utility model discloses a further set up, the memory cell includes: the multi-bit resistive random access memory and the first MOS tube are connected; wherein the content of the first and second substances,
one end of the multi-bit resistive random access memory is connected with the source electrode of the first MOS tube, the other end of the multi-bit resistive random access memory is connected with the charging unit, and the multi-bit resistive random access memory is used for storing the weight of the neural network;
the grid electrode of the first MOS tube is connected with the output end connected with the digital-time domain pulse signal converter, and the drain electrode of the first MOS tube is connected with a constant voltage.
The utility model discloses a further set up, the charging unit includes: and one end of the capacitor is respectively connected with the storage unit, the analog-to-digital converter and the reset unit, and the other end of the capacitor is grounded.
The utility model discloses a further setting, the reset unit includes: the drain electrode of the second MOS tube is connected with one end of the charging unit, the grid electrode of the second MOS tube is connected with a reset signal, and the source electrode of the second MOS tube is grounded.
The utility model discloses a further setting, first MOS pipe is N type MOS pipe.
The utility model discloses a further setting, the second MOS pipe is N type MOS pipe.
The utility model discloses a further setting, digit-time domain pulse signal converter with first MOS pipe passes through the word line and connects.
The utility model discloses a further setting, it is a plurality of the first MOS pipe of memory cell passes through the source line and connects.
The utility model discloses a further setting is a plurality of the resistance change formula random access memory of memory cell with connect through the bit line between the charging unit.
The utility model provides a pair of in-memory computing circuit, in-memory computing circuit includes: the memory cell array is arranged in n rows and n columns; wherein each column comprises: the device comprises a plurality of storage units, a digital-time domain pulse signal converter, a charging unit, an analog-to-digital converter and a resetting unit which are connected in parallel; the memory unit is a multi-bit resistance variable memory unit; the magnitude of the conductance value of the storage unit represents the magnitude of the stored neural network weight, and determines the magnitude of the charging current of the charging unit; the digital-time domain pulse signal converter is connected with the corresponding storage unit and used for converting the received input operation number into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the width of the time domain pulse signal determines the duration of the charging current of the charging unit and is in direct proportion to the size of an input operand; the charging unit is connected with the storage units and used for receiving current flowing through each storage unit to charge so as to obtain charging voltage and outputting the charging voltage to the analog-to-digital converter; wherein the charging voltage represents a result of multiply-add operation of n input time-domain pulse signals and n memory cell conductance values; the analog-to-digital converter is connected with the charging unit and used for converting a multiplication and addition operation result into a digital code and outputting the digital code; the reset unit is connected with the charging unit and used for discharging the charging voltage of the charging unit so as to reset the operation period. The utility model provides a storage element is used for saving neural network's weight, and the size of the neural network weight of storage element's conductance value represents the size of the storage, and decide the charging current's of charging unit size, digit-time domain pulse signal converter exports to storage element after being converted into time domain pulse signal by digital code with the input operand of receiving, time domain pulse signal who comes when digit-time domain pulse converter output, storage element is in the on-state, the electric current flows through a plurality of parallelly connected storage element, and charge to the charging unit, the charging voltage of charging unit no longer increases after a calculation cycle finishes, charging voltage this moment represents the time domain pulse signal of n inputs and the multiplication operation result of n storage element 100 conductance values. And then, converting the multiplication and addition operation result into a digital code through an analog-to-digital converter and outputting the digital code to a subsequent processing unit to obtain a calculation result. After one period is finished, the reset signal is set to be high level to discharge the charging unit, and after the charging unit discharges to 0 again, the start of the next period can be waited. And the storage units of the storage unit array share the input time domain pulse signal, and the n output analog-to-digital converters output n multiplication and addition operation results, so that the memory calculation result of the storage unit array can be obtained. Therefore, the utility model discloses need not the memory cell of a plurality of single bits and participate in the operation, can realize the internal calculation of multibit memory in single memory cell to saved subsequent weight recovery circuit, saved area, reduced the consumption.
Drawings
In order to clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following descriptions are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of a single row of functional blocks in a memory cell array of the in-memory computing circuit of the present invention.
Fig. 2 is a schematic circuit diagram of a memory cell array in the memory cell computing circuit of the present invention.
Fig. 3 is a time domain waveform diagram of the correlation signal when n equals 3 in the memory computing circuit of the present invention.
Fig. 4 is a schematic circuit diagram of a memory cell array of n rows and n columns in the present invention.
Fig. 5 is a flow chart of the memory computing method according to the present invention.
The various symbols in the drawings: 100. a storage unit; 200. a digital-to-time domain pulse signal converter; 300. a charging unit; 400. an analog-to-digital converter; 500. the cell is reset.
Detailed Description
The utility model provides an in-memory calculating circuit for the operation of multiplying And adding (MAC) that realize in the artificial intelligence algorithm inessential And frequent use. In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention will be described in further detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
In the embodiments and claims, the articles "a", "an", "the" and "the" may include plural forms as well, unless the context specifically dictates otherwise. If there is a description in an embodiment of the present invention referring to "first", "second", etc., the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory to each other or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
Referring to fig. 1 to 4, the present invention provides a preferred embodiment of a memory computing circuit.
As shown in fig. 1 to 4, the present invention provides a memory computing circuit, which includes: the memory cell array is arranged in n rows and n columns; wherein each column comprises: a plurality of memory units 100, a Digital to Time Converter (DTC) 200, a charging unit 300, an Analog to Digital Converter (ADC) 400, and a reset unit 500 connected in parallel; the memory unit 100 is a multi-bit resistive random access memory unit and can execute analog multiplication; the digital-to-time domain pulse signal converter 200 is connected corresponding to the storage unit 100, and is configured to convert the received input operands into time domain pulse signals and output the time domain pulse signals to the storage unit 100; the width of the time domain pulse signal determines the duration of the charging current of the charging unit 300, and is in direct proportion to the magnitude of the input operand; the charging unit 300 is connected to the storage units 100, and is configured to receive the current flowing through each storage unit 100 to perform charging so as to obtain a charging voltage and output the charging voltage to the analog-to-digital converter 400; wherein the charging voltage represents a result of a multiply-add operation of n input time-domain pulse signals and n conductance values of the memory cell 100; the analog-to-digital converter 400 is connected to the charging unit 300, and is configured to convert the result of the multiply-add operation into a digital code and output the digital code; the reset unit 500 is connected to the charging unit 300, and is configured to discharge the charging voltage of the charging unit 300 to reset an operation cycle.
Specifically, the memory cells 100 in each row of the array of memory cells 100 in each column are connected to the digital-to-time domain pulse signal converter 200, and the digital-to-time domain pulse signal converter 200 converts the received input operand from a digital code into a time domain pulse signal (t 1, t2.. Tn) and outputs the time domain pulse signal to the memory cells 100, so that the time domain pulse signal can control the current on-time of the memory cells 100 because the width of the time domain pulse signal is proportional to the size of the input operand.
When the time domain pulse signal output by the digital-to-time domain pulse converter 200 comes, the storage unit 100 is in a conducting state, current flows through the plurality of storage units 100 connected in parallel, the charging unit 300 is charged, and after a calculation cycle is finished, the charging voltage of the charging unit 300 is not increased any more, and at this time, the charging voltage represents the multiplication and addition operation result of the n input time domain pulse signals and the n storage unit 100 conductance values. And then, the multiplication and addition operation result is converted into a digital code through the analog-to-digital converter 400 and then output to a subsequent processing unit to obtain a calculation result. After one period is finished, the reset signal is set to high level to discharge the charging unit 300, and after the charging unit 300 discharges to 0 again, the start of the next period can be waited. The memory cells 100 of the memory cell array share the input time domain pulse signal, and the n output analog-to-digital converters 400 output n multiplication and addition operation results, so as to obtain the memory calculation result of the memory cell array. Therefore, the utility model discloses need not the memory cell of a plurality of single bits and participate in the operation, can realize the internal calculation of multibit memory in single memory cell to saved subsequent weight recovery circuit, saved area, reduced the consumption.
Referring to fig. 2, in some embodiments, the memory cell 100 includes: the charging unit 300 includes a multi-bit resistive random access memory (for example, the multi-bit resistive random access memory in the first column of memory cells is R11, R12.. R1N) and a first MOS transistor (N11, N12.. N1N), the multi-bit resistive random access memory and the first MOS transistor form a 1t1r cell, the first MOS transistor is an N-type MOS transistor, one end of the multi-bit resistive random access memory is connected to a source of the first MOS transistor, the other end of the multi-bit resistive random access memory is connected to the charging unit 300, the multi-bit resistive random access memory is configured to store weights of a neural network, and a magnitude of a conductivity value of the memory unit 100 indicates a magnitude of the stored weights of the neural network, and determines a magnitude of a charging current of the charging unit 300. The gate of the first MOS transistor is connected to the output end of the digital-to-time domain pulse signal converter 200, and the drain of the first MOS transistor is connected to a constant voltage Vs. The first MOS transistors of the memory cells 100 are connected together through a Source Line (SL) to access a constant voltage Vs through the Source Line SL, the first MOS transistors are connected together with the time domain pulse signal converter through Word Lines (WL), the multi-Bit resistive random access memory is connected together through Bit lines (Bit lines, BL), and the charging unit 300 can be charged by a current flowing through the multi-Bit resistive random access memory through the Bit lines BL.
Referring to fig. 2 and 4, the resistance random access memories (R11, R12.. R1N) in the first row are connected by a bit line BL1, the first MOS transistors (N11, N12.. N1N) in the first row are connected by a source line SL1, the resistance random access memories (R21, R22.. R2N) in the second row are connected by a bit line BL2, the first MOS transistors (N21, N22.. N2N) in the second row are connected by a source line SL2, the resistance random access memories (Rn 1, R32.. Rnn) in the nth row are connected by a bit line BLn, the first MOS transistors (Nn 1, N2.. Nnn) in the third row are connected by a source line SLn, the memory cells in each row of the memory cell array are connected by a word line WL, the input time domain pulse signals are shared, and the N output analog-to-digital converters 400 output N multiplication and addition operation results, that are the results in the memory cell array.
It is visible, the utility model discloses a multiseriate n memory cell 100 shares n word line WL and connects at first MOS pipe grid terminal, the operation array of n row of final constitution, this array has a plurality of different multibit resistance variable random access memory of nxn, can save the weight of a plurality of neural network of nxn, multiply and add the calculation that can accomplish a nxn's matrix and an n dimension vector multiplication with a plurality of time domain pulse signal of input again mutually, need not the memory cell 100 of a plurality of single bits and participate in the operation, can realize the calculation in the multibit deposit in single memory cell 100, the occupation area is saved, and subsequent weight recovery circuit has been saved, complexity and consumption have been reduced, the memory density has been improved.
Referring to fig. 2, in a further implementation manner of an embodiment, the charging unit 300 includes: capacitor C BL Said capacitor C BL Is connected to the memory unit 100, the analog-to-digital converter 400 and the reset unit 500, respectively, and the capacitor C BL And the other end of the same is grounded.
In particular, the capacitance C BL The capacitor C is connected to the end of the bit line BL BL And one end of the reset unit is connected to the resistive random access memory, the analog-to-digital converter 400, and the reset unit 500. Referring to FIG. 3, the capacitance C is measured at the beginning of a calculation cycle BL Voltage V of BL =0, then when the input time domain pulse signal arrives, the first MOS transistor in the 1T1R unit (memory cell) is turned on, the current flows through the plurality of resistive random access memories RRAM connected in parallel, and finally is collected to the capacitor C BL Sum of the added currents to the capacitance C BL Charging and raising the capacitor C BL Voltage of, capacitor C after one calculation cycle is over BL Is no longer increasing, at which time the voltage (i.e., the charging voltage V) is BL ) The method can represent the multiplication and addition operation result of n input time domain pulse signals and n resistance random access memory conductance values. The relevant mathematical relationship is derived as follows:
assuming that the widths of the n input time domain pulse signal signals are T1, T2.. Tn, respectively, the current flowing through the kth 1T1R unit can be expressed as:
wherein u (t) =1,t > 0, is a unit step function.
Then the capacitance C BL The charging current of (a) is the sum of the currents flowing through the n 1T1R cells connected in parallel:
on the other hand, the charging current of the capacitor meets the following conditions:
thus establishing a first order linear differential equation:
wherein C is a capacitor C BL Accommodating of (A), R k For the resistance value of the resistance change random access memory, solving the first-order linear differential equation to obtain the end time (t > max { t) of the input time domain pulse signal 1 ,t 2 ,...t n }) capacitance C BL The voltages on are:
in the above formula V BL Is a capacitor C BL Upper final voltage level, vs is the voltage on the source line SL, C BL Is a capacitor C BL The capacitance value is obtained by the formula, namely n input time domain pulses (the pulse width is t) 1 ,t 2 ,...,t n ) And n resistance random access memory conductance values (G) 1 ,G 2 ,...,G n ) MAC operation between, the final result of multiply-add operation is capacitance C BL Upper voltage value V BL Is divided byA coefficient of
Referring to fig. 2, in a further implementation of an embodiment, the reset unit 500 includes: a second MOS transistor M1, a drain electrode of the second MOS transistor M1 and the capacitor C BL The gate of the second MOS transistor M1 is connected to a Reset signal BL _ Reset, and the source of the second MOS transistor M1 is grounded.
Specifically, the second MOS transistor M1 is an N-type MOS transistor. Said capacitor C in each operation cycle BL Charging is started when the voltage is 0, and the capacitor C is charged after the operation is finished BL The voltage on the voltage is converted into a digital code through an output digital-to-analog conversion unit ADC and the result of a row of multiply-add operation is output. When a calculation period is finished, the Reset signal BL _ Reset is changed into high level, so that the second MOS tube M1 is conducted, and the capacitor C is connected BL To 0 to wait for the start of the next calculation cycle.
Referring to fig. 4, it can be understood that the multiplication and addition operation of the memory cell array arranged in n rows and n columns is an extension of the multiplication and addition operation of the memory cell array in one column, word lines of the memory cells in each column share the input time domain pulse signal, n output analog-to-digital converters 400 output n multiplication and addition operation results, and the memory cell array arranged in n rows and n columns can implement the following matrix and vector multiplication operation:
in the above equation, the result to the right of the equation is from a single V BL The values extending to a column of vectors V BL1 ，V BL2 ，V BL3 ...，V BLn ] T The calculation process is consistent with the principle of the single-column calculation process, and is not described herein again.
Referring to fig. 5, to better understand the present invention, the present invention further provides a memory computing method applied to the memory computing circuit, which includes the steps of:
s100, receiving an input operand and converting the input operand into a time domain pulse signal by a digital-time domain pulse signal converter and outputting the time domain pulse signal to a storage unit; the width of the time domain pulse signal determines the duration of the charging current of the charging unit and is in direct proportion to the size of the input operand; as described in an embodiment of a memory computing circuit, details are not repeated herein.
S200, the charging unit receives the current flowing through each storage unit to obtain a charging voltage and outputs the charging voltage to the analog-to-digital converter; wherein the charging voltage represents a result of multiply-add operation of n input time-domain pulse signals and n memory cell conductance values; as described in an embodiment of the memory computing circuit, details are not repeated herein.
S300, the analog-to-digital converter obtains and outputs a digital code according to the multiplication and addition operation result; as described in an embodiment of a memory computing circuit, details are not repeated herein.
S400, the reset unit receives a reset signal and carries out discharge processing on the charging unit according to the reset signal so as to reset an operation period. As described in an embodiment of the memory computing circuit, details are not repeated herein.
To sum up, the utility model provides a memory computing circuit, memory computing circuit includes: the memory cell array is arranged in n rows and n columns; wherein each column comprises: the device comprises a plurality of storage units, a digital-time domain pulse signal converter, a charging unit, an analog-to-digital converter and a resetting unit which are connected in parallel; the memory unit is a multi-bit resistance variable memory unit; the magnitude of the conductance value of the storage unit represents the magnitude of the stored neural network weight, and determines the magnitude of the charging current of the charging unit; the digital-time domain pulse signal converter is connected with the corresponding storage unit and used for converting the received input operation number into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the width of the time domain pulse signal determines the duration of the charging current of the charging unit and is in direct proportion to the size of an input operand; the charging unit is connected with the storage units and used for receiving current flowing through each storage unit to charge so as to obtain charging voltage and outputting the charging voltage to the analog-to-digital converter; wherein the charging voltage represents a result of multiply-add operation of n input time-domain pulse signals and n memory cell conductance values; the analog-to-digital converter is connected with the charging unit and used for converting a multiplication and addition operation result into a digital code and outputting the digital code; the reset unit is connected with the charging unit and used for discharging the charging voltage of the charging unit so as to reset the operation period. The utility model discloses need not the memory cell of a plurality of single bits and participating in the operation, can realize the internal calculation of many bits in single memory cell to saved subsequent weight recovery circuit, saved area occupied, and saved subsequent weight recovery circuit, reduced complexity and consumption, improved storage density.
It is to be understood that the invention is not limited to the above-described embodiments, and that modifications and variations may be made by those skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.
Claims (9)
1. An in-memory computation circuit, comprising: a memory cell array arranged in n rows and n columns; wherein each column comprises: the device comprises a plurality of storage units, a digital-time domain pulse signal converter, a charging unit, an analog-digital converter and a resetting unit which are connected in parallel; the memory unit is a multi-bit resistance variable memory unit; the magnitude of the conductance value of the storage unit represents the magnitude of the stored neural network weight, and determines the magnitude of the charging current of the charging unit;
the digital-time domain pulse signal converter is connected with the corresponding storage unit and used for converting the received input operation number into a time domain pulse signal and outputting the time domain pulse signal to the storage unit; the width of the time domain pulse signal determines the duration of the charging current of the charging unit and is in direct proportion to the size of an input operand;
the charging unit is connected with the storage units and used for receiving current flowing through each storage unit to charge so as to obtain charging voltage and outputting the charging voltage to the analog-to-digital converter; wherein the charging voltage represents a result of multiply-add operation of n input time-domain pulse signals and n memory cell conductance values;
the analog-to-digital converter is connected with the charging unit and used for converting a multiplication and addition operation result into a digital code and outputting the digital code;
the reset unit is connected with the charging unit and used for discharging the charging voltage of the charging unit so as to reset the operation period.
2. The in-memory computing circuit of claim 1, wherein the storage unit comprises: the multi-bit resistive random access memory and the first MOS tube are connected; wherein, the first and the second end of the pipe are connected with each other,
one end of the multi-bit resistive random access memory is connected with the source electrode of the first MOS tube, the other end of the multi-bit resistive random access memory is connected with the charging unit, and the multi-bit resistive random access memory is used for storing the weight of the neural network;
the grid electrode of the first MOS tube is connected with the output end of the digital-time domain pulse signal converter, and the drain electrode of the first MOS tube is connected with a constant voltage.
3. The memory computing circuit of claim 1, wherein the charging unit comprises: and one end of the capacitor is respectively connected with the storage unit, the analog-to-digital converter and the reset unit, and the other end of the capacitor is grounded.
4. The in-memory computing circuit of claim 1, wherein the reset unit comprises: the drain electrode of the second MOS tube is connected with one end of the charging unit, the grid electrode of the second MOS tube is connected with a reset signal, and the source electrode of the second MOS tube is grounded.
5. The memory computing circuit of claim 2, wherein the first MOS transistor is an N-type MOS transistor.
6. The memory computing circuit of claim 4, wherein the second MOS transistor is an N-type MOS transistor.
7. The memory computing circuit of claim 2, wherein the digital-to-time domain pulse signal converter is connected to the first MOS transistor by a word line.
8. The memory computing circuit of claim 2, wherein the first MOS transistors of a number of the memory cells are connected by a source line.
9. The memory computing circuit of claim 2, wherein the resistive random access memory of the plurality of memory cells is connected to the charging unit via a bit line.
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