CN217903108U - Chip packaging substrate with high air tightness and high reliability - Google Patents
Chip packaging substrate with high air tightness and high reliability Download PDFInfo
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- CN217903108U CN217903108U CN202221870786.9U CN202221870786U CN217903108U CN 217903108 U CN217903108 U CN 217903108U CN 202221870786 U CN202221870786 U CN 202221870786U CN 217903108 U CN217903108 U CN 217903108U
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- support
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- dielectric layer
- reliability
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A chip packaging substrate with high air tightness and high reliability comprises printing ink arranged around at least the edge of a single packaging unit, a copper layer circuit formed by etching is arranged on the surface of a support circuit board of the single packaging unit, the single packaging unit is of a common-hole or single-hole structure, a dielectric layer is fixed around the edge of the support through a thermosetting process, the printing ink is arranged around the edge of the support, and a dam structure with a horizontal plane is formed after high-temperature curing gradually increased at 65-165 ℃.
Description
Technical Field
The utility model relates to a chip package field specifically is a chip package substrate of high gas tightness high reliability.
Background
The existing semiconductor chip packaging bracket applied to the LED or the sensor has the following two common technologies;
technique 1: taking an LED single support as an example, as shown in fig. 1 and fig. 2, fig. 1 is a top view, fig. 2 is a side view, which illustrates a circuit board of the support formed with a copper material 2' by etching, conductive portions connected to the circuit in the support are provided at four corners of the single support, the conductive portions are provided with a common hole structure 3' that can be shared with other multiple supports, copper is filled in the common hole structure 3', so that the circuit of the copper material 2' on the upper surface of the support can be electrically connected with the copper material 2' at the bottom of the support, a wafer 4' is welded on the circuit of the copper material 2' after the processes of fixing gold and bonding wire on the support, electrical connection is formed in the circuit board through a bonding wire 41' welded between the copper layers, and then the surface of the support is encapsulated and protected by pouring resin 1 ';
the advantages are that: the bracket has simple process and low production cost, but has the problems of short service life and low durability due to poor air tightness;
the disadvantages are as follows: the positions around the edge of the bracket are the bracket base material and the copper material 2', the subsequent poor combination with the resin 1' causes poor air tightness at the combination positions of different materials around the edge, water vapor easily enters from the positions with poor air tightness, and the water vapor can cause the electric leakage of adjacent circuits to cause electron migration, so that the product is scrapped and has poor reliability;
and (2) a technology: in order to solve the problem of short service life caused by poor air tightness of the product in the technology 1, as shown in fig. 3 and fig. 4, fig. 3 is a top view, fig. 4 is a side view, and a cup-type chip packaging support (see patent CN 202220156188.9) is improved and designed, an optical cup 5' is tightly pressed on a circuit board support through vacuum hot pressing, copper materials 2' on the circuit board are well combined with the optical cup 5', and resin 1' is poured into a cup of the optical cup 5' to completely seal and protect the surface of the circuit board of the support;
the advantages are that: the air-tightness is good, the performance is stable, and the reliability is high;
the disadvantages are as follows: the bracket manufacturing process is complex and the production cost is high.
It should be noted that, the supports in the above two technologies all adopt a common-hole design, a plurality of single support circuits are formed on a whole support plate through etching, the whole support plate is punched according to actual needs, the finished product is a single or multiple integrated circuit board support, the punching part is a common-hole connecting part of several adjacent single circuits, the process of punching a conductive hole at the position of the corresponding circuit on the back of each single support is reduced, and the production cost is reduced, so that the support adopting the common-hole design is frequently used at present.
It is also noted that fig. 1 and 2 are a top view and a side view of a product manufactured by corresponding methods, but for clarity of explanation, the two figures are not in corresponding relation, and fig. 3 and 4 are the same.
SUMMERY OF THE UTILITY MODEL
The utility model discloses main aim at provides a chip package substrate of high gas tightness high reliability to solve the problem of mentioning in the background art.
In order to achieve the above object, the utility model provides a following technical scheme:
a chip packaging substrate with high air tightness and high reliability comprises a dielectric layer arranged on the periphery of at least one edge of a single packaging unit, a copper layer circuit formed by etching is arranged on the surface of a support circuit board of the single packaging unit, a copper layer in the single packaging unit is provided with a common hole structure which can be electrically conducted with a plurality of chip supports in a shared mode, or a single hole structure which corresponds to the position of the copper layer circuit and is used for conducting is arranged at the bottom of the single packaging unit, and the dielectric layer is fixed on the periphery of the edge of the support through a thermosetting process.
The utility model has the advantages that:
the method is characterized in that a dielectric layer is arranged on the periphery of the edge of a support, a dam structure with a horizontal plane is formed after the dielectric layer is solidified at a high temperature of 65-165 ℃ in a gradual increasing mode, the dielectric layer naturally flows on the surface of the support, the dielectric layer is solidified and formed through high-temperature thermosetting treatment, the dielectric layer, a copper layer and a support substrate are combined well, the air tightness is good, when the method is applied to an actual chip packaging process, epoxy resin is filled on the surface of a support circuit board in a packaging mode, the epoxy resin is fixedly sealed on the periphery of the edge of a single support through the dielectric layer, and the dielectric layer, the copper layer, the support substrate and the epoxy resin are combined well, so that the dielectric layer is combined well on the periphery of the edge of the support, the air tightness is good, a permeation path can be stopped, the problem of circuit board electronic migration caused by water vapor is solved, the reliability is greatly improved, the service life of the support is prolonged, the manufacturing process is simple, the production cost is low, the application fields are multiple, the advantages of two packaging supports in the background technology are achieved, the defects of the two packaging supports are avoided, and the method is suitable for popularization.
Other features and advantages of the present invention will be described in detail in the detailed description which follows.
Drawings
Fig. 1 is a top view of prior art 1.
Fig. 2 is a side view of prior art 1.
Fig. 3 is a top view of prior art 2.
Fig. 4 is a side view of prior art 2.
Fig. 5 is a top view of the first embodiment of the present invention.
Fig. 6 is a side view of the first embodiment of the present invention.
Fig. 7 is a side sectional view of a first embodiment of the present invention.
Fig. 8 is a plan view of the second embodiment of the present invention.
The parts in the drawings are numbered as follows: 1' -a resin; 2' -copper material; a 3' -common pore structure; 4' -a wafer; 41' -binding line; 5' -light cup; 1-epoxy resin; 2-a copper layer; 3-co-pore; 4-chip; 41-gold wire; 6-dielectric layer.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
In order to solve the problem that the gas tightness is poor and the processing cost is high that exist respectively among the two kinds of current packaging technique, the utility model provides a chip packaging substrate of high gas tightness high reliability.
The first embodiment is as follows: the utility model provides a chip package substrate of high gas tightness high reliability, includes that single encapsulation unit is at least marginal dielectric layer 6 that is equipped with all around, the support circuit board surface of single encapsulation unit is equipped with the copper layer 2 circuit that the etching formed, copper layer 2 in single encapsulation unit is equipped with and can shares electrically conductive 3 structures in hole altogether with a plurality of chip support, perhaps single encapsulation unit's bottom is equipped with and corresponds with copper layer 2 circuit position and be used for electrically conductive sole hole structure, dielectric layer 6 is fixed around the support edge through thermosetting technology, and no matter single chip support is hole altogether or sole hole, has or not copper product all around the support edge, and dielectric layer 6 all fixes around the support edge.
It is noted that the single package unit in the present embodiment is a single chip holder, and the single chip holder is suitable for a low-power LED lamp, and the side length of the single chip holder is between 1mm and 2 mm.
As shown in fig. 5 and 6, in the manufacturing process of the bracket, the dielectric layer 6 is formed around the edge of a single bracket, and after the dielectric layer 6 is cured at a high temperature of 65 ℃ to 165 ℃ in a gradually increasing manner, a dam structure with a horizontal plane is formed, the dielectric layer 6 in the embodiment adopts hole plugging resin ink, the dielectric layer 6 is coated around the edge of the single chip bracket through a printing process, the dielectric layer 6 naturally flows, and the dielectric layer 6 is solidified and formed through high-temperature thermosetting treatment, when the bracket in the embodiment is applied to an actual chip packaging process, the chip 4 is welded on a bracket copper layer 2 through a gold fixing and wire bonding process, electric connection is formed in a circuit board through a gold wire 41 welded among copper layer circuits, the periphery of the circuit is provided with a common hole 3 structure which can share electric conduction with a plurality of brackets, the surface of the bracket circuit board is filled with epoxy resin 1, at the moment, the epoxy resin 1 seals and isolates the chip 4, the gold wire 41 and the copper layer 2 on the circuit board from the outside, the epoxy resin 1 is fixedly sealed and sealed at the periphery of the edge of the single bracket through the dielectric layer 6, and the dielectric layer 6 is suitable for being applied to the semiconductor bracket, thereby greatly improving the reliability of the semiconductor bracket, and being suitable for being applied to the semiconductor bracket, and being applicable to the semiconductor bracket.
In addition, there is a single chip support with single hole design, and its conductive connection hole is set on the back of the chip support, that is, the welding point of the conductive connection line is set on the back of the circuit board, and it does not share one connection hole with other chip supports.
It should be noted that, in this embodiment, the main component of the resin-filled ink used for the dielectric layer 6 is resin, which has the functions of adhesion and hole plugging, the resin-filled ink is coated on the periphery of the edge of the bracket, the epoxy resin 1 used for encapsulation is adhered and fixed to the periphery of the edge of the bracket in the process of bracket encapsulation, the curing of the resin-filled ink starts from 65 ℃, the temperature of the ink increases at most not more than 165 ℃ after a period of time, and after a total of several hours of high-temperature curing, the bonding property of the resin-filled ink and the bracket is good, the type of the epoxy resin 1 is electric 6688 one-component epoxy resin glue, the main components of the dielectric layer 6 and the epoxy resin 1 are both resin, the mutual bonding property is good, and the ink can fill the surface gap of at least the substrate part (possibly including the copper layer) around the edge of the bracket to play a role of hole plugging, and the bonding property of the ink and the copper layer 2, the bracket substrate and the epoxy resin 1 is very good, so that the air tightness at the periphery of the edge of the bracket is good, and the reliability is high.
In the following description of the dam structure, when the thickness of the copper layer 2 of the circuit on the upper surface of the bracket is higher, there may be a fall between the dam on the copper layer and the dam on the substrate, and the dam with a horizontal plane is not the same as the dam on the same horizontal plane, but the dam is formed in the horizontal direction.
It should be noted that fig. 5 and 6 are a top view and a side view of the single stent in the present embodiment, and fig. 7 is a side view of a middle cross-sectional surface of the single stent, which are not corresponding to each other for clarity of explanation.
The following explains why the service life of a product is reduced due to the air tightness difference caused by the poor bonding property of the epoxy resin 1, the bracket substrate and the copper layer 2 in the prior art, because the copper in the copper layer 2, the fiber layer in the bracket substrate and the epoxy resin 1 are different molecular structure materials with large differences, and the molecular gaps are different, the surface roughness of the fiber layer and the epoxy resin is different, so that water vapor enters the bonding parts, and the bonding parts have different surface roughness, and the water vapor enters the interior from the small gaps due to different thermal expansion coefficients and different degrees of expansion and contraction of the two materials under different temperature environments, so that the bonding parts of the two materials generate small gaps, the water vapor enters the interior from the small gaps, such as single particles and tiny chips of an LED (light emitting diode) in an LED screen commonly seen in daily life, the distance between circuits on an internal circuit board is generally in a micron unit, once the water vapor causes the electron migration of adjacent circuits, the original circuits are disconnected or abnormally connected, the connection is abnormal connection, the electron migration rate is accelerated by high temperature, and the service life of the LED lamp bead with poor air tightness is greatly influenced.
In this embodiment, the dielectric layer 6 may also be completely covered on the surface of a single support circuit board, and then the area to be soldered or bonded on the circuit board may be subjected to windowing in the subsequent process.
Example two: as shown in fig. 8, a single package unit is an all-in-one support formed by a plurality of chip supports in a rectangular array, in this embodiment, a dielectric layer 6 is fixed around the edge of each support in the all-in-one support, and is cured at a high temperature of 65 ℃ to 165 ℃ gradually and gradually to form a protective enclosure dam, so that the air tightness of each support in the all-in-one support is enhanced, the reliability is better, the sealing effect is the same as that of the first embodiment, other features are the same as that of the first embodiment, and details are not repeated here.
This embodiment can also form the box dam with the fixed setting of dielectric layer 6 at the holistic all around edge of unification support more, the box dam can all surround every single support in the unification support more, pours epoxy 1 into to the support surface again and forms the isolation protection layer, strengthens the holistic gas tightness of unification support more, promotes product reliability.
It should be noted that, the filling surface of the circuit board is designed with no or few conductive connecting lines between the interiors, and the epoxy resin 1 and the copper surface 2 have poor bonding property, so that the reduction of the bonding between the epoxy resin 1 and the copper surface is beneficial to improving the overall bonding force and increasing the reliability.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may include only a single embodiment, and such description is for clarity only, and those skilled in the art will be able to make the description as a whole, and the embodiments may be appropriately combined to form other embodiments as will be apparent to those skilled in the art.
Claims (9)
1. The utility model provides a chip package substrate of high gas tightness high reliability which characterized in that: the packaging structure comprises a dielectric layer (6) arranged on the periphery of at least one edge of a single packaging unit, a copper layer (2) circuit formed by etching is arranged on the surface of a support circuit board of the single packaging unit, a copper layer (2) in the single packaging unit is provided with a common hole (3) structure which can be electrically conducted with a plurality of chip supports in a shared mode, or a single hole structure which corresponds to the position of the copper layer (2) circuit and is used for conducting is arranged at the bottom of the single packaging unit, and the dielectric layer (6) is fixed on the periphery of the edge of the support through a thermosetting process.
2. The substrate for chip package with high airtightness and high reliability as claimed in claim 1, wherein: the single packaging unit is a single chip support.
3. The high-reliability chip package substrate with high airtightness according to claim 1, wherein: the single packaging unit is an all-in-one support formed by a plurality of chip support rectangular arrays.
4. The high-reliability chip package substrate with high airtightness according to claim 2 or 3, wherein: and the dielectric layer (6) is cured at a high temperature of 65-165 ℃ which is gradually increased, and then a dam with a horizontal plane is formed around the edge of the single chip support.
5. The high-reliability chip package substrate with high airtightness according to claim 4, wherein: the chip (4) is welded on the copper layer (2), electric connection is formed in the circuit board through gold wires (41) welded among the copper layers (2), a common hole (3) structure which can be electrically connected with a plurality of chip supports in a shared mode is arranged on the periphery of the circuit of the copper layer (2), epoxy resin (1) is filled on the surface of the circuit board of the support, and the epoxy resin (1) is sealed with the dielectric layer (6) on the periphery of the edge of a single chip support and the upper surface of the support.
6. The high-reliability chip package substrate with high airtightness according to claim 2 or 3, wherein: and the dielectric layer (6) is completely covered on the surface of the single bracket circuit board after being cured at the high temperature of 65-165 ℃ which is gradually increased, and the area which needs to be welded or bonded is subjected to windowing treatment.
7. The high-reliability chip package substrate with high airtightness according to claim 2 or 3, wherein: and the bottom of the single packaging unit is provided with a single-hole structure which corresponds to the line position of the copper layer (2) and is used for conducting electricity.
8. The high-reliability chip package substrate with high airtightness according to claim 3, wherein: the whole periphery of the all-in-one support is fixed with a dielectric layer (6).
9. The high-reliability chip package substrate with high airtightness according to claim 5, wherein: the dielectric layer (6) is plug hole resin ink, and the type of the epoxy resin (1) is electric 6688 single-component epoxy resin glue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221870786.9U CN217903108U (en) | 2022-07-11 | 2022-07-11 | Chip packaging substrate with high air tightness and high reliability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221870786.9U CN217903108U (en) | 2022-07-11 | 2022-07-11 | Chip packaging substrate with high air tightness and high reliability |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217903108U true CN217903108U (en) | 2022-11-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221870786.9U Active CN217903108U (en) | 2022-07-11 | 2022-07-11 | Chip packaging substrate with high air tightness and high reliability |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217903108U (en) |
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2022
- 2022-07-11 CN CN202221870786.9U patent/CN217903108U/en active Active
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