CN217902291U

CN217902291U - Power supply sequential control circuit

Info

Publication number: CN217902291U
Application number: CN202222006585.0U
Authority: CN
Inventors: 蔡舒宏
Original assignee: Nanjing Xinning Optoelectronic Technology Co ltd
Current assignee: Nanjing Xinning Optoelectronic Technology Co ltd
Priority date: 2022-04-22
Filing date: 2022-08-01
Publication date: 2022-11-25
Anticipated expiration: 2032-08-01

Abstract

The utility model provides a power supply time sequence control circuit. The power supply timing control circuit includes: a power supply time sequence control chip U1 (1), a power supply conversion chip U2 (2) and a circuit switch SW1 (3); the power supply conversion chip U2 (2) comprises a VDD _ EN port, and the power supply conversion chip U2 (2) is connected with an input Voltage (VDD) through the VDD _ EN port; the power supply time sequence control chip U1 (1) comprises a power supply Voltage (VCC), a pin (EN), a secondary ground wire (GND), a first state Flag register (Flag 1) and a second state Flag register (Flag 2); the power conversion chip U2 (2) is connected with the second state Flag register (Flag 2) through a first lead. The utility model provides a power supply time sequence control circuit compares and hangs 2 power conversion chip's scheme under power supply time sequence control chip, replaces one of them power supply chip with SW1 now, has reached same purpose, has nevertheless saved design cost's advantage.

Description

Power supply sequential control circuit

Technical Field

The utility model belongs to the technical field of power supply time sequence control circuit, especially, relate to a power supply time sequence control circuit.

Background

Following a specific power-up sequence and a specific power-down sequence is one of the principles that an electric product needs to be ensured, so that the product can normally and reliably operate. Based on the above, a power timing control chip, such as LM3880 of TI (TEXAS INSTRUMENTS), can set a threshold voltage through an external voltage dividing resistor, and is used for tracking the change of an input power, and accordingly, the output flag1 and the output flag2 are used for controlling the on or off of the power conversion chip. According to the type selection, the flag1 outputs an enable signal before the flag2 to drive the output voltage of the down-hung power conversion chip when power is on, and the flag1 lags behind a flag2 off enable signal when power is off so as to turn off the down-hung power conversion chip, in the related technology, a power timing control circuit is disclosed, which comprises an active power factor correction circuit, a timing controller and a power converter, wherein the timing controller is formed by connecting a voltage stabilizing diode ZD2 and a resistor R20 in series, and one end of the timing controller is connected to the power output end of the active power factor correction circuit; the power supply input end of the power supply converter is connected with the power supply output end of the active power factor correction circuit, the power supply converter is provided with a control chip U2, the U2 is provided with a voltage starting pin V1, and the time schedule controller is connected to the voltage starting pin V1 of the U2. The utility model discloses circuit structure is simple, with low costs, and practicality and reliability are very high moreover.

However, the above structure has disadvantages that after the electronic device is usually connected to an external power adapter to provide voltage VCC _ IN for power supply, the electronic device generates VDD through a power conversion chip and provides VDD for a small system, however, for the timing requirement that VDD is powered down before VCC _ IN, it is difficult for the power supply to be VCC _ IN, IN the prior art, after the power timing control chip, except for the VDD power conversion chip required for hanging down, a power conversion chip is added to output voltage VCC _ IN and the like as VCC _ OUT, and the power conversion chip is controlled to be turned on or turned off through the output of the power timing control chip, which increases design cost and complexity.

Therefore, it is necessary to provide a new power timing control circuit to solve the above technical problems.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem provide a compare in the scheme of hanging 2 power conversion chips under power time sequence control chip, replace one of them power chip with SW1 now, reached same purpose, nevertheless saved design cost's power time sequence control circuit.

In order to solve the above technical problem, the utility model provides a power supply sequential control circuit includes: the power supply time sequence control chip U1 (1), the power supply conversion chip U2 (2) and the circuit switch SW1 (3);

the power supply conversion chip U2 (2) comprises a VDD _ EN port, and the power supply conversion chip U2 (2) is connected with an input Voltage (VDD) through the VDD _ EN port;

the power supply time sequence control chip U1 (1) comprises a power supply Voltage (VCC), a pin (EN), a secondary ground wire (GND), a first state Flag register (Flag 1) and a second state Flag register (Flag 2);

the power conversion chip U2 (2) is connected with the second state Flag register (Flag 2) through a first lead.

As a further aspect of the present invention, the first status Flag register (Flag 1) is connected to the circuit switch SW1 (3) through a second wire, the circuit switch SW1 (3) is connected to VCC _ OUT, and the circuit switch SW1 (3) is connected to VCC _ IN through a third wire.

As a further aspect of the present invention, a resistor R3 is connected between the third wire and the second wire, and a resistor R4 is connected between the third wire and the first wire.

As a further aspect of the present invention, VCC _ IN is connected with a fourth wire, the fourth wire is connected with R1, R1 is connected with R2, R2 is connected with a total ground wire (CND).

As a further aspect of the present invention, the VCC is connected to the fourth wire and the resistor R1, the EN is connected to the resistor R1 and the resistor R2, and the GND is connected to the resistor R2 and the common ground (CND).

Compared with the prior art, the utility model provides a power supply time sequence control circuit has following beneficial effect:

1. the utility model discloses compare in the scheme of hanging 2 power conversion chips under power time sequence control chip, replace one of them power chip with SW1 now, reached same purpose, nevertheless saved the design cost.

Drawings

In order to facilitate understanding for those skilled in the art, the present invention will be further described with reference to the accompanying drawings.

Fig. 1 is a circuit block diagram of the present invention;

fig. 2 is a block diagram of the power-on sequence of the present invention;

fig. 3 is the power down timing diagram of the present invention.

In the figure: 1. a power supply time sequence control chip U1; 2. a power conversion chip U2; 3. a switch SW1.

Detailed Description

Please refer to fig. 1, fig. 2 and fig. 3 in combination, wherein fig. 1 is a circuit block diagram of the present invention; fig. 2 is a block diagram of the power-on sequence of the present invention; fig. 3 is the power down timing diagram of the present invention. The power supply timing control circuit includes: a power supply time sequence control chip U1 (1), a power supply conversion chip U2 (2) and a circuit switch SW1 (3);

the power supply time sequence control chip U1 (1) comprises a power supply Voltage (VCC), a pin (EN), an auxiliary ground wire (GND), a first state Flag register (Flag 1) and a second state Flag register (Flag 2);

The first status Flag register (Flag 1) is connected with the circuit switch SW1 (3) through a second wire, the circuit switch SW1 (3) is connected with VCC _ OUT, and the circuit switch SW1 (3) is connected with VCC _ IN through a third wire.

A resistor R3 is connected between the third lead and the second lead, and a resistor R4 is connected between the third lead and the first lead.

The VCC _ IN is connected with a fourth lead, the fourth lead is connected with R1, the R1 is connected with R2, and the R2 is connected with a total ground wire (CND).

VCC and fourth wire are connected and resistance R1 are connected, EN is connected with resistance R1 and resistance R2, GND is connected with resistance R2 and total ground wire (CND).

The utility model provides a power supply sequential control circuit's theory of operation as follows:

the first step is as follows: when a power adapter inputs a power through VCC _ IN, a power time sequence control chip U1 (1) determines whether the chip works according to the voltage of an enable pin EN, namely when the power-on reaches a threshold voltage, a flag1 effective signal is output firstly, a switch SW1 (3) is turned on, VCC _ IN outputs VCC _ OUT through the switch, after a certain time is delayed after the flag1 outputs the effective signal, a flag2 effective signal is output and the power conversion chip U2 (2) outputs VDD voltage, when the power-off is lower than the threshold voltage, a flag2 invalid signal is output firstly to close the output voltage VDD of the power conversion chip U2 (2), after the flag2 outputs the invalid signal, a certain time is delayed, a flag1 invalid signal is output, the switch SW1 (3) is closed, the VCC _ OUT and VCC _ IN are disconnected, and the VCC _ OUT starts to power down, therefore, the function that VCC _ OUT is prior to VDD when the power-on and VCC _ OUT is prior to the power-down is realized;

the second step: the power supply adapter is adopted to provide 5V input voltage, a VCC _ IN port is connected, a power supply time sequence control chip U1 (1) uses LM3880 of TI, a power supply conversion module U2 (2) uses an MP3429GL-Z test board of MPS, the output end is VDD, 12V, setting or material selection can be carried OUT according to the actual condition of a system, the power-on time sequence is shown IN figure 2, after VCC _ IN reaches EN pin threshold level of U1, U1 starts working, a flag1 effective signal is output firstly after about 10ms, SW1 (3) is driven to be opened, VCC _ OUT is output, a flag2 effective signal is output after 10ms is delayed after flag1 is effective, U2 is enabled to output VDD, the power-down time sequence is shown IN figure 3, after VCC _ IN is reduced to EN pin threshold level of U1, U1 stops working, a flag2 invalid signal is output firstly after about 10ms, U2 power supply output is closed, VDD is started, power-down is delayed again after invalid signal is output, SW1 (3) is closed, VCC _ IN and VCC _ OUT is disconnected, VCC _ OUT is connected, and then power-down is discharged gradually, thereby, the power-down is delayed.

It should be noted that the device structure and the accompanying drawings of the present invention mainly describe the principle of the present invention, and in the design principle, the settings of the power mechanism, the power supply system, the control system, etc. of the device are not completely described, and on the premise that the skilled person understands the principle of the present invention, the details of the power mechanism, the power supply system, and the control system can be clearly known, the control mode of the application file is automatically controlled by the controller, and the control circuit of the controller can be implemented by simple programming by the skilled person in the art;

the standard parts used in the method can be purchased from the market, and can be customized according to the description of the specification and the description of the attached drawings, the specific connection mode of each part adopts conventional means such as mature bolts, rivets, welding and the like in the prior art, the machinery, parts and equipment adopt conventional models in the prior art, and the structure and the principle of the parts are known by technical manuals or conventional experimental methods for technicians in the field.

Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, and it is intended that the scope of the invention be defined by the appended claims and their equivalents and that all such modifications are intended to be encompassed by the scope of the invention as defined in the claims.

Claims

1. A power timing control circuit, comprising:

the power supply time sequence control chip U1 (1), the power supply conversion chip U2 (2) and the circuit switch SW1 (3);

2. The power supply timing control circuit according to claim 1, wherein: the first status Flag register (Flag 1) is connected with the circuit switch SW1 (3) through a second wire, the circuit switch SW1 (3) is connected with VCC _ OUT, and the circuit switch SW1 (3) is connected with VCC _ IN through a third wire.

3. The power supply timing control circuit according to claim 2, wherein: and a resistor R3 is connected between the third lead and the second lead, and a resistor R4 is connected between the third lead and the first lead.

4. The power timing control circuit of claim 2, wherein: the VCC _ IN is connected with a fourth wire, the fourth wire is connected with R1, the R1 is connected with R2, and the R2 is connected with a total ground wire (CND).

5. The power timing control circuit of claim 4, wherein: VCC is connected with resistance R1 with the fourth wire, EN is connected with resistance R1 and resistance R2, GND is connected with resistance R2 and total ground wire (CND).