CN217846711U - Semiconductor packaging structure - Google Patents

Abstract

The utility model relates to a semiconductor packaging structure. The semiconductor package structure includes: a carrier; the optical integrated circuit is connected above the carrier and comprises a body part connected with the carrier and formed with at least one opening, at least one bearing part positioned in the at least one opening and spaced from the carrier, and at least two connecting parts respectively connecting two opposite sides of the bearing part and the body part; an optical component disposed over the optical integrated circuit and emitting light toward the optical integrated circuit; at least one sensor connected to the carrier; and the adjusting unit is arranged between the optical integrated circuit and the carrier and comprises a first magnetic piece connected to the carrier and a second magnetic piece connected below the bearing part. The technical scheme can at least reduce the overall size of the packaging structure and improve the yield of products.

Description

Semiconductor packaging structure

Technical Field

The embodiment of the utility model provides a relate to the semiconductor technology field, more specifically relates to a semiconductor package structure.

Background

Referring to fig. 1, an optical Integrated Circuit (PIC) 12, a Fiber Array Unit (FAU) 14 and an Electronic Integrated Circuit (EIC) 16 are Integrated in a conventional silicon Photonic package 10. The mirror 15 must be provided to reflect the optical path 18 to the PIC 12 under the position limitation of the PIC 12 and the FAU 14, which causes problems of long optical path 18, high component cost and bulky package structure. And during the reflection of the light there will be a refraction of part of the light 19, resulting in a reduction of the transmitted power. In addition, the PIC 12, the mirror 15, and the FAU 14 in the conventional silicon photonic package 10 are all fixed, and when the angle or position of the arrangement is not accurate enough, the problem that the optical path 18 cannot be guided to the PIC 12 correctly cannot be solved by adjusting the angle or position of the device, so that the yield loss is high.

SUMMERY OF THE UTILITY MODEL

To the above-mentioned problem among the correlation technique, the utility model provides a semiconductor package structure takes place reflection or refraction when can avoiding the light transmission, has reduced package structure overall dimension simultaneously, can also improve the product yield.

According to the utility model discloses an embodiment provides a semiconductor package structure. The semiconductor package structure includes: a carrier; the optical integrated circuit is connected above the carrier and comprises a body part, at least one bearing part and at least two connection parts, wherein the body part is connected with the carrier and is provided with at least one opening, the bearing part is positioned in the at least one opening and is spaced from the carrier, and the two connection parts are respectively connected with the two opposite sides of the bearing part and the body part; an optical component disposed over the optical integrated circuit and emitting light toward the optical integrated circuit; at least one sensor connected to the carrier; and the adjusting unit is arranged between the optical integrated circuit and the carrier and comprises a first magnetic piece connected to the carrier and a second magnetic piece connected below the bearing part.

In some embodiments, the engagement portion engages at a corner of the carrier portion.

In some embodiments, the width of the engagement portion gradually narrows from the body portion toward the carrying portion.

In some embodiments, the optical integrated circuit includes a plurality of carriers spaced apart in a horizontal direction, and the semiconductor package structure includes a plurality of sensors respectively connected to the plurality of carriers.

In some embodiments, the body portion is formed with a plurality of openings that respectively receive the plurality of carriers.

In some embodiments, the semiconductor package structure further comprises an electrical integrated circuit, the electrical integrated circuit being located between the optical component and the carrier.

In some embodiments, the electrical integrated circuit is disposed on the carrier side-by-side with the optical integrated circuit.

In some embodiments, the stack of electrical integrated circuits is disposed on the optical integrated circuit, and the electrical integrated circuits are directly electrically connected to the optical integrated circuit.

In some embodiments, the semiconductor package structure further includes a fixing member, and the fixing member holds the carrier portion at a fixed position.

In some embodiments, the semiconductor package structure further includes a molding compound disposed over the carrier, the molding compound having a cavity, the optical element being disposed over the cavity, and the carrier portion and the bonding portion being disposed in the cavity.

In the semiconductor packaging structure, the optical component and the optical integrated circuit are oppositely arranged, so that light rays from the optical component can directly reach the sensor from the optical component, a shorter light path can be provided, a reflector can be omitted, reflection or refraction during light ray transmission is avoided, and the whole size of the packaging structure is reduced; in addition, the sensor is arranged on the bearing part which can be changed in direction by the adjusting unit, so that the yield problem can be solved; the movement of the bearing part is adjusted through the adjusting unit, so that the sensor can receive light more easily, and the sizes of the sensor and the optical integrated circuit can be reduced.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 is a schematic cross-sectional view of a conventional silicon photonic package structure.

Fig. 2A is a schematic cross-sectional view of a semiconductor package structure according to some embodiments of the present application.

Fig. 2B is a top view schematic diagram of the photonic integrated circuit of fig. 2A according to the present application.

Fig. 2C-2F are enlarged partial views of fig. 2A, respectively, according to various embodiments of the present application.

Fig. 3A and 3B are schematic cross-sectional views of semiconductor package structures according to further embodiments of the present application, respectively.

Fig. 4A and 4B are schematic cross-sectional views of semiconductor package structures, respectively, according to further embodiments of the present application.

Fig. 5A and 5B are schematic cross-sectional views of semiconductor package structures according to further embodiments of the present application, respectively.

Fig. 6A-6J, 7A-7H, and 8A-8K illustrate schematic diagrams of various stages of a method of fabricating a semiconductor package structure according to some embodiments of the present application.

Fig. 6K-1 and 6K-2 are a perspective view and a top view, respectively, of the resulting structure of fig. 6J inverted and cut.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, for convenience, the terms "first," "second," and the like may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," etc. are not intended to describe corresponding components.

Fig. 2A is a schematic cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present application. Fig. 2B is a schematic top view of a PIC (Photonic Integrated Circuit) 120 of the semiconductor package structure 100 of fig. 2A according to the present application. Referring to fig. 2A and 2B, semiconductor package structure 100 includes a carrier 110 and a PIC 120 connected over carrier 110.

The PIC 120 includes a body portion 120a, the body portion 120a being connected to the carrier 110 and formed with an aperture 125. The body portion 120a of the PIC 120 may be attached to the upper surface of the carrier 110 by an adhesive layer 128. In some embodiments, the material of the adhesive layer 128 may be PI (Polyimide), resin (Epoxy), ABF (ajinomoto film), PP (polypropylene), and/or acrylic. In some embodiments, the material of the adhesive layer 128 may also be an organic photosensitive liquid material and/or an organic non-photosensitive liquid material and/or an organic photosensitive dry film material and/or an organic non-photosensitive dry film material.

PIC 120 also includes a carrier 120b, carrier 120b being located in opening 125 of body portion 120a, and carrier 120b and carrier 110 being spaced apart from each other. In some embodiments, the thickness of the carrier 120b is less than the thickness of the body portion 120a such that the carrier 110 and the carrier 120b are spaced apart from each other. The sensor 140 is attached to the upper surface of the bearing part 120b. The PIC 120 also includes a plurality of splices 120c (see fig. 2B). It should be noted that the cross-sectional view shown in fig. 2A may correspond tobase:Sub>A cross-sectional view taken inbase:Sub>A plane ofbase:Sub>A linebase:Sub>A-base:Sub>A in fig. 2B, and although the engagement portion 120c may be seen from the opening 125 in fig. 2A, the engagement portion 120c is not shown in the cross-sectional view of fig. 2A and the subsequent cross-sectional views. The engaging portions 120c respectively engage two opposite sides of the supporting portion 120b and the body portion 120a. For example, opposite sides of the carrying portion 120b in the horizontal direction X may be engaged by the engaging portion 120c, and/or opposite sides of the carrying portion 120b in the horizontal direction Y may be engaged by the engaging portion 120c.

The semiconductor package structure 100 also includes an optical component 130, the optical component 130 disposed over the PIC 120 and emitting light toward a sensor 140 on the PIC 120. In some embodiments, the optical assembly 130 is a FAU (Fiber array Unit), but other types of optical assemblies 130 may be used in other embodiments.

The semiconductor package structure 100 further includes an adjustment unit 150 disposed between the PIC 120 and the carrier 110. The adjusting unit 150 is located in the space between the lower surface of the carrying part 120b and the upper surface of the carrier 110. The adjustment unit 150 includes a first magnetic member 151 coupled to the carrier 110, and a second magnetic member 152 coupled below the bearing portion 120b. The first magnetic member 151 can cooperate with the second magnetic member 152 to generate repulsive and attractive magnetic forces to rotate the carrying portion 120b in the X-Z plane in clockwise/counterclockwise directions, so as to change the orientation of the carrying portion 120b and the sensor 140 thereon and adjust the angle between the sensor 140 and the optical path from the optical assembly 130.

In the semiconductor package structure 100, the optical element 130 (e.g., FAU) is disposed opposite the PIC 120, so that light from the optical element 130 can directly reach the sensor 140 from the optical element 130, thereby providing a short optical path. Moreover, because the optical component 130 is arranged opposite to the PIC 120, the use of a reflector can be omitted, thereby avoiding the reflection or refraction during the light transmission and simultaneously reducing the overall size of the packaging structure. In addition, in the conventional structure, the yield loss problem caused by the fixed arrangement of the components can be solved by arranging the sensor 140 on the bearing portion 120b that can be changed in orientation by the first magnetic member 151 and the second magnetic member 152. The movement (e.g., clockwise/counterclockwise rotation in the X-Z plane) of the bearing portion 120b is adjusted by the repulsive and attractive magnetic force between the first magnetic member 151 and the second magnetic member 152, so that the sensor 140 can receive light more easily, thereby further reducing the size of the sensor 140 and the PIC 120.

In the plan view of fig. 2B, the opening 125 and the bearing part 120B located in the opening 125 each have a rectangular shape, and the sensor 140 is disposed at the center of the bearing part 120B. The four engaging portions 120c engage at four corners of the supporting portion 120b. In other words, the opening 125 surrounds the sensor 140, and the engagement portions 120c are uniformly distributed around the sensor 140. The width of each engaging portion 120c is gradually narrowed from the body portion 120a toward the carrying portion 120b. By connecting the engaging portion 120c at the corner of the bearing portion 120b and having a width gradually narrowing toward the bearing portion 120b, it is possible to more easily adjust the orientation of the bearing portion 120b.

However, in other embodiments, the number of the engaging portions 120c may be two, and the two engaging portions 120c connect opposite sides (e.g., opposite sides in the horizontal direction X, opposite sides in the horizontal direction Y, or opposite sides in directions that make an angle with the horizontal directions X, Y) of the carrying portion 120b with the body portion 120a. In other embodiments, the number of the engaging portions 120c may be other numbers, and the carrying portions 120b may have any other suitable shapes.

Fig. 2C and 2D are partial enlarged views of fig. 2A, in which the orientation of the bearing part 120b is changed. In some embodiments, the first magnetic member 151 may be a coil. The second magnetic member 152 may be a magnetic material layer. The magnetic material can be a magnet film formed by sputtering and other processes of a magnet alloy palladium material, or a magnet paste block made of magnet paste by printing and other processes, wherein the magnet paste is formed by mixing magnet alloy material powder (solid content is about 60-80%), a high-molecular adhesive (10-20%), resin, a volatile solvent (10-20%) and other materials. The magnetic material powder of the magnet film and the magnet paste may be magnetite (iron II or iron III oxide; fe) ₃ O ₄ Barium oxide or strontium oxide powder), artificial magnets (for example, alnico magnets in which an alloy element such as aluminum, nickel, or cobalt is added to iron), rare earth magnets (for example, neodymium magnets, i.e., neodymium iron boron iron), and samarium cobalt magnets, and the like.

In some embodiments, the orientation of the sensor 140 can be controlled by selecting different directions of current flowing into the first magnetic member 151 (e.g., a coil) and selecting the polarity configuration of the second magnetic member 152 (e.g., a magnetic material) to generate the repulsive and attractive magnetic forces between the first magnetic member 151 and the second magnetic member 152. The magnitude of the repulsive and attractive magnetic force can also be controlled by passing different magnitudes of electric currents into the first magnetic member 151.

Specifically, as shown in fig. 2C, the initial angle between the light path PA and the surface of the sensor 140 is θ. Generally, the initial angle θ is preferably 90 °, i.e. the light path PA is perpendicular to the surface of the sensor 140, so as to prevent the light from the optical component 130 from being refracted after reaching the sensor 140, and to make the light from the optical component 130 have better transmission efficiency. When the initial angle θ is not equal to 90 ° due to the inaccurate setting angle or position of the PIC 120 or the optical element 130, by selecting the current direction in the first magnetic member 151 and the polarity setting of the second magnetic member 152, the magnetic force generated between the first magnetic member 151 and the second magnetic member 152 causes one side (e.g., left side) of the first magnetic member 151 and one side (e.g., right side) of the second magnetic member 152 to attract each other, and the other side (e.g., right side) of the second magnetic member 152 to repel each other, so that the bearing portion 120b and the sensor 140 thereon can be driven to rotate counterclockwise by the magnetic force, the bearing portion 120b, the second magnetic member 152 and the sensor 140 are respectively rotated to the positions shown by the dotted lines in fig. 2C, and the surface of the sensor 140 is perpendicular to the light path PA, thereby reducing light loss. At this time, the orientation of the sensor 140 generates an angular change of Δ θ, and the angle between the light path PA and the surface of the sensor 140 after the sensor 140 rotates counterclockwise is (θ - Δ θ).

In another use situation, as shown in fig. 2D, the magnetic force generated between the first magnetic member 151 and the second magnetic member 152 causes one side (e.g., right side) of the first magnetic member 151 and the second magnetic member 152 to attract each other, and the other side (e.g., left side) of the second magnetic member 152 to repel each other, so that the bearing portion 120b and the sensor 140 thereon can be driven to rotate clockwise by the magnetic force, the bearing portion 120b, the second magnetic member 152 and the sensor 140 can rotate to the positions shown by the dotted lines in fig. 2D, respectively, and the surface of the sensor 140 is perpendicular to the light path PA, thereby reducing the light loss. At this time, the orientation of the bearing portion 120b is changed by an angle Δ θ, and the angle between the optical path PA and the surface of the sensor 140 after the clockwise rotation of the bearing portion 120b is (θ + Δ θ). In this way, the angle between the light path PA and the surface of the sensor 140 can be adjusted by the repulsive and attractive magnetic force between the first magnetic member 151 and the second magnetic member 152, thereby making it easier for the sensor 140 to receive light.

In some embodiments, as shown in fig. 2E, the first magnetic member 151 and the second magnetic member 152 can be attracted by magnetic force to drive the bearing portion 120b and the sensor 140 thereon away from the optical assembly 130, so as to increase the distance between the sensor 140 and the optical assembly 130. In other embodiments, as shown in fig. 2F, the first magnetic member 151 and the second magnetic member 152 can repel each other by using magnetic force to drive the bearing portion 120b and the sensor 140 thereon to approach the optical assembly 130, so as to reduce the distance between the sensor 140 and the optical assembly 130. In this way, the distance between the light path PA and the surface of the sensor 140 can be adjusted by the repulsive and attractive magnetic force between the first magnetic member 151 and the second magnetic member 152, thereby being capable of being adapted to different use requirements.

Further, in some embodiments, the semiconductor package structure 100 may further include a fixing member 190 (e.g., an adhesive), for example, as shown in fig. 2C, to hold the carrier portion 120b at a fixed position. After the sensor 140 is adjusted to a proper position, a fixing member 190 may be disposed between the carrying portion 120b and the body portion 120a to hold the carrying portion 120b and the sensor 140 thereon in the adjusted proper position for direct use. In other embodiments, for example, as shown in fig. 2D, the fixing member 190 may not be provided, and the supporting portion 120b may be kept in a real-time adjustable state, so as to be beneficial to use environments suitable for different conditions.

Referring again to fig. 2A, the semiconductor package structure 100 further includes an EIC (Electronic Integrated Circuit) 160 located between the optical assembly 130 and the carrier 110. In this embodiment, the EIC 160 is disposed on the carrier 110 side by side with the PIC 120, for example in the horizontal direction X. In this embodiment, the EIC 160 is electrically connected to the carrier 110 through micro bumps (uBump) 162 with solder. The diameter of each microbump 162 may be in a range of 10 μm to 30 μm, and the pitch (pitch) between adjacent microbumps 162 may be in a range of 15 μm to 60 μm. PIC 120 is electrically connected to carrier 110 through leads 116 connected to the upper surface of carrier 110. In some embodiments, the material of the lead 116 may be copper, gold, silver, aluminum, palladium, platinum, or nickel alloy.

An underfill 166 is formed between the EIC 160 and the carrier 110, the underfill 166 surrounding the microbumps 162 between the EIC 160 and the carrier 110. In some embodiments, the material of the underfill 166 may be PI, resin, ABF, PP, and/or acryl. In some embodiments, the material of the underfill 166 may also be an organic photosensitive liquid material and/or an organic non-photosensitive liquid material and/or an organic photosensitive dry film material and/or an organic non-photosensitive dry film material. In other embodiments, the EIC 160 may also be attached to the carrier 110 by ACP (Anisotropic Conductive Paste) or ACF (Anisotropic Conductive Film). In some embodiments, the width dimension of the EIC 160 in the horizontal direction X may be in the range of tens of micrometers to several millimeters, and the thickness of the EIC 160 may be in the range of 20 μm to 200 μm. In some embodiments, the width dimension of the PIC 120 in the horizontal direction X may be in the range of tens of microns to several millimeters, and the thickness of the PIC 120 may be in the range of 20 μm to 200 μm.

The semiconductor package structure 100 further includes solder balls 104 disposed under the carrier 110 for electrically connecting to external structures. In some embodiments, the diameter of each solder ball 104 may be in the range of 30 μm to 200 μm, and the pitch between adjacent solder balls 104 may be in the range of 50 μm to 400 μm.

The semiconductor package structure 100 further includes a molding compound 170 disposed over the carrier 110, the molding compound 170 encapsulating the EIC 160 on the carrier 110, the body portion 120a of the PIC 120, and the upper surface of the carrier 110, the molding compound 170 further encapsulating an underfill 166 between the EIC 160 and the carrier 110, the adhesive layer 128 between the PIC 120 and the carrier 110, and the leads 116 connecting the PIC 120 and the carrier 110. In some embodiments, the material of the molding compound 170 may be PI, resin, ABF, PP, and/or acryl. In some embodiments, the material of the molding compound 170 may also be an organic photosensitive liquid material and/or an organic non-photosensitive liquid material and/or an organic photosensitive dry film material and/or an organic non-photosensitive dry film material.

In some embodiments, the height of the molding compound 170 (from the upper surface of the carrier 110 to the upper surface of the molding compound 170) may be in a range of 50 μm to 500 μm. The height of the interval between the lower surface of the bearing part 120b and the upper surface of the carrier 110 may be in the range of 5 μm to 100 μm. The thickness of the bearing part 120b may be in the range of 5 μm to 20 μm. The thickness of the second magnetic member 152 may be in the range of 2 μm to 20 μm.

The molding compound 170 has a cavity 172 therein, the optical element 130 is located above the cavity 172, and the carrying portion 120b and the connecting portion 120c are located in the cavity 172. By forming the molding compound 170 on the carrier 110, the strength of the semiconductor package structure 100 may be maintained. And as will be described in detail below, in the manufacturing process, the carrier plate of the carrier 110 is removed after the molding compound 170 is formed (such as removing the carrier plate 702 described below with reference to fig. 8G), and the molding compound 170 may be used to avoid warpage after the carrier plate 702 of the carrier 110 is removed.

The optical assembly 130 is secured to the molding compound 170 and spans the cavity 172 by an adhesive layer 138. In some embodiments, the thickness of the adhesive layer 138 may be in the range of 10 μm to 50 μm. The material of the adhesive layer 138 may be PI, resin, ABF, PP, and/or acryl. In some embodiments, the material of the adhesive layer 138 may also be an organic photosensitive liquid material and/or an organic non-photosensitive liquid material and/or an organic photosensitive dry film material and/or an organic non-photosensitive dry film material. The adhesive layer 138 exposes a portion of the lower surface of the optical component 130 so that the optical component 130 can emit light toward the sensor 140 over the PIC 120.

Further, in some embodiments, the support 110 is a redistribution layer (RDL). In such embodiments, the carrier 110 may comprise a plurality of dielectric layers, a first dielectric layer 111 and a second dielectric layer 112 being schematically shown stacked in fig. 2A. The carrier 110 further comprises conductive lines 115 in the first and second dielectric layers 111, 112. The conductive traces 115 may be made of copper, gold, silver, aluminum, palladium, platinum, nickel alloy, or the like. In this embodiment, two dielectric layers, i.e., the first dielectric layer 111 and the second dielectric layer 112, are shown, but the number of dielectric layers may be more than two. In some embodiments, the thickness of each of the first dielectric layer 111 and the second dielectric layer 112 may be in a range of 5 μm to 20 μm. The material of each of the first and second dielectric layers 111 and 112 may be PI, resin, ABF, PP, and/or acryl. In some embodiments, the material of each of the first dielectric layer 111 and the second dielectric layer 112 may also be an organic photosensitive liquid material and/or an organic non-photosensitive liquid material and/or an organic photosensitive dry film material and/or an organic non-photosensitive dry film material. The thickness of the conductive lines 115 in the carrier 110 extending in the horizontal plane X-Y may be in the range of 1 μm to 20 μm. Conductive line 115 can include a seed layer 116 (e.g., a Cu layer), and a metal layer 117 (e.g., a Ti layer) on seed layer 116. The thickness of the seed layer 116 may be in the range of 0.1 μm to 1 μm. Among them, the conductive line 115 may include a fine line of a line width/line space (L/S) <2 μm/2 μm (i.e., a line width and a line space <2 μm, respectively). Since the RDL can realize a thin line, a larger number of I/os can be provided, and thus miniaturization and low cost of the package structure can be realized. Additionally, in some applications where a greater number of I/Os are not required, the carrier 110 may be a substrate.

Fig. 3A and 3B are schematic cross-sectional views of semiconductor package structures 200a, 200B, respectively, according to further embodiments of the present application. In the semiconductor package structures 200a, 200B of fig. 3A and 3B, the PIC 120 includes a plurality of carriers 120B spaced apart from each other in the horizontal direction X. In such an embodiment, the body portion 120a is formed with a plurality of apertures 125, and the plurality of apertures 125 accommodate the plurality of bearing portions 120b, respectively. Two carriers 120B and corresponding two apertures 125 for each PIC 120 are shown in fig. 3A and 3B, but in other embodiments more carriers 120B and apertures 125 may be formed. Each of the bearing portions 120b is connected to a sensor 140. And an adjusting unit 150 including a first magnetic member 151 and a second magnetic member 152 is disposed under each bearing part 120b, respectively. A plurality of openings 125 are located within the same cavity 172 of the molding compound 170. In this way, a plurality of sensors 140 are provided on a plurality of carriers 120b, and different sensors 140 can be used to process light of different wavelengths, respectively.

In fig. 3A, the two openings 125 communicate with each other. Whereas in fig. 3B, a portion of the body portion 120a of the PIC 120 is present between the two apertures 125 to space the two apertures 125 apart. Providing a plurality of sensors 140 on a plurality of load bearing portions 120B in the manner shown in fig. 3B is structurally stronger than that shown in fig. 3A, and the orientation of each load bearing portion 120B can be individually adjusted without being affected by the other load bearing portions 120B.

Other aspects of fig. 3A and 3B may be the same and are the same as described above with reference to fig. 2A through 2F, and a description thereof will not be repeated.

Fig. 4A and 4B are schematic cross-sectional views of semiconductor package structures 300a, 300B, respectively, according to further embodiments of the present application. In semiconductor package structure 300a of fig. 4A, EIC 160 is stacked on PIC 120, EIC 160 being electrically connected directly to PIC 120. That is, EIC 160 is flip-chip and EIC 160 is bonded to PIC 120 by solder-bearing micro bumps 162. In semiconductor package structure 300B of fig. 4B, EIC 160 is stacked on PIC 120, EIC 160 being electrically connected to the upper surface of PIC 120 by leads 118. In the embodiment illustrated in fig. 4A and 4B, the size of semiconductor package structures 300a, 300B in the X-Y plane may be reduced by stacking EIC 160 on PIC 120.

Fig. 5A and 5B are schematic cross-sectional views of semiconductor package structures 400a, 400B, respectively, according to further embodiments of the present application. Referring to fig. 5A and 5B, the semiconductor package structures 400a, 400B further include a cover layer 180 covering the optical assembly 130. In fig. 5A, the capping layer 180 may be a molding compound (molding compound) formed using a molding process. In such embodiments, the sidewalls of the capping layer 180 may be aligned with the sidewalls of the molding compound 170 thereunder, and the capping layer 180 has a planar top surface that is higher than the top surface of the optical component 130. In fig. 5B, the covering layer 180 may be a non-metallic material formed using a drip irrigation (potting) process. In such an embodiment, the overlay 180 may have a convexly curved top surface. In the embodiment of fig. 5A and 5B, the cover layer 180 may be used to protect the optical assembly 130 by forming it.

The present application further provides a method of manufacturing a semiconductor package structure. Fig. 6A-8K show schematic diagrams of various stages of a method of fabricating a semiconductor package structure 100 according to some embodiments of the present application. Wherein fig. 6A-6K-2 show cross-sectional schematic diagrams of various stages of preparing the PIC 120; fig. 7A to 7H show schematic views of various stages of preparing the carrier 110. Fig. 8A through 8K show schematic diagrams of various stages of forming a semiconductor package structure 100 using the prepared carrier 110 and PIC 120.

Referring first to fig. 6A, a PIC wafer 120 'is provided, the PIC wafer 120' having opposing first and second surfaces 121, 122. The PIC wafer 120' has a plurality of pads 124 and a plurality of sensors 140 on the first surface 121. Referring to fig. 6B, a carrier board 602 and a buffer layer 604 are provided stacked on top of each other, the buffer layer 604 and the carrier board 602 are laminated (layering) on the PIC wafer 120' with the buffer layer 604 facing the PIC wafer 120' such that the buffer layer 604 encapsulates the plurality of pads 124 and the plurality of sensors 140 on the PIC wafer 120 '.

The resulting structure of fig. 6B is then inverted, as shown in fig. 6C, such that the second surface 122 of the PIC wafer 120' faces upward. A mask layer 611 covers the second surface 122 of the PIC wafer 120'. In some embodiments, the mask layer 611 may be a photoresist layer. The mask layer 611 may be patterned by a photolithography process to form a plurality of openings 621 through the mask layer 611, as shown in fig. 6D. The plurality of openings 621 are respectively located above the plurality of sensors 140. An etching process 631 is performed on the underlying PIC wafer 120 'through the plurality of openings 621 in the mask layer 611, thereby removing a portion of the PIC wafer 120' underlying the plurality of openings 621. This forms a plurality of recesses 622 on the second surface 122 of the PIC wafer 120', as shown in fig. 6E. A mask layer 613 is then conformally formed on the second surface 122 of the PIC wafer 120'.

As shown in fig. 6F, the mask layer 613 is patterned to form a plurality of openings 624 through the mask layer 613, the plurality of openings 624 being respectively located in the recesses 622 and above the corresponding sensors 140. Thereafter, a layer of magnetic material 152 is covered over the mask layer 612, the magnetic material 152 also filling in the respective openings 624. As shown in fig. 6G, an etching process 632 is performed on the magnetic material 152 to remove the magnetic material 152 outside the opening 624. The magnetic material 152 in the opening 624 is retained, as shown in fig. 6H, and the retained magnetic material 152 functions as the second magnetic member 152 as described above with reference to fig. 2A.

Thereafter, with continued reference to fig. 6H, a mask layer 615 is conformally formed over the second surface 122 of the PIC wafer 120'. Then, the mask layer 615 is patterned, and an opening 626 in the recess 622 is formed in the mask layer 615, as shown in fig. 6I. An opening 626 is located between the magnetic material 152 and the side wall of the recess 622, the opening 626 surrounding the magnetic material 152. Although not shown in the cross-sectional view of fig. 6I, the opening 626 has a pattern therein that corresponds to the engagement portion 120c described above with reference to fig. 2B. The underlying PIC wafer 120 'is etched through the opening 626 in the mask layer 615 to form an opening 125 through the PIC wafer 120', as shown in fig. 6J. After the opening 125 is formed, the carrier 602 and the buffer layer 604 are removed. The resulting structure of fig. 6J is then inverted and a dicing process is performed.

Fig. 6K-1 and 6K-2 show a perspective view and a top view, respectively, of the resulting structure of fig. 6J inverted and a cut performed. Referring collectively to fig. 6K-1 and 6K-2, a dicing process 634 is performed at a location between two adjacent sensors 140, resulting in a plurality of individual PICs 120. For each PIC 120, an opening 125 separates the PIC 120 into a body portion 120a and a carrier portion 120b, with the carrier portion 120b located in the opening 125. The engaging portion 120c is located at a corner of the carrying portion 120b and engages the carrying portion 120b and the body portion 120a. In this way, subsequent processes may be performed using a single PIC 120 after the single PIC 120 is formed.

The stages of preparing the carrier 110 are described below with reference to fig. 7A to 7H. First, as shown in fig. 7A, a carrier plate 702 is provided. The carrier plate 702 has pads 102 disposed thereon. As shown in fig. 7B, the first dielectric layer 111 is covered on the carrier board 702 and the pads 102 of the carrier board 702.

As shown in fig. 7C, a plurality of openings 721 are formed in the first dielectric layer 111. The opening 721 may be formed using photolithography. The opening 721 may expose the pad 102 under the first dielectric layer 111. Next, a seed layer 116 is conformally formed on the first dielectric layer 111 and the opening 721. In some embodiments, seed layer 116 may be deposited using, for example, physical Vapor Deposition (PVD).

As shown in fig. 7D, a mask layer 741 covers the seed layer 116. As shown in fig. 7E, the mask layer 741 is patterned, which may be photolithographically patterned, to form a plurality of openings 723 in the mask layer 741 that expose the seed layer 116. Next, a metal layer 117 is formed on the seed layer 116 in the plurality of openings 723 of the mask layer 741. The metal layer 117 may be formed by an electroplating process. Then, as shown in fig. 7F, the mask layer 741 and the seed layer 116 covered by the mask layer 741 are removed, for example, by etching. The remaining seed layer 116 and the metal layer 117 thereon form the conductive line 115. Some of the conductive lines 115 may be electrically connected to the pads 102 under the first dielectric layer 111.

As shown in fig. 7G, a second dielectric layer 112 is covered over the first dielectric layer 111. Then, steps similar to those of fig. 7C to 7F may be repeatedly performed to form conductive lines 115 in the second dielectric layer 112. As shown in fig. 7H, conductive lines 115 disposed in the second dielectric layer 112 are formed. In other embodiments, other numbers of dielectric layers, such as more than two layers, may be formed. In addition, the conductive line 115 includes therein a first magnetic member 151, such as a coil, as described above with reference to fig. 2A. Thus, an RDL is formed on carrier plate 702 to serve as carrier 110.

A schematic diagram of various stages of forming the semiconductor package structure 100 using the prepared carrier 110 and PIC 120 is described below in conjunction with fig. 8A through 8K. Referring to fig. 8A, carrier 110 formed on carrier plate 702 at fig. 7H is provided. An EIC 160 is attached to the carrier 110. In this embodiment, the EIC 160 is bonded to the conductive traces 115 of the carrier 110 by micro-bumps 162 with solder. As shown in fig. 8B, an Underfill 166 is formed between the EIC 160 and the carrier 110, such as by a Capillary Underfill (CUF) process to form the Underfill 166. The underfill 166 encapsulates the plurality of micro-bumps 162. In some embodiments, the underfill 166 may also surround the bottom of the EIC 160. Furthermore, in embodiments in which EIC 160 is not engaged on carrier 110, the steps of fig. 8A and 8B may be omitted.

Referring to fig. 8C, PIC 120 is fixed to carrier 110. An adhesive layer 128 may be disposed on the bottom of the body portion 120a of the PIC 120 to secure the PIC 120 to the carrier 110. Thereafter, as shown in fig. 8D, first wire bonding is performed to form first wires 161a electrically connecting the pads 124 on the PIC 120 and the carrier 110. The subsequent plurality of leads are formed until the final lead 161b is formed, as shown in fig. 8E. These leads, including the first lead 161a and the last lead 161b, may be collectively referred to as leads 116.

As shown in fig. 8F, a molding process is performed to form a molding compound 170 over the carrier 110. The molding compound 170 encapsulates the EIC 160 on the carrier 110, the body portion 120a of the PIC 120, and the upper surface of the carrier 110, the molding compound 170 further encapsulates the underfill 166 between the EIC 160 and the carrier 110, the adhesive layer 128 between the PIC 120 and the carrier 110, and the leads 116 connecting the PIC 120 and the carrier 110. In addition, the molding compound 170 forms a cavity 172 for receiving the carrier 120b of the PIC 120. In some embodiments in which EIC 160 is stacked over PIC 120, EIC 160 may be stacked and bonded onto PIC 120 prior to forming molding compound 170 in fig. 8F.

Referring to fig. 8G, the carrier plate 702 under the carrier 110 is removed. And after the carrier plate 702 is removed, the resulting structure is inverted as shown in fig. 8H. An etching process 802 is performed on the exposed surface of the carrier 110 to expose the pads 102 in the carrier 110. As shown in fig. 8I, a solder ball 104 is formed on the exposed pad 102.

The resulting structure in fig. 8I is inverted and the optical component 130 (e.g., FAU) is disposed over the molding compound 170 using the adhesive layer 138, with the optical component 130 positioned over the cavity 172 and across the cavity 172, such that the optical component 130 is disposed opposite the PIC 120, as shown in fig. 8J.

Then, as shown in fig. 8K, for example, in a wafer level (wafer level) process or a panel level (panel level) process, a dicing process may be performed on the molding compound 170 and the carrier 110, for example, along the dotted line L, so as to obtain the final semiconductor package structure 100. The resulting semiconductor package structure 100 may have the advantages described above with reference to fig. 2A-2F.

In some embodiments, after the semiconductor package structure 100 is manufactured, the orientation of the carrier 120b and the sensor 140 thereon may be adjusted by the first and second magnetic members 151 and 152, the orientation of the sensor 140 may be adjusted to a proper orientation, and the carrier 120b may be fixed at the adjusted proper orientation by a fixing member (see fig. 2C). In some embodiments, the support portion 120b is not fixed, so that the orientation of the support portion 120b and the sensor 140 thereon can be adjusted in real time during subsequent use, thereby being beneficial to different conditions of use.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor package structure, comprising:

a carrier;

the optical integrated circuit is connected above the carrier and comprises a body part connected with the carrier and formed with at least one opening, at least one bearing part positioned in the at least one opening and spaced from the carrier, and at least two connecting parts respectively connecting two opposite sides of the bearing part and the body part;

an optical component disposed over the optical integrated circuit and emitting light toward the optical integrated circuit;

at least one sensor connected to the carrier;

and the adjusting unit is arranged between the optical integrated circuit and the carrier and comprises a first magnetic piece connected to the carrier and a second magnetic piece connected below the bearing part.

2. The semiconductor package structure of claim 1, wherein the engagement portion engages at a corner of the carrier portion.

3. The semiconductor package structure of claim 2, wherein the width of the engagement portion gradually narrows from the body portion toward the carrier portion.

4. The semiconductor package structure of claim 1, wherein the optical integrated circuit comprises a plurality of the carriers spaced apart in a horizontal direction, and the semiconductor package structure comprises a plurality of the sensors respectively connected to the plurality of the carriers.

5. The semiconductor package structure according to claim 4, wherein the body portion is formed with a plurality of the openings, and the plurality of the openings respectively accommodate a plurality of the carriers.

6. The semiconductor package structure of claim 1, further comprising:

an electrical integrated circuit located between the optical component and the carrier.

7. The semiconductor package of claim 6, wherein the electrical integrated circuit is disposed on the carrier side-by-side with the optical integrated circuit.

8. The semiconductor package of claim 6, wherein the electrical integrated circuit stack is disposed on the optical integrated circuit and the electrical integrated circuit is directly electrically connected to the optical integrated circuit.

9. The semiconductor package structure of claim 1, further comprising:

and the fixing piece is used for keeping the bearing part at a fixed position.

10. The semiconductor package structure of claim 1, further comprising:

the molding compound is arranged above the carrier and provided with a cavity, the optical component is positioned above the cavity, and the bearing part and the jointing part are positioned in the cavity.

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