CN217821313U - Data acquisition device - Google Patents
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- CN217821313U CN217821313U CN202221722781.1U CN202221722781U CN217821313U CN 217821313 U CN217821313 U CN 217821313U CN 202221722781 U CN202221722781 U CN 202221722781U CN 217821313 U CN217821313 U CN 217821313U
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Abstract
The utility model relates to the technical field of data acquisition, and discloses a data acquisition device, which comprises a MCU main control unit, an AD input buffer unit, a PWM input buffer unit, a storage unit and a trigger unit; the AD input buffer unit and the PWM input buffer unit are configured to receive an analog signal to be recorded and a PWM signal to be recorded and send the received signal to the MCU main control unit; the MCU main control unit is respectively and electrically connected with the storage unit and the trigger unit; the trigger unit is configured to send a trigger signal to the MCU main control unit, and the trigger signal is used for starting and stopping recording; when in actual use, through using the utility model discloses can gather and save data automatically to and give the host computer with the data transmission who gathers, need not artifical record, convenient test.
Description
Technical Field
The utility model relates to a data acquisition technical field, concretely relates to data acquisition device.
Background
In the development process of electronic products, hardware circuits and software programs need to be tested to detect whether the functions or signal outputs of the electronic products are correct. Taking the test of a single chip microcomputer chip as an example, the single chip microcomputer is a control chip internally integrated with a plurality of functional modules such as a timer, a counter, a serial port module, an ADC module, a DAC module and an IO module. The testing of the output signal of the single chip microcomputer comprises testing whether the output analog signal is correct or not and testing whether the period and the duty ratio of the PWM signal output by the IO port are correct or not. The existing test about the signals is to observe and record through a manual oscilloscope, so that the defects that the equipment cost is high, manual work is consumed for long-time recording, manual recording is easy to make mistakes and the like exist.
SUMMERY OF THE UTILITY MODEL
In view of the not enough of background art, the utility model provides a data acquisition device can not need artifical record test data.
In order to solve the technical problem, the utility model provides a data acquisition device, which comprises a MCU main control unit, an AD input buffer unit, a PWM input buffer unit, a storage unit and a trigger unit;
the AD input buffer unit is configured to receive an analog signal to be recorded and send the received analog signal to the MCU main control unit;
the PWM input buffer unit is configured to receive a PWM signal to be recorded and send the received PWM signal to the MCU main control unit;
the MCU main control unit is electrically connected with the storage unit and the trigger unit respectively; the trigger unit is configured to send a trigger signal to the MCU master control unit, the trigger signal being used to start and stop recording.
In a certain implementation manner of the first aspect, the present invention further includes a USB interface and a data conversion unit, the MCU main control unit is electrically connected to the data conversion unit, the data conversion unit is electrically connected to the USB interface, and is configured to convert USB data into TTL level data or convert TTL level data into USB data.
In one embodiment of the first aspect, the AD input buffer unit includes a first operational amplifier unit, a second operational amplifier unit, a third operational amplifier unit, a reference voltage regulator unit, and an amplification factor regulator unit;
the positive input end of the first operational amplification unit and the positive input end of the second operational amplification unit are configured to input analog signals; the negative input end of the first operational amplification unit and the negative input end of the second operational amplification unit are electrically connected with the amplification regulation unit, the amplification regulation unit is configured to regulate the resistance between the negative input end of the first operational amplification unit and the negative input end of the second operational amplification unit and the grounding end, the output end of the first operational amplification unit is electrically connected with the negative input end of the third operational amplification unit, the output end of the second operational amplification unit is electrically connected with the positive input end of the third operational amplification unit, and the output end of the third operational amplification unit is electrically connected with the MCU main control unit;
the reference voltage adjusting unit is electrically connected with the MCU main control unit, receives the PWM control signal sent by the MCU main control unit, outputs reference voltage with variable amplitude based on the duty ratio of the PWM control signal, and inputs the reference voltage to the negative input end of the third operational amplification unit.
In one embodiment of the first aspect, the first operational amplifier unit includes an operational amplifier U1B, a resistor R5, and a resistor R6, and an output terminal of the operational amplifier U1B is electrically connected to a negative input terminal of the operational amplifier U1B sequentially through the resistor R5 and the resistor R6; the positive input end of the operational amplifier U1B is also electrically connected with one end of a capacitor C3, one end of a bidirectional diode D1 and one end of a resistor R1 respectively, and the other end of the bidirectional diode D1 and the other end of the capacitor C3 are grounded;
the second operational amplification unit comprises an operational amplifier U1A, a resistor R9 and a resistor R10, and the output end of the operational amplifier U1A is electrically connected with the negative input end of the operational amplifier U1A sequentially through the resistor R9 and the resistor R10; the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C6, one end of a bidirectional diode D5 and one end of a resistor R20 respectively, and the other end of the bidirectional diode D5 and the other end of the capacitor C6 are grounded;
the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C4 and one end of a bidirectional diode D2 respectively, and the other end of the capacitor C4 and the other end of the bidirectional diode D2 are electrically connected with the positive input end of the operational amplifier U1A;
the third operational amplification unit comprises an operational amplifier U1C, a resistor R3 and a resistor R4, and the output end of the operational amplifier U1C is electrically connected with the negative input end of the operational amplifier U1C through the resistor R3 and the resistor R4 in sequence; the positive input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1A through a resistor R17, and the negative input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1B through a resistor R2; the output end of the operational amplifier U1C is electrically connected with one end of a resistor R11, the other end of the resistor R11 is electrically connected with one end of a resistor R13 and one end of a resistor R12 respectively, the other end of the resistor R12 is electrically connected with one end of a capacitor C5, the anode of a diode D3 and the cathode of the diode D4 respectively, the cathode of the diode D3 is electrically connected with a power supply, and the anode of the diode D4, the other end of the capacitor C5 and the other end of the resistor R13 are all grounded.
In a certain implementation manner of the first aspect, the reference voltage adjusting unit includes an operational amplifier U1D, a positive input end of the operational amplifier U1D is electrically connected to one end of a capacitor C7 and one end of a resistor R14, the other end of the resistor R14 is electrically connected to one end of a capacitor C8 and one end of a resistor R15, the other end of the resistor R15 is electrically connected to one end of a capacitor C9 and the MCU main control unit, and the other end of the capacitor C7, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded; the negative input end of the operational amplifier U1D is electrically connected with one end of the resistor R7 and one end of the resistor R8 respectively, the other end of the resistor R8 is grounded, the other end of the resistor R7 is electrically connected with the output end of the operational amplifier U1D and one end of the resistor R19 respectively, and the other end of the resistor R9 is electrically connected with the negative input end of the third operational amplification unit through the resistor R18.
In a certain implementation manner of the first aspect, the amplification factor adjusting unit includes a switch chip U2, a pin one of the switch chip U2 sequentially passes through a resistor R26 and a resistor R21 to be electrically connected to a pin twelve of the switch chip U2, a pin two of the switch chip U2 sequentially passes through a resistor R28 and a resistor R23 to be electrically connected to a pin fifteen of the switch chip U2, a pin 4 of the switch chip U2 sequentially passes through a resistor R29 and a resistor R24 to be electrically connected to a pin eleven of the switch chip U2, a pin five of the switch chip U2 sequentially passes through a resistor R27 and a resistor R22 to be electrically connected to a pin fourteen of the switch chip U2, a pin three of the switch chip U2 is electrically connected to a negative input terminal of the second operational amplification unit, a pin thirteen of the switch chip U2 is electrically connected to a negative input terminal of the first operational amplification unit, a pin nine and a pin ten of the switch chip U2 are electrically connected to the MCU main control unit, a pin sixteen of the switch chip U2 inputs a power supply, and a pin six and a pin eight of the switch chip U2 are both grounded.
In one embodiment of the first aspect, the PWM input buffer unit includes an operational amplifier U20, a positive input terminal of the operational amplifier U20 is electrically connected to one end of a bidirectional diode D80 and one end of a bidirectional diode D81, respectively, the other end of the bidirectional diode D80 is connected to a first power supply, and the other end of the bidirectional diode D81 is grounded; the negative input end of the operational amplifier U20 is electrically connected with one end of a resistor R80 and one end of a resistor R81 respectively, the other end of the resistor R80 is grounded, the other end of the resistor R81 is electrically connected with one end of a resistor R83 and one end of a resistor R84 through a resistor R82 respectively, the other end of the resistor R83 is connected with a second power supply, the other end of the resistor R84 is electrically connected with one end of a resistor R85 and the output end of the operational amplifier U20 respectively, the other end of the resistor R85 is electrically connected with one end of a capacitor C80, the anode of a diode D82, the cathode of the diode D83 and one end of a resistor R86 are electrically connected, the other end of the capacitor C80 and the anode of the diode D83 are grounded, the cathode of the diode D82 is connected with a third power supply, and the other end of the resistor R86 is electrically connected with the MCU main control unit.
In a certain embodiment of the first aspect, the utility model discloses still include the power supply unit, the power supply unit includes voltage input end, boost unit, negative voltage generation unit, ADC reference voltage generation unit and LDO steady voltage unit, voltage input end respectively with boost unit, negative voltage generation unit, ADC reference voltage generation unit and LDO steady voltage unit electricity are connected, boost unit's voltage output end is connected with first operational amplification unit's positive voltage input end, second operational amplification unit's positive voltage input end, third operational amplification unit's positive voltage input end, operational amplifier U20's positive voltage input end and magnification adjustment unit power pin electricity respectively, the voltage output end of negative voltage generation unit is connected with first operational amplification unit's negative voltage input end, second operational amplification unit's negative voltage input end, third operational amplification unit's negative voltage input end, operational amplifier U20's negative voltage input end electricity respectively, LDO steady voltage unit respectively to storage unit, MCU main control unit provide operating voltage, ADC reference voltage generation unit to MCU main control unit provides ADC sampling reference voltage.
In a second aspect, the present invention further provides a data collecting method, using the above data collecting device, including the following steps:
s1: the method comprises the steps that an upper computer is used for carrying out information configuration on an MCU main control unit, and the amplification factor, the data source, the acquisition period, the recording time length, the data reporting interval and the acquisition start-stop mode of an AD input buffer unit are set, wherein the acquisition start-stop mode comprises trigger unit trigger start-stop and upper computer trigger start-stop;
s2: the method comprises the steps that signals to be collected are connected to an AD input buffer unit and a PWM input buffer unit, when the MCU main control unit receives a start collection signal according to a configured collection start-stop mode, the MCU main control unit collects data according to a set collection period within a set recording duration and stores the collected data in a storage unit, the collected data are sent to an upper computer periodically according to a set data reporting interval, when the data reporting interval is not set in the step S1, the MCU main control unit sends the collected data to the upper computer after the data collection is finished, and when the MCU main control unit receives a stop collection signal according to the configured collection start-stop mode, the MCU main control unit stops collecting the data.
Compared with the prior art, the utility model the beneficial effect who has is: through using the utility model discloses can gather and save data automatically to and give the host computer with the data transmission who gathers, need not artifical record, convenient test.
Drawings
Fig. 1 is a schematic structural diagram of the present invention in an embodiment;
FIG. 2 is a schematic diagram of an embodiment of an AD input buffer unit;
fig. 3 is a circuit diagram of a first operational amplification unit, a second operational amplification unit, and a third operational amplification unit in the embodiment;
fig. 4 is a circuit diagram of a magnification adjustment unit in the embodiment;
FIG. 5 is a circuit diagram of a reference voltage adjusting unit in the embodiment;
FIG. 6 is a circuit diagram of a PWM input buffer unit in an embodiment;
fig. 7 is a second structural diagram of the present invention in an embodiment;
fig. 8 is a schematic structural diagram of a power supply unit.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.
As shown in fig. 1, a data acquisition device includes an MCU main control unit 1, an AD input buffer unit 2, a PWM input buffer unit 3, a storage unit 4, and a trigger unit 5;
the AD input buffer unit 2 is configured to receive an analog signal to be recorded and send the received analog signal to the MCU main control unit 1;
the PWM input buffer unit 3 is configured to receive a PWM signal to be recorded and send the received PWM signal to the MCU main control unit 1;
the MCU main control unit 1 is respectively and electrically connected with the storage unit 4 and the trigger unit 5; the trigger unit 5 is configured to send a trigger signal to the MCU master unit 1, the trigger signal being used to start and stop recording.
In this embodiment, the triggering unit 5 may be a key, and when the key is pressed, the level state of a signal input to the MCU main control unit 1 by the key changes, and the level state change may be that the triggering signal changes to a high level state, or that the triggering signal changes to a low level state; when the MCU main control unit 1 receives a trigger signal when the MCU main control unit 1 does not start data acquisition, the MCU main control unit 1 starts data acquisition, and when the MCU main control unit 1 receives the trigger signal in the data acquisition process, the MCU main control unit 1 stops data acquisition;
in this embodiment, the model of the single chip microcomputer of the MCU main control unit 1 may be selected according to actual requirements, and may support IO output, analog data reception, and a communication interface.
In this embodiment, the type of the storage unit 4 may be selected according to the storage capacity and the storage type (power-down retention and non-power-down retention).
In addition, the utility model also comprises a USB interface 7 and a data conversion unit 6, the MCU main control unit 1 is electrically connected with the data conversion unit 6, the data conversion unit 6 is electrically connected with the USB interface 7 and is configured to convert the USB data into TTL level data or convert the TTL level data into the USB data. In actual use, the signal level output by the MCU main control unit 1 is not consistent with the signal level of an upper computer such as a computer, so the data conversion unit 6 is required to perform data conversion.
In actual use, the upper computer can send a collection starting command and a collection stopping command to the MCU main control unit 1 through the USB interface 7 and the data conversion unit 6, and the MCU main control unit 1 starts collecting data when receiving the collection starting command and stops collecting data when receiving the collection stopping command sent by the upper computer.
As shown in fig. 2, in the present embodiment, the AD input buffer unit 2 includes a first operational amplification unit 20, a second operational amplification unit 21, a third operational amplification unit 22, a reference voltage adjustment unit 23, and an amplification factor adjustment unit 24;
the positive input terminal of the first operational amplifier unit 20 and the positive input terminal of the second operational amplifier unit 21 are configured to input analog signals; the negative input end of the first operational amplification unit 20 and the negative input end of the second operational amplification unit 21 are electrically connected with the amplification adjustment unit 24, the amplification adjustment unit 24 is configured to adjust the resistance between the negative input end of the first operational amplification unit 20 and the negative input end and the grounding end of the second operational amplification unit 21, the output end of the first operational amplification unit 20 is electrically connected with the negative input end of the third operational amplification unit 22, the output end of the second operational amplification unit 21 is electrically connected with the positive input end of the third operational amplification unit 22, and the output end of the third operational amplification unit 22 is electrically connected with the MCU main control unit 1;
the reference voltage adjusting unit 23 is electrically connected with the MCU main control unit 1, receives the PWM control signal sent by the MCU main control unit 1, and outputs a reference voltage with a varying amplitude based on the duty ratio of the PWM control signal, and the reference voltage is input to the negative input terminal of the third operational amplifying unit 22; wherein the amplitude variation means that the magnitude of the reference voltage varies with the duty ratio of the PWM control signal.
In actual use, the input impedance of the AD input buffer unit 2 can be increased by providing the first operational amplification unit 20, the second operational amplification unit 21, and the third operational amplification unit 22; the amplification factors of the first operational amplification unit 20 and the second operational amplification unit 21 are adjusted by adjusting the resistance values between the negative input end of the first operational amplification unit 20 and the negative input end and the ground end of the second operational amplification unit 21 through the amplification factor adjustment unit 24, and the detection signal with smaller voltage amplitude can be amplified by changing the amplification factors of the first operational amplification unit 20 and the second operational amplification unit 21, so that the detection precision is improved; the measured voltage can be raised by changing the magnitude of the reference voltage input to the negative input terminal of the third operational amplification unit 22, so that a negative voltage signal can be detected;
specifically, as shown in fig. 3, the first operational amplification unit 20 includes an operational amplifier U1B, a resistor R5, and a resistor R6, and an output terminal of the operational amplifier U1B is electrically connected to a negative input terminal of the operational amplifier U1B through the resistor R5 and the resistor R6 in sequence; the positive input end of the operational amplifier U1B is also electrically connected with one end of a capacitor C3, one end of a bidirectional diode D1 and one end of a resistor R1 respectively, and the other end of the bidirectional diode D1 and the other end of the capacitor C3 are grounded;
the second operational amplification unit 21 comprises an operational amplifier U1A, a resistor R9 and a resistor R10, and the output end of the operational amplifier U1A is electrically connected with the negative input end of the operational amplifier U1A through the resistor R9 and the resistor R10 in sequence; the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C6, one end of a bidirectional diode D5 and one end of a resistor R20 respectively, and the other end of the bidirectional diode D5 and the other end of the capacitor C6 are grounded;
the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C4 and one end of a bidirectional diode D2 respectively, and the other end of the capacitor C4 and the other end of the bidirectional diode D2 are electrically connected with the positive input end of the operational amplifier U1A;
the third operational amplification unit 22 comprises an operational amplifier U1C, a resistor R3 and a resistor R4, and the output end of the operational amplifier U1C is electrically connected with the negative input end of the operational amplifier U1C through the resistor R3 and the resistor R4 in sequence; the positive input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1A through a resistor R17, and the negative input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1B through a resistor R2; the output end of the operational amplifier U1C is also electrically connected with one end of a resistor R11, the other end of the resistor R11 is respectively electrically connected with one end of a resistor R13 and one end of a resistor R12, the other end of the resistor R12 is respectively electrically connected with one end of a capacitor C5, the anode of a diode D3 and the cathode of a diode D4, the cathode of the diode D3 is electrically connected with a power supply, and the anode of the diode D4, the other end of the capacitor C5 and the other end of the resistor R13 are all grounded;
the bidirectional diode D1, the bidirectional diode D2 and the bidirectional diode D5 are all bidirectional TVS tubes, so that the input port Vin _1 and the input port Vin _2 can be protected from spike pulse or electrostatic damage, and the normal operation of the operational amplifier U1A and the operational amplifier U1B is ensured; the capacitor C3, the capacitor C4 and the capacitor C6 are used for filtering, so that the noise of an input signal is reduced; the diode D3 and the diode D4 are used to prevent the output voltage of the operational amplifier U1C from being too high and losing the input port of the MCU master control unit 1.
The utility model discloses a process is stayed in AD input buffer unit 2's work as follows: two ends of a detected signal are respectively input into a resistor R1 and a resistor R20, the detected signal is respectively input into an operational amplifier U1B and an operational amplifier U1A after being filtered by a capacitor C3, a capacitor C4 and a capacitor C6, the detected signal is input into an operational amplifier U1C after being buffered by the operational amplifier U1A and the operational amplifier U1B, the detected signal is output into a resistor R11 and a resistor R13 after being amplified by the operational amplifier U1C, the resistor 11 and the resistor R13 are used for voltage division, and finally, the divided signal is input into the MCU main control unit 1.
As shown in fig. 4, the amplification factor adjusting unit 24 includes a switch chip U2, a pin one of the switch chip U2 passes through a resistor R26 and a resistor R21 to be electrically connected to a pin twelve of the switch chip U2, a pin two of the switch chip U2 passes through a resistor R28 and a resistor R23 to be electrically connected to a pin fifteen of the switch chip U2, a pin 4 of the switch chip U2 passes through a resistor R29 and a resistor R24 to be electrically connected to a pin eleven of the switch chip U2, a pin five of the switch chip U2 passes through a resistor R27 and a resistor R22 to be electrically connected to a pin fourteen of the switch chip U2, a pin three of the switch chip U2 is electrically connected to a negative input terminal of a second operational amplifier unit, a pin thirteen of the switch chip U2 is electrically connected to a negative input terminal of a first operational amplifier unit, a pin nine pin and a pin ten of the switch chip U2 are electrically connected to the MCU main control unit, a pin sixteen of the switch chip U2 inputs a power supply, and a pin six and a pin eight of the switch chip U2 are grounded.
The resistor R21 and the resistor R26 form a resistor branch, the resistor R22 and the resistor R27 form a resistor branch, the resistor R23 and the resistor R28 form a resistor branch, and the resistor R24 and the resistor R29 form a resistor branch; the MCU main control unit 1 can connect the negative input terminal of the operational amplifier U1B and the negative input terminal of the operational amplifier U1A to different resistor branches through the switch chip U2, so as to adjust the amplification factors of the operational amplifier U1B and the operational amplifier U1A.
As shown in fig. 5, the reference voltage adjusting unit 23 includes an operational amplifier U1D, a positive input end of the operational amplifier U1D is electrically connected to one end of a capacitor C7 and one end of a resistor R14, the other end of the resistor R14 is electrically connected to one end of a capacitor C8 and one end of a resistor R15, the other end of the resistor R15 is electrically connected to one end of a capacitor C9 and the MCU main control unit, and the other end of the capacitor C7, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded; the negative input end of the operational amplifier U1D is electrically connected with one end of the resistor R7 and one end of the resistor R8 respectively, the other end of the resistor R8 is grounded, the other end of the resistor R7 is electrically connected with the output end of the operational amplifier U1D and one end of the resistor R19 respectively, and the other end of the resistor R9 is electrically connected with the negative input end of the third operational amplification unit through the resistor R18.
The resistor R16 and the capacitor C9 form a first-order filter circuit, the resistor 15 and the capacitor C8 form a second-order filter circuit, the resistor R14 and the resistor C7 form a third-order filter circuit, and PWM signals input by the MCU main control unit 1 can be converted into stable voltage signals through the three filter circuits so as to automatically adjust the reference.
As shown in fig. 6, in the present embodiment, the PWM input buffer unit 3 includes an operational amplifier U20, a positive input terminal of the operational amplifier U20 is electrically connected to one end of a bidirectional diode D80 and one end of a bidirectional diode D81 respectively, the other end of the bidirectional diode D80 is connected to a first power supply, and the other end of the bidirectional diode D81 is grounded; the negative input end of the operational amplifier U20 is electrically connected with one end of a resistor R80 and one end of a resistor R81 respectively, the other end of the resistor R80 is grounded, the other end of the resistor R81 is electrically connected with one end of a resistor R83 and one end of a resistor R84 through a resistor R82 respectively, the other end of the resistor R83 is connected with a second power supply, the other end of the resistor R84 is electrically connected with one end of a resistor R85 and the output end of the operational amplifier U20 respectively, the other end of the resistor R85 is electrically connected with one end of a capacitor C80, the anode of a diode D82, the cathode of the diode D83 and one end of a resistor R86 respectively, the other end of the capacitor C80 and the anode of the diode D83 are grounded, the cathode of the diode D82 is connected with a third power supply, and the other end of the resistor R86 is electrically connected with the MCU main control unit.
Likewise, the diode D82 and the diode D83 can prevent the output voltage of the operational amplifier U20 from being too high and losing the input port of the MCU master control unit 1; the bidirectional diode D80 and the bidirectional diode D81 can protect the input port COMP _ IN _1 from spike or electrostatic damage, and ensure that the operational amplifier U20 operates normally.
In addition, in the circuit of the PWM input buffer unit 3 shown in fig. 6, the operational amplifier U20, the resistor R2, the resistor R3, and the resistor R5 constitute a voltage follower, which increases the input impedance and reduces the influence on the signal to be measured.
As shown in fig. 7, the utility model discloses still include power supply unit 8, power supply unit 8 is used for providing the required operating voltage of AD input buffering 2 units, PWM input buffer unit 3, memory cell 4, MCU main control unit 1 and the work of data conversion unit 6. In this embodiment, the operating voltage of the storage unit 4 is 3.3V, the operating voltage of the MCU main control unit is 3.3V, and the operating voltages of +15V and-15V are required for the operational amplifier U1A, the operational amplifier U1B, the operational amplifier U1C, and the operational amplifier U20.
As shown in fig. 8, the power supply unit 8 includes a power supply unit including a voltage input terminal VIN, a boosting unit 80, a negative voltage generating unit 81, an ADC reference voltage generating unit 82, and an LDO voltage stabilizing unit 83;
the voltage input end VIN is electrically connected with the boosting unit 80, the negative voltage generating unit 81, the ADC reference voltage generating unit 82 and the LDO voltage stabilizing unit 83, respectively; the boost unit 80 is used for boosting the 5V input voltage to 15V, the negative voltage generating unit 81 is used for converting the 5V voltage into-15V voltage, the ADC reference voltage generating unit 82 is used for converting the 5V voltage into 3V voltage, and the LDO voltage stabilizing unit 83 is used for converting the 5V voltage into 3.3V voltage;
the voltage output end of the voltage boosting unit 80 is electrically connected to the positive voltage input end of the first operational amplification unit 20, the positive voltage input end of the second operational amplification unit 21, the positive voltage input end of the third operational amplification unit 22, the positive voltage input end of the operational amplifier U20 and the power pin of the amplification adjustment unit 24, the voltage output end of the negative voltage generation unit 81 is electrically connected to the negative voltage input end of the first operational amplification unit 20, the negative voltage input end of the second operational amplification unit 21, the negative voltage input end of the third operational amplification unit 22 and the negative voltage input end of the operational amplifier U20, the LDO voltage stabilization unit 83 provides working voltage to the storage unit 4 and the MCU main control unit 1, and the ADC reference voltage generation unit 82 provides ADC sampling reference voltage to the MCU main control unit. In this embodiment, the voltage input terminal VIN is a power supply terminal of the USB interface 7.
The utility model discloses when the in-service use, MCU main control unit 1 can be with the data storage who receives through AD input buffer unit 2 and PWM input buffer unit 3 to memory cell 4, need not artifical manual record, and efficiency is fast, also can send the data of gathering for the host computer through data conversion unit 6 and USB interface 7 in addition, is convenient for look over.
Additionally, the utility model provides a data acquisition method uses foretell data acquisition device, including following step:
s1: an upper computer is used for carrying out information configuration on the MCU main control unit 1, and the amplification factor, the data source, the acquisition period, the recording time length, the data reporting interval and the acquisition start-stop mode of the AD input buffer unit 2 are set, wherein the acquisition start-stop mode comprises the trigger unit 4 for triggering start-stop and the upper computer for triggering start-stop;
s2: the method comprises the steps that signals to be collected are connected to an AD input buffer unit 2 and a PWM input buffer unit 3, when the MCU main control unit 1 receives a start collection signal according to a configured collection start-stop mode, the MCU main control unit 1 collects data according to a set collection period within a set recording duration and stores the collected data into a storage unit 4, the collected data are sent to an upper computer periodically according to a set data reporting interval, when the data reporting interval is not set in the step S1, the MCU main control unit 1 sends the collected data to the upper computer after the data collection is finished, and when the MCU main control unit 1 receives a stop collection signal according to the configured collection start-stop mode, the MCU main control unit 1 stops collecting the data.
In step S2, when the data reporting interval is not set in step S1, the data reporting interval is set to 0.
In light of the above, the present invention is to be construed as being applicable to various changes and modifications within the scope of the present invention as defined by the appended claims. The technical scope of the present invention is not limited to the content of the description, and must be determined according to the scope of the claims.
Claims (8)
1. A data acquisition device is characterized by comprising an MCU main control unit, an AD input buffer unit, a PWM input buffer unit, a storage unit and a trigger unit;
the AD input buffer unit is configured to receive an analog signal to be recorded and send the received analog signal to the MCU main control unit;
the PWM input buffer unit is configured to receive a PWM signal to be recorded and send the received PWM signal to the MCU main control unit;
the MCU main control unit is electrically connected with the storage unit and the trigger unit respectively; the trigger unit is configured to send a trigger signal to the MCU master control unit, the trigger signal being used to start and stop recording.
2. The data acquisition device according to claim 1, further comprising a USB interface and a data conversion unit, wherein the MCU master control unit is electrically connected to the data conversion unit, and the data conversion unit is electrically connected to the USB interface and configured to convert USB data into TTL level data or convert TTL level data into USB data.
3. The data acquisition device according to claim 1, wherein the AD input buffer unit includes a first operational amplification unit, a second operational amplification unit, a third operational amplification unit, a reference voltage adjustment unit, and an amplification factor adjustment unit;
the positive input end of the first operational amplification unit and the positive input end of the second operational amplification unit are configured to input analog signals; the negative input end of the first operational amplification unit and the negative input end of the second operational amplification unit are electrically connected with the amplification regulation unit, the amplification regulation unit is configured to regulate the resistance value between the negative input end of the first operational amplification unit and the negative input end and the grounding end of the second operational amplification unit, the output end of the first operational amplification unit is electrically connected with the negative input end of the third operational amplification unit, the output end of the second operational amplification unit is electrically connected with the positive input end of the third operational amplification unit, and the output end of the third operational amplification unit is electrically connected with the MCU main control unit;
the reference voltage adjusting unit is electrically connected with the MCU main control unit, receives the PWM control signal sent by the MCU main control unit, outputs reference voltage with variable amplitude based on the duty ratio of the PWM control signal, and inputs the reference voltage to the negative input end of the third operational amplification unit.
4. The data acquisition device according to claim 3, wherein the first operational amplification unit comprises an operational amplifier U1B, a resistor R5 and a resistor R6, and the output end of the operational amplifier U1B is electrically connected with the negative input end of the operational amplifier U1B through the resistor R5 and the resistor R6 in sequence; the positive input end of the operational amplifier U1B is also electrically connected with one end of a capacitor C3, one end of a bidirectional diode D1 and one end of a resistor R1 respectively, and the other end of the bidirectional diode D1 and the other end of the capacitor C3 are grounded;
the second operational amplification unit comprises an operational amplifier U1A, a resistor R9 and a resistor R10, and the output end of the operational amplifier U1A is electrically connected with the negative input end of the operational amplifier U1A sequentially through the resistor R9 and the resistor R10; the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C6, one end of a bidirectional diode D5 and one end of a resistor R20 respectively, and the other end of the bidirectional diode D5 and the other end of the capacitor C6 are grounded;
the positive input end of the operational amplifier U1A is also electrically connected with one end of a capacitor C4 and one end of a bidirectional diode D2 respectively, and the other end of the capacitor C4 and the other end of the bidirectional diode D2 are electrically connected with the positive input end of the operational amplifier U1A;
the third operational amplification unit comprises an operational amplifier U1C, a resistor R3 and a resistor R4, and the output end of the operational amplifier U1C is electrically connected with the negative input end of the operational amplifier U1C sequentially through the resistor R3 and the resistor R4; the positive input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1A through a resistor R17, and the negative input end of the operational amplifier U1C is electrically connected with the output end of the operational amplifier U1B through a resistor R2; the output end of the operational amplifier U1C is electrically connected with one end of a resistor R11, the other end of the resistor R11 is electrically connected with one end of a resistor R13 and one end of a resistor R12 respectively, the other end of the resistor R12 is electrically connected with one end of a capacitor C5, the anode of a diode D3 and the cathode of the diode D4 respectively, the cathode of the diode D3 is electrically connected with a power supply, and the anode of the diode D4, the other end of the capacitor C5 and the other end of the resistor R13 are all grounded.
5. The data acquisition device according to claim 3 or 4, wherein the amplification factor adjustment unit comprises a switch chip U2, a pin I of the switch chip U2 is electrically connected with a pin twelve of the switch chip U2 sequentially through a resistor R26 and a resistor R21, a pin II of the switch chip U2 is electrically connected with a pin fifteen of the switch chip U2 sequentially through a resistor R28 and a resistor R23, a pin 4 of the switch chip U2 is electrically connected with a pin eleven of the switch chip U2 sequentially through a resistor R29 and a resistor R24, a pin five of the switch chip U2 is electrically connected with a pin fourteen of the switch chip U2 sequentially through a resistor R27 and a resistor R22, a pin three of the switch chip U2 is electrically connected with a negative input end of a second operational amplification unit, a pin thirteen of the switch chip U2 is electrically connected with a negative input end of a first operational amplification unit, a pin nine pin and a pin ten of the switch chip U2 are electrically connected with the MCU main control unit, a pin sixteen of the switch chip U2 inputs a power supply, and a pin six pin and a pin eight of the switch chip U2 are both grounded.
6. The data acquisition device according to claim 3 or 4, wherein the reference voltage adjusting unit comprises an operational amplifier U1D, a positive input end of the operational amplifier U1D is electrically connected with one end of a capacitor C7 and one end of a resistor R14 respectively, the other end of the resistor R14 is electrically connected with one end of a capacitor C8 and one end of a resistor R15 respectively, the other end of the resistor R15 is electrically connected with one end of a capacitor C9 and the MCU main control unit respectively, and the other end of the capacitor C7, the other end of the capacitor C8 and the other end of the capacitor C9 are all grounded; the negative input end of the operational amplifier U1D is electrically connected with one end of the resistor R7 and one end of the resistor R8 respectively, the other end of the resistor R8 is grounded, the other end of the resistor R7 is electrically connected with the output end of the operational amplifier U1D and one end of the resistor R19 respectively, and the other end of the resistor R9 is electrically connected with the negative input end of the third operational amplification unit through the resistor R18.
7. The data acquisition device according to claim 3, wherein the PWM input buffer unit comprises an operational amplifier U20, a positive input end of the operational amplifier U20 is respectively electrically connected with one end of a bidirectional diode D80 and one end of a bidirectional diode D81, the other end of the bidirectional diode D80 is connected to a first power supply, and the other end of the bidirectional diode D81 is grounded; the negative input end of the operational amplifier U20 is electrically connected with one end of a resistor R80 and one end of a resistor R81 respectively, the other end of the resistor R80 is grounded, the other end of the resistor R81 is electrically connected with one end of a resistor R83 and one end of a resistor R84 through a resistor R82 respectively, the other end of the resistor R83 is connected with a second power supply, the other end of the resistor R84 is electrically connected with one end of a resistor R85 and the output end of the operational amplifier U20 respectively, the other end of the resistor R85 is electrically connected with one end of a capacitor C80, the anode of a diode D82, the cathode of the diode D83 and one end of a resistor R86 are electrically connected, the other end of the capacitor C80 and the anode of the diode D83 are grounded, the cathode of the diode D82 is connected with a third power supply, and the other end of the resistor R86 is electrically connected with the MCU main control unit.
8. The data acquisition device according to claim 7, further comprising a power supply unit, wherein the power supply unit comprises a voltage input terminal, a boost unit, a negative voltage generation unit, an ADC reference voltage generation unit and an LDO regulation unit, the voltage input terminal is electrically connected to the boost unit, the negative voltage generation unit, the ADC reference voltage generation unit and the LDO regulation unit, the voltage output terminal of the boost unit is electrically connected to the positive voltage input terminal of the first operational amplification unit, the positive voltage input terminal of the second operational amplification unit, the positive voltage input terminal of the third operational amplification unit, the positive voltage input terminal of the operational amplifier U20 and the amplification factor regulation unit power pin, the voltage output terminal of the negative voltage generation unit is electrically connected to the negative voltage input terminal of the first operational amplification unit, the negative voltage input terminal of the second operational amplification unit, the negative voltage input terminal of the third operational amplification unit and the negative voltage input terminal of the operational amplifier U20, the LDO regulation unit provides the working voltage to the storage unit and the MCU unit, and the ADC reference voltage generation unit provides the ADC sampling reference voltage to the MCU unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221722781.1U CN217821313U (en) | 2022-07-05 | 2022-07-05 | Data acquisition device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221722781.1U CN217821313U (en) | 2022-07-05 | 2022-07-05 | Data acquisition device |
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| Publication Number | Publication Date |
|---|---|
| CN217821313U true CN217821313U (en) | 2022-11-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221722781.1U Active CN217821313U (en) | 2022-07-05 | 2022-07-05 | Data acquisition device |
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| CN (1) | CN217821313U (en) |
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