CN216248109U - Data acquisition instrument with multiple acquisition functions - Google Patents
Data acquisition instrument with multiple acquisition functions Download PDFInfo
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- CN216248109U CN216248109U CN202122166219.7U CN202122166219U CN216248109U CN 216248109 U CN216248109 U CN 216248109U CN 202122166219 U CN202122166219 U CN 202122166219U CN 216248109 U CN216248109 U CN 216248109U
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Abstract
The utility model relates to a data acquisition instrument with multiple acquisition functions, which comprises a shell, wherein a sensing device interface, an equipment communication interface, a data communication interface, an analog and digital signal input interface and an LCD display screen are arranged on the shell, the circuit board in the shell is provided with a signal selection circuit, a filter circuit, an amplifying circuit, an analog-digital conversion circuit, a singlechip U1, a display circuit and a wireless communication module, the utility model can carry out data acquisition and control on various traditional equipment and parameters through a sensing device interface, an equipment communication interface, a data communication interface and an analog and digital signal input interface, meanwhile, the system can communicate with a plurality of intelligent devices and acquire the collected data, has simple structure and low cost, the feasibility is high, the data acquisition efficiency and the reliability and flexibility of data acquisition are greatly improved, and the integrated design has high practicability.
Description
Technical Field
The utility model belongs to the technical field of data acquisition instruments, and particularly relates to a data acquisition instrument with multiple acquisition functions.
Background
The power grid center digital system is an important infrastructure for bearing power grid regulation and control operation and is a core brain for guaranteeing safe and stable operation of the power grid.
The power grid center digital system realizes the basic function of digitalizing the stations and equipment, meets the global control related to the stations, and improves the timely effectiveness of positioning the hidden danger of the power quality and troubleshooting, thereby improving the key supporting force and the technical level in the innovative development process of a company; various documents generated during operation are classified and sorted, and are digitally managed together with documents of daily work, scientific research achievements and the like; the collected mass data are analyzed by receiving data packets from other platform databases and program interfaces, and because the power and environmental conditions of the digital system in the power grid center generate large data volume, different parameter data of various devices need to be collected every few seconds or dozens of seconds, the collected data are not only one, and when a plurality of data are monitored together, a data collecting instrument with multiple collecting functions needs to be provided.
SUMMERY OF THE UTILITY MODEL
The utility model overcomes the defects of the prior art, and solves the technical problems that: a data acquisition instrument with multiple acquisition functions is provided, which can acquire data with various devices and parameters.
In order to solve the technical problems, the utility model adopts the technical scheme that: a data acquisition instrument with multiple acquisition functions comprises a shell, wherein a sensing device interface, an equipment communication interface, a data communication interface, an analog and digital signal input interface and an LCD display screen are arranged on the shell, a signal selection circuit, a filter circuit, an amplifying circuit, an analog-to-digital conversion circuit, a singlechip U1, a display circuit and a wireless communication module are arranged on a circuit board in the shell, the sensor device interface, the equipment communication interface, the data communication interface and the analog and digital signal input interface are respectively connected with the input end of the signal selection circuit, the output end of the signal selection circuit is sequentially connected with the input end of the single chip microcomputer U1 through the filter circuit, the amplifying circuit and the analog-to-digital conversion circuit, the output end of the single chip microcomputer U1 is connected with the background server through the wireless communication module, and the output end of the single chip microcomputer U1 is connected with the LCD display screen through the display circuit.
Furthermore, an optical fiber communication interface J1 is further arranged on the shell, an optical fiber communication interface circuit is further arranged on the circuit board, and the output end of the main control chip U1 is connected with the background server sequentially through the optical fiber communication interface circuit and the optical fiber communication interface J1.
Preferably, the optical fiber communication interface circuit includes a level conversion chip U4, the C1+ terminal of the level conversion chip U4 is connected in series with the electrolytic capacitor E2 and then connected to the C1-terminal of the level conversion chip U4, the V + terminal of the level conversion chip U4 is connected in series with the electrolytic capacitor E1 and then grounded, the C2+ terminal of the level conversion chip U4 is connected in series with the electrolytic capacitor E3 and then connected to the C2-terminal of the level conversion chip U4, the V-terminal of the level conversion chip U4 is connected in series with the electrolytic capacitor E4 and then grounded, the VCC terminal of the level conversion chip U4 is connected to the +5V power terminal and one terminal of the electrolytic capacitor E5, the other terminal of the electrolytic capacitor E5 is connected to the level conversion chip U4 and then grounded, the GND terminal of the level conversion chip U4 is connected to the second terminal of the optical fiber communication interface J1, the R1 terminal IN terminal of the level conversion chip 4 is connected to the third terminal 1, the first wiring terminal of the optical fiber communication interface J1 is connected with the +5V power supply end, the fifth wiring terminal of the optical fiber communication interface J1 is grounded, the R1OUT end of the level conversion chip U4 is connected with the P1.2 end of the single chip microcomputer U1, and the T1IN end of the level conversion chip U4 is connected with the P1.1 end of the single chip microcomputer U1.
Preferably, the filter circuit includes an amplifier P1 and an amplifier P2, a non-inverting input terminal of the amplifier P1 is connected in series with a resistor R3 and a resistor R1in sequence and then connected to an output terminal of the signal selection circuit, a connection line between the resistor R3 and the resistor R1 is connected in series with a capacitor C1 and then grounded, a series circuit composed of the capacitor C1 and the capacitor C1 is connected in parallel with both ends of the series circuit composed of the resistor R1 and the resistor R1, a connection line between the capacitor C1 and the capacitor C1 is connected in series with the non-inverting input terminal of the amplifier P1 and then connected to an output terminal of the amplifier P1, an inverting input terminal of the amplifier P1 is connected in series with the resistor R1 and then connected to ground, a connection line between the inverting input terminal of the amplifier P1 and the resistor R1 is connected to the non-inverting input terminal of the amplifier P1 and then connected to the connection line of the amplifier P1 and then connected to the non-inverting input terminal of the amplifier P1, the inverting input end of the amplifier P2 is connected with the output end of the amplifier P2 and the connecting terminal b after being connected with the resistor R6 in series, the capacitor C4 is connected with the two ends of the resistor R6 in parallel, and the output end of the filter circuit is connected with the input end of the amplifying circuit through the connecting terminal b.
Preferably, the amplifying circuit comprises a digital potentiometer U2, an amplifier P3 and an amplifier P4, the INC terminal of the digital potentiometer U2 is connected with the P2.1 terminal of the singlechip U1, the U/D terminal of the digital potentiometer U2 is connected with the P2.0 terminal of the singlechip U1, the VH terminal of the digital potentiometer U2 is connected with the output terminal of the filter circuit through a connection terminal C, the VSS terminal of the digital potentiometer U2 is grounded, the VCC terminal of the digital potentiometer U2 is connected with a +5V power supply terminal, the CS terminal of the digital potentiometer U2 is connected with the P2.2 terminal of the singlechip U1, the VL terminal of the digital potentiometer U2 is grounded, the VW terminal of the digital potentiometer U2 is connected with the non-inverting input terminal of the amplifier P3, the inverting input terminal of the amplifier P3 is connected with the output terminal of the amplifier P3 and one terminal of the capacitor C5, the other terminal of the capacitor C5 is connected with a resistor R8 connected in series with the varistor RT1, the inverting input terminal of the varistor 4 is connected with the fixed terminal of the varistor P599, the non-inverting input terminal of the amplifier P4 is grounded, and the output terminal of the amplifier P4 is connected to the input terminal of the analog-to-digital conversion circuit through the connection terminal d.
Preferably, the analog-to-digital conversion circuit comprises an amplifier P5, an amplifier P6 and an amplifier P7, a non-inverting input terminal of the amplifier P5 is connected with an output terminal of the amplification circuit through a connection terminal e, an inverting input terminal of the amplifier P5 is connected with an output terminal of the amplifier P5 after being connected with a resistor R11 in series, an output terminal of the amplifier P5 is connected with a non-inverting input terminal of the amplifier P6 after being connected with a capacitor C6 in series, a connection line between the capacitor C6 and the non-inverting input terminal of the amplifier P6 is connected with an anode of a diode D1, a cathode of the diode D1 is connected with the non-inverting input terminal of the amplifier P7, the inverting input terminal of the amplifier P7 is connected with one end of a resistor R9 and an input terminal of a single chip U1 respectively, the other end of the resistor R9 is connected with an output terminal of the amplifier P6, an inverting input terminal of the amplifier P6 is connected with a resistor R12 in series and then connected with a ground, an output terminal of the amplifier P7 is connected with a resistor R10 and then connected with a base of a triode Q1, the collector of transistor Q1 is connected to ground, and the emitter of transistor Q1 is connected to the non-inverting input of amplifier P5.
Preferably, the model of the single chip microcomputer U1 is AT89C51, and the model of the level conversion chip U4 is MAX 220.
Preferably, the model of the digital potentiometer U2 is X9C104, and the models of the amplifier P3 and the amplifier P4 are LM 324.
Compared with the prior art, the utility model has the following beneficial effects:
the utility model relates to a data acquisition instrument with multiple acquisition functions, which comprises a plurality of acquisition interfaces, wherein data acquired by each acquisition interface is transmitted to a filter circuit through a signal selection circuit, the filter circuit filters out high-frequency clutter and low-frequency fluctuation to enable signals to be more stable, the signals are amplified through an amplifying circuit and then output to an analog-to-digital conversion circuit, the conversion circuit converts analog signals into digital electric signals to be output, a singlechip U1 displays the processed digital electric signals through an LCD display screen and sends the digital electric signals to a background server through a wireless communication module, and workers carry out corresponding processing on the digital electric signals. The data acquisition system has the advantages of simple structure, low cost, high feasibility, greatly improved data acquisition efficiency, data acquisition reliability and flexibility, integrated design and high practicability.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings.
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic diagram of the circuit structure of the present invention;
FIG. 3 is a schematic circuit diagram of an optical fiber communication interface circuit according to the present invention;
FIG. 4 is a circuit schematic of the filter circuit of the present invention;
FIG. 5 is a schematic circuit diagram of an amplifier circuit of the present invention;
FIG. 6 is a schematic circuit diagram of an analog-to-digital conversion circuit according to the present invention;
FIG. 7 is a schematic circuit diagram of a single chip microcomputer U1, a wireless communication module and a display circuit in the utility model;
in the figure: the device comprises a sensing device interface 1, an equipment communication interface 2, a data communication interface 3, an analog and digital signal input interface 4, an LCD display screen 5, a signal selection circuit 61, a filter circuit 62, an amplification circuit 63, an analog-to-digital conversion circuit 64, a display circuit 65, a wireless communication module 66 and an optical fiber communication interface circuit 67.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments, but not all embodiments, of the present invention; all other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 and 2, a data acquisition instrument with multiple acquisition functions comprises a housing, wherein a sensing device interface 1, an equipment communication interface 2, a data communication interface 3, an analog and digital signal input interface 4 and an LCD display screen 5 are arranged on the housing, a circuit board in the housing is provided with a signal selection circuit 61, a filter circuit 62, an amplification circuit 63, an analog-to-digital conversion circuit 64, a single chip microcomputer U1, a display circuit 65 and a wireless communication module 66, the sensing device interface 1, the equipment communication interface 2, the data communication interface 3, the analog and digital signal input interface 4 are respectively connected with an input end of the signal selection circuit 61, an output end of the signal selection circuit 61 is sequentially connected with the filter circuit 62, the amplification circuit 63 and the analog-to-digital conversion circuit 64 and an input end of the single chip microcomputer U1, an output end of the single chip microcomputer U1 is connected with a server background through the wireless communication module 66, the output end of the singlechip U1 is connected with the LCD display screen 5 through the display circuit 65.
Specifically, the device comprises a plurality of acquisition interfaces, data acquired by each acquisition interface is transmitted to a filter circuit 62 through a signal selection circuit 61, the filter circuit 62 filters out clutter of high frequency and fluctuation of low frequency to enable the signals to be more stable, the signals are amplified through an amplifying circuit 63 and then output to an analog-to-digital conversion circuit 64, the conversion circuit converts analog signals into digital electric signals to be output, a single chip microcomputer U1 displays the processed digital electric signals through an LCD display screen 5 and sends the digital electric signals to a background server through a wireless communication module 66, and workers carry out corresponding processing, the device can carry out data acquisition and control on various traditional equipment and parameters through a sensing device interface 1, an equipment communication interface 2, a data communication interface 3 and an analog and digital signal input interface 4 and can also communicate with a plurality of intelligent equipment to acquire acquired data, the data acquisition system has the advantages of simple structure, low cost, high feasibility, greatly improved data acquisition efficiency, data acquisition reliability and flexibility, integrated design and high practicability.
As shown in fig. 3, the housing is further provided with an optical fiber communication interface J1, the circuit board is further provided with an optical fiber communication interface circuit 67, and the output end of the single chip microcomputer U1 is connected with the background server through the optical fiber communication interface circuit 67 and the optical fiber communication interface J1 in sequence.
The optical fiber communication interface circuit 67 comprises a level conversion chip U4, the type of the single chip microcomputer U1 is AT89C51, the type of the level conversion chip U4 is MAX220, the C1+ end of the level conversion chip U4 is connected in series with an electrolytic capacitor E2 and then connected with the C1-end of the level conversion chip U4, the V + end of the level conversion chip U4 is connected in series with an electrolytic capacitor E1 and then grounded, the C2+ end of the level conversion chip U4 is connected in series with an electrolytic capacitor E3 and then connected with the C2-end of the level conversion chip U4, the V-end of the level conversion chip U4 is connected in series with an electrolytic capacitor E4 and then grounded, the VCC end of the level conversion chip U4 is respectively connected with a +5V power supply terminal and one end of the electrolytic capacitor E4, the other end of the electrolytic capacitor E4 is connected with the GND terminal of the level conversion chip U4 and then grounded, the T1OUT end of the level conversion chip U4 is connected with the second connection terminal 4 of the optical fiber communication interface 4, and the third connection terminal 4 of the optical fiber communication interface 4, a first connecting terminal of the optical fiber communication interface J1 is connected with a +5V power supply end, a fifth connecting terminal of the optical fiber communication interface J1 is grounded, an R1OUT end of the level conversion chip U4 is connected with a P1.2 end of the single chip microcomputer U1, and a T1IN end of the level conversion chip U4 is connected with a P1.1 end of the single chip microcomputer U1; specifically, an R1OUT end and a T1IN end of a level conversion chip U4 receive data processed by a singlechip U1, an electrolytic capacitor E1, an electrolytic capacitor E2, an electrolytic capacitor E3 and an electrolytic capacitor E4 form a charge pump part of the level conversion chip U4, a +5V power supply is converted into a +/-12V power supply, the data processed by the singlechip U1 is sent to a background server through an optical fiber communication interface J1, the data transmission reliability is further guaranteed through wired connection, monitoring personnel of the background server can master data of collected equipment in time and take corresponding measures to adjust and control in time, accidents are avoided, and the safe operation of a power grid is guaranteed.
As shown in fig. 4, the filter circuit 62 includes an amplifier P1 and an amplifier P2, a non-inverting input terminal of the amplifier P1 is connected in series with a resistor R3 and a resistor R1in sequence and then connected to an output terminal of the signal selection circuit, a connection line between the resistor R3 and the resistor R1 is connected in series with a capacitor C1 and then grounded, a series circuit composed of the capacitor C1 and the capacitor C1 is connected in parallel with both ends of the series circuit composed of the resistor R1 and the resistor R1, a connection line between the capacitor C1 and the capacitor C1 is connected in series with the non-inverting input terminal of the amplifier P1 and then connected to an output terminal of the amplifier P1, an inverting input terminal of the amplifier P1 is connected in series with the resistor R1 and then connected to a connection line between the inverting input terminal of the amplifier P1 and the resistor R1 and then connected to an output terminal of the amplifier P1, an output terminal of the amplifier P1 is connected to the connection line between the resistor R1 and the non-inverting input terminal of the amplifier P1, the inverting input end of the amplifier P2 is connected with the output end of the amplifier P2 and the connecting terminal b after being connected with the resistor R6 in series, the capacitor C4 is connected with the two ends of the resistor R6 in parallel, and the output end of the filter circuit 62 is connected with the input end of the amplifying circuit 63 through the connecting terminal b; the filtering circuit 62 can filter out clutter of high frequency and fluctuation of low frequency, so that the signal is more stable.
As shown in fig. 5, the amplifying circuit 63 includes a digital potentiometer U2, an amplifier P3, an amplifier P4, the type of the digital potentiometer U2 is X9C104, the types of the amplifier P3 and the amplifier P4 are both LM324, the INC terminal of the digital potentiometer U2 is connected to the P2.1 terminal of the monolithic computer U1, the U/D terminal of the digital potentiometer U2 is connected to the P2.0 terminal of the monolithic computer U1, the VH terminal of the digital potentiometer U2 is connected to the output terminal of the filter circuit through a connection terminal C, the VSS terminal of the digital potentiometer U2 is grounded, the VCC terminal of the digital potentiometer U2 is connected to the +5V power supply terminal, the CS terminal of the digital potentiometer U2 is connected to the P2.2 terminal of the monolithic computer U1, the VL terminal of the digital potentiometer U2 is grounded, the VW terminal of the digital potentiometer U2 is connected to the non-inverting input terminal of the amplifier P3, the inverting terminal of the amplifier P3 is connected to the input terminal of the amplifier P3, the RT 2C terminal of the resistor R8653 and the sliding resistor 8653, the fixed end of the slide rheostat RT1 is connected with the inverting input terminal of the amplifier P4, the non-inverting input terminal of the amplifier P4 is grounded, and the output terminal of the amplifier P4 is connected with the input terminal of the analog-to-digital conversion circuit 64 through the connection terminal d.
Specifically, the model is X9C104 digital potentiometer U2, which is a novel CMOS digital and analog mixed signal processing integrated circuit replacing the traditional mechanical potentiometer, the digital potentiometer U2 can adjust the electric quantity output, the digital potentiometer is controlled by digital input to generate an analog quantity output, the maximum value of the tap current can be hundreds of microamperes to a few milliamperes according to the difference of the digital potentiometers, and the digital potentiometer adopts a numerical control mode to adjust the resistance value, so that the digital potentiometer has the remarkable advantages of flexible use, high adjustment precision, no contact, low noise, difficult fouling, vibration resistance, interference resistance, small volume, long service life and the like; amplifiers P3, P4, capable of amplifying signals, can operate with power supplies as low as 3.0 volts or as high as 32 volts, and the common mode input range includes a negative supply, thus eliminating the need for external biasing elements in many applications.
As shown in fig. 6, the analog-to-digital conversion circuit 64 includes an amplifier P5, an amplifier P6 and an amplifier P7, the non-inverting input terminal of the amplifier P5 is connected to the output terminal of the amplifying circuit 63 through a connection terminal e, the inverting input terminal of the amplifier P5 is connected to the output terminal of the amplifier P5 after being connected in series with a resistor R11, the output terminal of the amplifier P5 is connected to the non-inverting input terminal of the amplifier P6 after being connected in series with a capacitor C6, a connection line between the capacitor C6 and the non-inverting input terminal of the amplifier P6 is connected to the anode of a diode D1, the cathode of the diode D1 is connected to the non-inverting input terminal of the amplifier P7, the inverting input terminal of the amplifier P7 is connected to one end of a resistor R9 and the P1.5 end of the monolithic computer 695u 2, the other end of the resistor R9 is connected to the output terminal of the amplifier P6, the inverting input terminal of the amplifier P12 is connected to the ground after being connected to the resistor R12, the output terminal of the amplifier P7 is connected to the base of the transistor Q1 after being connected in series with the resistor R10, the collector of the triode Q1 is grounded, and the emitter of the triode Q1 is connected with the non-inverting input end of the amplifier P5; specifically, an amplifier P5 and a resistor R11 of the analog-to-digital conversion circuit 64 form a buffer isolation circuit, the amplifier P6, the amplifier P7 and the diode D1 form a conversion circuit, the conversion circuit converts an analog signal into a digital electrical signal to be output, the buffer isolation circuit plays a role of starting and stopping, the phenomenon that the analog signal is lost in a front-stage amplification filter circuit can be avoided, distortion of the digital electrical signal converted by the analog-to-digital conversion circuit 64 can be avoided, the analog-to-digital conversion circuit 64 sends the processed digital electrical signal to a P1.5 end of the single chip microcomputer U1, and the single chip microcomputer U1 performs data processing.
As shown in fig. 7, the wireless communication module 66 includes a wireless communication chip U3 with a model nRF401, and is in communication connection with the background server by using the wireless communication chip U3, and the wireless communication module 66 is an existing module, and the specific operation process of wireless transmission is not described herein again.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the utility model has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. The utility model provides a data acquisition instrument of multiple collection function, includes the casing, its characterized in that: the shell is provided with a sensing device interface (1), an equipment communication interface (2), a data communication interface (3), an analog and digital signal input interface (4) and an LCD display screen (5), a circuit board in the shell is provided with a signal selection circuit (61), a filter circuit (62), an amplification circuit (63), an analog-to-digital conversion circuit (64), a singlechip U1, a display circuit (65) and a wireless communication module (66), the sensing device interface (1), the equipment communication interface (2), the data communication interface (3) and the analog and digital signal input interface (4) are respectively connected with the input end of the signal selection circuit (61), the output end of the signal selection circuit (61) is sequentially connected with the filter circuit (62), the amplification circuit (63) and the analog-to-digital conversion circuit (64) and the input end of the singlechip U1, and the output end of the singlechip U1 is connected with a background server through the wireless communication module (66), the output end of the singlechip U1 is connected with an LCD display screen (5) through a display circuit (65).
2. The data acquisition instrument with multiple acquisition functions according to claim 1, wherein: the shell is further provided with an optical fiber communication interface J1, the circuit board is further provided with an optical fiber communication interface circuit (67), and the output end of the single chip microcomputer U1 is connected with the background server sequentially through the optical fiber communication interface circuit (67) and the optical fiber communication interface J1.
3. The data acquisition instrument with multiple acquisition functions according to claim 2, wherein: the optical fiber communication interface circuit (67) comprises a level conversion chip U4, a C1+ end of a level conversion chip U4 is connected with a C1-end of a level conversion chip U4 after being connected with an electrolytic capacitor E2 in series, a V + end of a level conversion chip U4 is connected with an electrolytic capacitor E1 in series and then grounded, a C2+ end of a level conversion chip U4 is connected with an electrolytic capacitor E3 in series and then connected with a C2-end of a level conversion chip U4, a V-end of a level conversion chip U4 is connected with an electrolytic capacitor E4 in series and then grounded, a VCC end of the level conversion chip U4 is respectively connected with a +5V power supply end and one end of an electrolytic capacitor E5, the other end of an electrolytic capacitor E5 is connected with a level conversion chip U4 and then grounded, a T1OUT end of a level conversion chip U4 is connected with a second power supply end of an optical fiber communication interface J1, an R1 end of a level conversion chip U4 is connected with a third power supply end 3687458 of an optical fiber communication interface J1 and a GND communication interface 1 is connected with a first GND communication interface 1, the fifth wiring terminal of the optical fiber communication interface J1 is grounded, the R1OUT end of the level conversion chip U4 is connected with the P1.2 end of the single chip microcomputer U1, and the T1IN end of the level conversion chip U4 is connected with the P1.1 end of the single chip microcomputer U1.
4. The data acquisition instrument with multiple acquisition functions according to claim 1, wherein: the filter circuit (62) comprises an amplifier P1 and an amplifier P2, wherein the non-inverting input end of the amplifier P1 is connected with the output end of the signal selection circuit after being connected with a resistor R3 and a resistor R1in series in sequence, a connecting line between the resistor R3 and the resistor R1 is connected with the output end of the signal selection circuit after being connected with a capacitor C1 in series and then is grounded, a series circuit formed by the capacitor C1 and the capacitor C1 is connected with two ends of the series circuit formed by the resistor R1 and the resistor R1in parallel, a connecting line between the capacitor C1 and the capacitor C1 is connected with the non-inverting input end of the amplifier P1 in series and then is connected with the output end of the amplifier P1, the inverting input end of the amplifier P1 is connected with the series with the resistor R1 and then is grounded, a connecting line between the inverting input end of the amplifier P1 and the inverting input end of the amplifier P1 is connected with the connecting line of the amplifier P1 in series and then is connected with the non-inverting input end of the amplifier P1 and then is connected with the amplifier P1, the inverting input end of the amplifier P2 is connected with the output end of the amplifier P2 and the connecting terminal b after being connected with the resistor R6 in series, the capacitor C4 is connected with the two ends of the resistor R6 in parallel, and the output end of the filter circuit (62) is connected with the input end of the amplifying circuit (63) through the connecting terminal b.
5. The data acquisition instrument with multiple acquisition functions according to claim 1, wherein: the amplifying circuit (63) comprises a digital potentiometer U2, an amplifier P3 and an amplifier P4, wherein the INC end of the digital potentiometer U2 is connected with the P2.1 end of the singlechip U1, the U/D end of the digital potentiometer U2 is connected with the P2.0 end of the singlechip U1, the VH end of the digital potentiometer U2 is connected with the output end of the filter circuit through a connecting terminal C, the VSS end of the digital potentiometer U2 is grounded, the VCC end of the digital potentiometer U2 is connected with a +5V power supply end, the CS end of the digital potentiometer U2 is connected with the P2.2 end of the singlechip U1, the VL end of the digital potentiometer U2 is grounded, the VW end of the digital potentiometer U2 is connected with the non-inverting input end of the amplifier P3, the inverting input end of the amplifier P3 is respectively connected with the output end of the amplifier P3 and one end of the capacitor C5, the other end of the capacitor C5 is connected with a resistor R8 connected with a sliding RT1, and the inverting input end of the sliding resistor RT1, the non-inverting input of the amplifier P4 is grounded, and the output of the amplifier P4 is connected to the input of the analog-to-digital conversion circuit (64) through a terminal d.
6. The data acquisition instrument with multiple acquisition functions according to claim 1, wherein: the analog-to-digital conversion circuit (64) comprises an amplifier P5, an amplifier P6 and an amplifier P7, wherein the non-inverting input end of the amplifier P5 is connected with the output end of the amplifying circuit (63) through a connecting terminal e, the inverting input end of the amplifier P5 is connected with the output end of the amplifier P5 after being connected in series with a resistor R11, the output end of the amplifier P5 is connected with the non-inverting input end of the amplifier P6 after being connected in series with a capacitor C6, the connecting line between the capacitor C6 and the non-inverting input end of the amplifier P6 is connected with the anode of a diode D1, the cathode of the diode D1 is connected with the non-inverting input end of the amplifier P7, the inverting input end of the amplifier P7 is connected with one end of a resistor R9 and the P1.5 end of a singlechip 695U 2, the other end of the resistor R9 is connected with the output end of the amplifier P6, the inverting input end of the amplifier P12 is connected with the resistor R12 and then connected with the ground, the output end of the amplifier P7 is connected with the base of a triode Q1 after being connected in series with the resistor R10, the collector of transistor Q1 is connected to ground, and the emitter of transistor Q1 is connected to the non-inverting input of amplifier P5.
7. The data acquisition instrument with multiple acquisition functions according to claim 3, wherein: the model of the singlechip U1 is AT89C51, and the model of the level conversion chip U4 is MAX 220.
8. The data acquisition instrument with multiple acquisition functions according to claim 5, wherein: the model of the digital potentiometer U2 is X9C104, and the models of the amplifier P3 and the amplifier P4 are both LM 324.
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| CN116131937A (en) * | 2023-01-09 | 2023-05-16 | 深圳市光派通信技术有限公司 | Semi-active power acquisition circuit and active wavelength division device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116131937A (en) * | 2023-01-09 | 2023-05-16 | 深圳市光派通信技术有限公司 | Semi-active power acquisition circuit and active wavelength division device |
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