CN217789656U - Level shifter and electronic device - Google Patents

Abstract

A level shifter and an electronic apparatus, the level shifter including an input unit, an output unit, a first control unit, and a second control unit; the input unit receives a first driving voltage and comprises a first input transistor and a second input transistor; the output unit comprises a first output transistor and a second output transistor; the first control unit is directly connected between the input unit and the output unit and includes a first bias transistor connected between the first input transistor and the second output transistor and a second bias transistor connected between the second input transistor and the first output transistor; the second control unit receives the second driving voltage and supplies it to the output unit, and includes a third bias transistor connected between the second driving voltage terminal and the first output transistor and a fourth bias transistor connected between the second driving voltage terminal and the second output transistor. The level shifter circuit is simple, and has high-speed conversion and strong driving capability.

Description

Level shifter and electronic device

Technical Field

Embodiments of the present disclosure relate to a level shifter and an electronic apparatus.

Background

With the rapid development of display technology, a large number of driving circuits are required to improve the color depth, resolution, and other properties of the display device. On the one hand, in order to make the display device thinner and lighter, the size of the driving circuit in the display device needs to be reduced, and on the other hand, in order to reduce the power consumption of the display device, the driving voltage needs to be set lower. However, the scanning signal line driving circuit and the data signal line driving circuit in the display device require high operating voltages, and low voltage signals input from the peripheral circuits cannot normally operate the scanning signal line driving circuit and the data signal line driving circuit in the display device due to the reduced driving voltages. Therefore, it is necessary to use a level shifter to raise the low voltage signal input from the peripheral circuit to the high operating voltage required by the driving circuit.

A large number of level shifters are required in the display integrated circuit to receive an input signal of a low voltage level and to convert the input signal of the low voltage level into an output signal of a high voltage level. The level shifter is usually composed of a plurality of MOS transistors. The larger the source-drain voltage difference, the larger the channel length and the channel width of the MOS transistor, the larger the size of the chip, and the economic cost of the chip are increased.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, embodiments of the present disclosure provide a level shifter and an electronic device including the level shifter to make a chip smaller in size while ensuring a higher level shift rate and higher circuit stability.

Some embodiments of the present disclosure provide a level shifter, including: an input unit receiving a first driving voltage from a first driving voltage terminal, and including: a first input transistor electrically connected to the first input terminal to receive a first input signal; and a second input transistor electrically connected to the second input terminal to receive a second input signal that is inverted from the first input signal; an output unit including: a first output transistor electrically connected to a first output terminal to output a first output signal at the first output terminal; and a second output transistor electrically connected to a second output terminal to output a second output signal in phase opposition to the first output signal at the second output terminal; a first control unit directly connected between the input unit and the output unit, and including: a first bias transistor connected between the first input transistor and the second output transistor, and a second bias transistor connected between the second input transistor and the first output transistor, wherein the first bias transistor and the second bias transistor are controlled by a first bias voltage; and a second control unit receiving a second driving voltage from a second driving voltage terminal and providing the second driving voltage to the output unit, and including: a third bias transistor connected between the second driving voltage terminal and the first output transistor, and a fourth bias transistor connected between the second driving voltage terminal and the second output transistor, wherein the third bias transistor and the fourth bias transistor are controlled by a second bias voltage.

For example, some embodiments of the present disclosure provide a level shifter, wherein a source of the first input transistor is connected to the first driving voltage terminal, a drain of the first input transistor is connected to a source of the first bias transistor, a gate of the first input transistor is connected to the first input terminal, and a source of the second input transistor is connected to the first driving voltage terminal, a drain of the second input transistor is connected to a source of the second bias transistor, a gate of the second input transistor is connected to the second input terminal, wherein the first driving voltage is lower than the second driving voltage.

For example, some embodiments of the present disclosure provide a level shifter, wherein the source of the first output transistor is electrically connected to the drain of the third bias transistor, the drain of the first output transistor is electrically connected to the first output terminal, the gate of the first output transistor is connected to the second output terminal, and the source of the second output transistor is electrically connected to the drain of the fourth bias transistor, the drain of the second output transistor is electrically connected to the second output terminal, and the gate of the second output transistor is connected to the first output terminal.

For example, in some embodiments of the present disclosure, a level shifter is provided, in which the first input transistor and the second input transistor are NPN transistors, and the first output transistor and the second output transistor are PNP transistors.

For example, some embodiments of the present disclosure provide a level shifter, wherein a drain of the first bias transistor is connected to the second output terminal, a drain of the second bias transistor is connected to the first output terminal, and a gate of the first bias transistor and a gate of the second bias transistor are connected together at a first bias voltage terminal.

For example, some embodiments of the present disclosure provide a level shifter, wherein the source of the third bias transistor and the source of the fourth bias transistor are connected together at the second driving voltage terminal, and the gate of the third bias transistor and the gate of the fourth bias transistor are connected together at the second bias voltage terminal.

For example, in some embodiments of the present disclosure, a level shifter is provided, in which the first bias transistor and the second bias transistor are NPN transistors, and the third bias transistor and the fourth bias transistor are PNP transistors.

For example, some embodiments of the present disclosure provide a level shifter in which the first input transistor and the second input transistor are smaller in size than the first output transistor or the second output transistor.

Some embodiments of the present disclosure further provide an electronic device including the level shifter according to any one of the embodiments of the present disclosure.

For example, in an electronic device provided in some embodiments of the present disclosure, the electronic device is a source driver.

The level shifter provided by the embodiment of the disclosure has a simple circuit structure, a smaller circuit size and a higher slew rate, can perform level shifting on a high-speed signal under a larger voltage difference condition, and effectively reduces peak currents of AVDD and GND.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

FIG. 1A is a circuit diagram of a level shifter;

FIG. 1B is a waveform diagram of an output signal of the level shifter shown in FIG. 1A;

FIG. 1C is a circuit diagram of another level shifter;

fig. 2 is a circuit diagram of a level shifter according to at least one embodiment of the present disclosure;

fig. 3A and fig. 3B are schematic diagrams illustrating PVT test characteristics of a level shifter according to at least one embodiment of the present disclosure;

fig. 4 is a schematic diagram of a source driver according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and the like in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The present disclosure is illustrated by the following specific examples. In order to keep the following description of the disclosed embodiments clear and concise, a detailed description of known functions and known parts (elements) may be omitted. When any element of an embodiment of the present disclosure appears in more than one drawing, that element is identified in each drawing by the same or similar reference numeral.

Fig. 1A shows a general circuit configuration of a conventional level shifter. The level shifter shown in fig. 1A includes: a first driving voltage terminal GND as a ground terminal, a second driving voltage terminal AVDD to which a driving voltage is supplied, transistors M1 and M2 connected to the second driving voltage terminal, and transistors M3 and M4 connected to the first driving voltage terminal.

The gate of the transistor M3 is connected to the first input terminal In, the first input signal inputted by the first input terminal In is a low-voltage input signal, and the source of the transistor M3 is connected to the first driving voltage terminal GND, for example, the first driving voltage terminal GND may be a ground terminal, and the first driving voltage terminal GND may be 0V, for example.

The gate of the transistor M4 is connected to the second input terminal InB, a second input signal input from the second input terminal InB is inverted with respect to the first input signal input from the first input terminal In, for example, the second input terminal InB is connected to the first input terminal In through an inverter, so that the second input signal and the first input signal are inverted. The source of the transistor M4 is connected to the first driving voltage terminal GND to receive the first driving voltage from the first driving voltage terminal GND.

The sources of the transistors M1 and M2 are both connected to the second driving voltage terminal AVDD to receive a second driving voltage, which may be 18V, for example, from the second driving voltage terminal AVDD. The gate of the transistor M1 is connected to the drain of the transistor M4, the gate of the transistor M2 is connected to the drain of the transistor M3, meanwhile, the gate of the transistor M1 is also connected to the first output terminal Out, the gate of the transistor M2 is also connected to the second output terminal OutB, the first output signal output by the first output terminal Out is inverted with the second output signal output by the second output terminal OutB, for example, the first output terminal Out is connected to the second output terminal OutB through an inverter, so that the second output signal is inverted with the first output signal.

In the level shifter shown in fig. 1A, the transistor M3 and the transistor M4 are NPN-type transistors, and the transistor M1 and the transistor M2 are PNP-type transistors.

Therefore, when the first input signal at the first input terminal In is at a high level (e.g., 1.8V), the transistor M3 is turned on, and since the second input signal at the second input terminal InB is inverted from the first input signal, the second input signal is at a low level, and the transistor M4 is turned off. The drain of the transistor M3 is connected to the gate of the transistor M2, and the drain terminal voltage of the transistor M3 is pulled low by the first driving voltage terminal GND, so that the transistor M2 is turned on, the first output terminal Out outputs a first output signal driven by the second driving voltage terminal AVDD, the first output signal is a high-voltage output signal converted by the level converter, and the second output terminal OutB outputs a low-voltage output signal having a phase opposite to that of the first output terminal Out.

When the first input signal at the first input end In is at a low level, the transistor M3 is turned off, since the second input signal at the second input end InB is at a low level due to the phase inversion of the first input signal, the transistor M4 is turned on, the voltage at the drain end of the transistor M4 is pulled low by the first driving voltage end GND, the PNP transistor M1 is turned on, the second output end OutB outputs the second output signal driven by the second driving voltage end AVDD, the second output signal is a high voltage output signal, and therefore the first output signal output by the first output end Out is a low voltage output signal.

In the level shifter shown in fig. 1A, since the input transistors M3 and M4 are high voltage transistors, the frequency of the input signal is limited, so that the response speed of the level shifter is slow.

When the level shifter shown in fig. 1A is verified at PVT (process/voltage/temperature), for example, when operating under typical conditions, as shown in fig. 1B, the rising time and the falling time of the first output signal of the first output terminal Out or the second output signal of the second output terminal OutB may be lengthened, and the overlap interval may be lengthened, and in addition, the deviation between the rising time and the falling time of the output signal may be large.

Fig. 1C shows a level shifter having an improved circuit configuration, and compared to fig. 1A, the level shifter further includes a transistor M5 connected between the first input terminal In and the second output terminal OutB, and a transistor M6 connected between the second input terminal InB and the first output terminal Out, the transistor M5 and the transistor M6 being NPN transistors, and gates of both being controlled by an N-type bias voltage.

As shown in fig. 1C, the source of the transistor M5 is connected to the drain of the transistor M3, and the drain of the transistor M5 is connected to the second output terminal OutB and also to the drain of the transistor M1. The source of the transistor M6 is connected to the drain of the transistor M4, and the drain of the transistor M6 is connected to the first output terminal Out and also to the drain of the transistor M2. In addition to the above circuit structures, the other circuit structures in fig. 1C can refer to the description of fig. 1A, and are not repeated herein.

Compared with the conventional level shifter shown in fig. 1A, the level shifter in fig. 1C can reduce the peak current of GND to some extent, but cannot control the peak current of AVDD. Under this circuit configuration, since the input transistors M3 and M4 are both low voltage transistors, in some cases, the voltage fluctuation of AVDD may cause the drain voltage applied to the low voltage transistors M3 and M4 to be higher than the breakdown voltage of the transistors M3 and M4, thereby damaging the transistors M3 and M4, so that the level shifter may not operate normally.

At least one embodiment of the present disclosure provides a level shifter having a simple circuit structure, a small circuit size, and a high slew rate, capable of level-shifting a high-speed signal under a large voltage difference condition, and effectively reducing peak currents of AVDD and GND.

At least one embodiment of the present disclosure provides a level shifter, as shown in fig. 2, including: an input unit 10, an output unit 20, a first control unit 30 and a second control unit 40.

For example, the input unit 10 receives a first driving voltage from the first driving voltage terminal GND, and for example, includes a first input transistor M9 and a second input transistor M10.

For example, the first input transistor M9 is electrically connected to the first input terminal In to receive a first input signal, and the second input transistor M10 is electrically connected to the second input terminal InB to receive a second input signal that is inverted from the first input signal. For example, the second input signal may be inverted with respect to the first input signal.

For example, the gate of the first input transistor M9 may be configured to be connected to the first input terminal In and receive the first input signal, and the source of the first input transistor M9 may be configured to be electrically connected to the first node N1 to receive the first driving voltage from the first driving voltage terminal GND. For example, the gate of the second input transistor M10 may be configured to be connected to the second input terminal InB and receive the second input signal, and the source of the second input transistor M10 may be configured to be electrically connected to the first node N1 to receive the first driving voltage from the first driving voltage terminal GND.

For example, the first driving voltage may be a ground voltage, e.g., the first driving voltage is 0V.

For example, the output unit 20 may receive the second driving voltage from the second driving voltage terminal AVDD, and output the first output signal through the first output terminal Out and the second output signal through the second output terminal OutB based on the first input signal and the second input signal of the input unit 10. For example, the second driving voltage is higher than the first driving voltage, for example, the second driving voltage is 18V.

For example, the output unit 20 includes a first output transistor M4 and a second output transistor M3. For example, the first output transistor M4 is electrically connected to the first output terminal Out to output a first output signal at the first output terminal Out. For example, the second output transistor M3 is electrically connected to the second output terminal OutB to output a second output signal at the second output terminal OutB that is inverted from the first output signal.

For example, the first output transistor M4 may be electrically connected between the second driving node N2 and the first output node O1, for example, the source of the first output transistor M4 may be configured to be electrically connected to the second driving node N2, and the drain of the first output transistor M4 may be configured to be electrically connected to the first output node O1, for example, the gate of the first output transistor M4 may be configured to be electrically connected to the second output terminal OutB, for example, the gate of the first output transistor M4 may be configured to be electrically connected to the second output node O2.

For example, the second output transistor M3 may be electrically connected between the second driving node N2 and the second output node O2, for example, a source of the second output transistor M3 may be configured to be electrically connected to the second driving node N2, a drain of the second output transistor M3 may be configured to be electrically connected to the second output node O2, for example, a gate of the second output transistor M3 may be configured to be electrically connected to the first output terminal Out, for example, a gate of the second output transistor M3 may be configured to be electrically connected to the first output node O1.

For example, the first and second input transistors M9 and M10 may be NPN-type transistors, and the first and second output transistors M4 and M3 may be PNP-type transistors.

For example, the first control unit 30 is directly connected between the input unit 10 and the output unit 20, and may control voltage drops between the first and second output terminals and the input unit 10 based on the first Bias voltage N-Bias.

For example, the first control unit 30 includes a first Bias transistor M5 and a second Bias transistor M6, and gates of the first Bias transistor M5 and the second Bias transistor M6 are connected to the first Bias voltage terminal to receive the first Bias voltage N-Bias.

For example, the first bias transistor M5 is directly connected between the first input transistor M9 and the second output transistor M3, for example, the source of the first bias transistor M5 may be configured to be directly connected with the drain of the first input transistor M9 of the input unit 10, and the drain of the first bias transistor M5 may be configured to be directly connected with the second output node O2, that is, the drain of the first bias transistor M5 may be configured to be directly connected with the drain of the second output transistor M3.

For example, the second bias transistor M6 is directly connected between the second input transistor M10 and the first output transistor M4, for example, the source of the second bias transistor M6 may be configured to be directly connected with the drain of the second input transistor M10 of the input unit 10, and the drain of the second bias transistor M6 may be configured to be directly connected with the first output node O1, that is, the drain of the second bias transistor M6 may be configured to be directly connected with the drain of the first output transistor M4.

For example, the first control unit 30 may make the voltage level of the drain terminal of the first input transistor M9 of the input unit 10 lower than the voltage level at the second output node O2, e.g., the first control unit 30 may make the voltage level of the drain terminal of the second input transistor M10 of the input unit 10 lower than the voltage level at the first output node O1. The first input transistor M9 and the second input transistor M10 may be protected by properly designing the first Bias voltage N-Bias, for example, the source voltages of the first Bias transistor M5 and the second Bias transistor M6 may be lower than the breakdown voltages of the first input transistor M9 and the second input transistor M10 by designing the first Bias voltage N-Bias to prevent the first input transistor M9 and the second input transistor M10 from being damaged by voltage fluctuation of the second driving voltage terminal or by high-level output voltages of the first output terminal Out and the second output terminal OutB.

For example, the second control unit 40 is connected between the second driving node N2 and the output unit 20, and may control voltage drops between the first and second output terminals and the second driving voltage terminal based on the second Bias voltage P-Bias.

For example, the second control unit 40 includes a third Bias transistor M2 and a fourth Bias transistor M1, and gates of the third Bias transistor M2 and the fourth Bias transistor M1 are connected to the second Bias voltage terminal to receive the second Bias voltage P-Bias.

For example, the third bias transistor M2 is connected between the second driving node N2 and the first output transistor M4, for example, a source of the third bias transistor M2 may be configured to be connected to the second driving voltage terminal, and a drain of the third bias transistor M2 may be configured to be connected to a source of the first output transistor M4 of the output unit 20.

For example, the fourth bias transistor M1 is connected between the second driving node N2 and the second output transistor M3, e.g., a source of the fourth bias transistor M1 may be configured to be connected to the second driving voltage terminal, and a drain of the fourth bias transistor M1 may be configured to be connected to a source of the second output transistor M3 of the output unit 20.

For example, the second control unit 40 may make the output voltage level of the output unit 20 lower than the voltage level of the second driving voltage terminal based on the control of the second Bias voltage P-Bias, e.g., the second control unit 40 may make the output signals of the first output terminal Out and the second output terminal OutB drop to about 15V.

For example, the first and second biasing transistors M5 and M6 may be NPN-type transistors, and the third and fourth biasing transistors M2 and M1 may be PNP-type transistors.

For example, the first input transistor M9 and the second input transistor M10 in the input unit 10 may each be a low voltage transistor (LV-TR). For example, the first output transistor M4 and the second output transistor M3 in the output unit 20 may each be a high voltage transistor (HV-TR).

For example, the first and second bias transistors M5 and M6 in the first control unit 30 may each be a medium-voltage transistor (MV-TR) or a high-voltage transistor.

For example, the third bias transistor M2 and the fourth bias transistor M1 in the second control unit 40 may each be a medium voltage transistor or a high voltage transistor.

In at least some embodiments of the present disclosure, the low voltage transistors employed may have a threshold voltage of, for example, 4V or less, the high voltage transistors may have a threshold voltage of, for example, 18V or more, and the intermediate voltage transistors may have a threshold voltage between that of the low voltage transistors and that of the high voltage transistors, for example, the intermediate voltage transistors may have a threshold voltage of, for example, 10V.

The size of the low-voltage transistor in at least one embodiment of the present disclosure is smaller than the size of the medium-voltage transistor, which is smaller than the size of the high-voltage transistor, for example, the channel width of the low-voltage transistor is smaller than the channel width of the medium-voltage transistor, which is smaller than the channel width of the high-voltage transistor.

For example, the channel widths of the first and second input transistors M9 and M10 in the input unit 10 are smaller than the channel widths of the first and second output transistors M4 and M3 in the output unit 20. Therefore, the level shifter in at least one embodiment of the present disclosure may have a smaller size, so that the size of the whole chip in the display device can be effectively reduced.

The transistors employed by the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor (e.g., MOS field effect transistor) or other transistors of the same characteristics. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. Embodiments of the present disclosure do not limit the type of transistors employed.

For example, the NPN transistor in at least one embodiment of the present disclosure may be an N-channel MOS transistor (NMOS-TR), and the PNP transistor may be a P-channel MOS transistor (PMOS-TR).

For convenience of description, the low-voltage N-channel MOS transistor may be denoted as "LV-NMOS-TR", the medium-voltage N-channel MOS transistor may be denoted as "MV-NMOS-TR", and the high-voltage N-channel MOS transistor may be denoted as "HV-NMOS-TR". Similarly, the low, middle and high voltage P-channel MOS transistors can be respectively expressed as "LV-PMOS-TR", "MV-PMOS-TR" and "HV-PMOS-TR".

For example, in one example of the present disclosure, the first and second input transistors M9 and M10 are low-voltage N-channel MOS transistors (LV-NMOS-TR), and the first and second output transistors M4 and M3 are high-voltage P-channel MOS transistors (HV-PMOS-TR). For example, the first and second bias transistors M5 and M6 are medium voltage N-channel MOS transistors (MV-NMOS-TR), and the third and fourth bias transistors M2 and M1 are medium voltage P-channel MOS transistors (MV-PMOS-TR).

For example, in this example, the first control unit 30 may control the gate voltage of the MV-NMOS-TR based on the first Bias voltage N-Bias to control and reduce the peak current of GND, and the second control unit 40 may control the gate voltage of the MV-PMOS-TR based on the second Bias voltage P-Bias to control and reduce the peak current of AVDD.

For example, the level shifter of at least one embodiment of the present disclosure may further control a voltage slew rate and a peak current of the level shifter by adjusting levels of the first bias voltage and the second bias voltage according to an operating environment of the circuit.

Although it is desirable to design a circuit as fast as possible, the faster the voltage slew rate (slew rate), the higher the slew rate, the increased peak current, and the like, which may cause side effects such as electromagnetic interference (EMI) and an increase in power supply ripple phenomenon, thereby deteriorating the performance of the entire system, and therefore, the level shifter circuit needs to have an appropriate slew rate and be insensitive to PVT variations.

Fig. 3A is a simulation result comparing PVT test characteristics of the level shifter proposed in at least one embodiment of the present disclosure with the conventional level shifter shown in fig. 1A. As shown in fig. 3A, the rising slew rate and the falling slew rate are set to about 10ns, and the level shifter proposed in at least one embodiment of the present disclosure has good circuit simulation results for different PVT variations, such as variations of process, voltage, and temperature. For example, in the cases of "Typical", "Worst", "Best", and "Best", the proposed level shifters of the embodiments of the present disclosure have a higher voltage slew rate, a smaller delay, and smaller peak and average currents.

For example, in a typical case, the AVDD peak current of the level shifter shown in fig. 1A is 65.22ua, and the GND peak current is 52.64uA, while the level shifter proposed by the embodiment of the present disclosure reduces the AVDD peak current to 8.12uA by the second control unit, and reduces the GND peak current to 7.68uA by the first control unit.

For example, in the worst case, the AVDD peak current of the level shifter shown in fig. 1A is 180.10ua, and the GND peak current is 170.30uA, whereas the level shifter proposed in the embodiment of the present disclosure reduces the AVDD peak current to 10.1uA by the second control unit, and reduces the GND peak current to 10.8uA by the first control unit.

Fig. 3B is a simulation result comparing PVT test characteristics of the level shifter and the level shifter shown in fig. 1C according to at least one embodiment of the disclosure. As shown in fig. 3B, in a typical case, the level shifter shown in fig. 2 of the present disclosure has improved delay, peak current, and average current compared to the level shifter shown in fig. 1C.

For example, the level shifter shown in fig. 1C has a significant delay, the rising delay is up to 63.9ns, and the falling delay is up to 39.56ns, while the embodiment of the present disclosure proposes a rising delay of only 10.6ns and a falling delay of only 9.02ns, which indicates that the level shifter of the present disclosure can effectively reduce the delay time.

Although the level shifter shown in fig. 1C also reduces peak currents of AVDD and GND to some extent compared with the level shifter shown in fig. 1A, the embodiment of the present disclosure enables the level shifter to better control and significantly reduce peak currents and average currents of AVDD and GND under the combined action of the first control unit and the second control unit through an improved circuit structure.

For example, as shown in fig. 3B, the AVDD peak current of the level shifter shown in fig. 1C is 54.11ua, the gnd peak current is 35.15uA, while the AVDD peak current of the level shifter of the present disclosure is 8.12ua, and the gnd peak current is 7.68uA.

For example, as shown in fig. 3B, the AVDD average current of the level shifter shown in fig. 1C is 3.312ua, the gnd average current is 3.311uA, while the AVDD average current of the level shifter of the present disclosure is 0.08ua, and the gnd average current is 0.08uA.

Therefore, the level shifter provided in at least one embodiment of the present disclosure has a simple circuit structure and a small circuit size, and also has fast voltage conversion, strong driving capability and good PVT test stability, and can control and reduce peak currents of AVDD and GND by the first bias voltage and the second bias voltage in the first control unit and the second control unit, thereby effectively improving EMI characteristics of the system and improving reliability of the system.

At least one embodiment of the present disclosure further provides an electronic device including the level shifter in any one of the embodiments of the present disclosure. For example, the electronic device is a source driver; alternatively, in another embodiment, the electronic device may be a display device including a source driver including the level shifter in any one of the embodiments of the present disclosure, for example, the display device may be a liquid crystal display device, an organic light emitting display device, an electronic paper display device, or the like.

Fig. 4 is a schematic diagram of a source driver according to at least one embodiment of the present disclosure, the source driver includes a shift register 1110, a first latch unit 1120, a second latch unit 1130, a level shifter 1140, a digital-to-analog converter 1150, and an output buffer unit 1160.

For example, shift register 1110 may receive and generate a shift signal in response to a horizontal clock signal.

For example, the first latch unit 1120 may include a plurality of first latches that synchronize the input image signal with the horizontal clock signal and sample the input image signal in response to the shift signal generated by the shift register 1110.

For example, the second latch unit 1130 may include a plurality of second latches and store the image data output from the first latch unit 1120.

For example, the level shifter 1140 converts the output data voltage of the second latch unit 1130 into a voltage level required for a circuit.

For example, the digital-to-analog converter 1150 converts the digital voltage signal output by the level shifter 1140 into an analog signal.

For example, the output buffer unit 1160 receives and amplifies an analog signal output from the digital-to-analog converter 1150.

The above components of the source driver may be implemented by, for example, a digital circuit and/or an analog circuit, which is not limited by the embodiments of the present disclosure.

For the present disclosure, there are also the following points to be explained:

(1) The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above are merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be determined by the scope of the claims.

Claims (10)

1. A level shifter, comprising:

an input unit receiving a first driving voltage from a first driving voltage terminal, and including:

a first input transistor electrically connected to the first input terminal to receive a first input signal; and

a second input transistor electrically connected to a second input terminal to receive a second input signal that is inverted from the first input signal;

an output unit including:

a first output transistor electrically connected to a first output terminal to output a first output signal at the first output terminal; and

a second output transistor electrically connected to a second output terminal to output a second output signal in phase opposition to the first output signal at the second output terminal;

a first control unit directly connected between the input unit and the output unit, and including:

a first bias transistor connected between the first input transistor and the second output transistor, an

A second bias transistor connected between the second input transistor and the first output transistor, wherein the first bias transistor and the second bias transistor are controlled by a first bias voltage; and

a second control unit receiving a second driving voltage from a second driving voltage terminal and providing the second driving voltage to the output unit, and including:

a third bias transistor connected between the second driving voltage terminal and the first output transistor, an

A fourth bias transistor connected between the second driving voltage terminal and the second output transistor, wherein the third bias transistor and the fourth bias transistor are controlled by a second bias voltage.

2. The level shifter of claim 1, wherein a source of the first input transistor is connected to the first drive voltage terminal, a drain of the first input transistor is connected to a source of the first bias transistor, a gate of the first input transistor is connected to the first input terminal, and

a source of the second input transistor is connected to the first driving voltage terminal, a drain of the second input transistor is connected to a source of the second bias transistor, a gate of the second input transistor is connected to the second input terminal,

wherein the first driving voltage is lower than the second driving voltage.

3. The level shifter according to claim 1 or 2, wherein a source of the first output transistor is electrically connected to a drain of the third bias transistor, a drain of the first output transistor is electrically connected to the first output terminal, a gate of the first output transistor is connected to the second output terminal, and

a source of the second output transistor is electrically connected to a drain of the fourth bias transistor, a drain of the second output transistor is electrically connected to the second output terminal, and a gate of the second output transistor is connected to the first output terminal.

4. The level shifter of claim 3, wherein the first and second input transistors are NPN-type transistors and the first and second output transistors are PNP-type transistors.

5. The level shifter of claim 1, wherein a drain of the first bias transistor is connected to the second output terminal, a drain of the second bias transistor is connected to the first output terminal, and

the grid electrode of the first bias transistor and the grid electrode of the second bias transistor are connected to a first bias voltage end together.

6. The level shifter of claim 1 or 5, wherein the source of the third bias transistor and the source of the fourth bias transistor are connected together at the second driving voltage terminal, and wherein

The grid electrode of the third bias transistor and the grid electrode of the fourth bias transistor are connected to a second bias voltage end together.

7. The level shifter of claim 6, wherein the first and second bias transistors are NPN-type transistors and the third and fourth bias transistors are PNP-type transistors.

8. The level shifter of claim 1, wherein the first input transistor and the second input transistor are smaller in size than the first output transistor or the second output transistor.

9. An electronic device, characterized in that it comprises a level shifter according to claim 1.

10. The electronic device of claim 9, wherein the electronic device is a source driver.

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