CN217789320U - Battery cell protection circuit and battery cell management system - Google Patents
Battery cell protection circuit and battery cell management system Download PDFInfo
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- CN217789320U CN217789320U CN202220233044.9U CN202220233044U CN217789320U CN 217789320 U CN217789320 U CN 217789320U CN 202220233044 U CN202220233044 U CN 202220233044U CN 217789320 U CN217789320 U CN 217789320U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
The utility model discloses an electric core protection circuit, which is connected with an electric core and comprises an electric core protection chip, a first transistor, a second transistor, a third transistor, an electric core interface and a charge-discharge interface; the battery cell protection chip comprises a charging control end and a discharging control end; the first transistor is connected with the discharge control end and the battery cell interface; the second transistor is connected with the charging control end, the first transistor and the third transistor; the third transistor is connected with the charging control end and the charging and discharging interface; when the battery cell is normally charged, the first transistor is conducted, and the second transistor or the third transistor is conducted; and when the battery cell is overcharged, the second transistor and the third transistor which are switched on when the battery cell is normally charged are switched off. According to the technical scheme, overcharge protection can be normally carried out under the condition that one charge protection device fails, the test of charge abuse is realized, the cost of the battery cell protection circuit is reduced, and the occupied area of electronic elements in the battery cell protection circuit is reduced.
Description
Technical Field
The utility model relates to an electricity core control technical field especially relates to an electricity core protection circuit and electric core management system.
Background
When the battery core is subjected to UL2054 authentication at present, the failure rate of an abusive charging test is high, after the abusive charging test requires that a protection device (transistor) in a battery core management system has a fault, the battery core in the battery core management system is charged for a long time by 6V1C/6V2C, and the battery core is required not to be ignited and not to explode.
The existing battery cell protection circuit generally adopts a scheme of double ICs and double transistors to carry out UL2054 authentication on a battery cell, namely, two ICs respectively control two transistors to realize UL2054 authentication of the battery cell. However, the above scheme results in a high cost required for the cell protection circuit and is limited by layout space.
SUMMERY OF THE UTILITY MODEL
An embodiment of the utility model provides an electricity core protection circuit and electric core management system to solve the higher problem of electricity core protection circuit cost.
A battery cell protection circuit is connected with a battery cell and comprises a battery cell protection chip, a first transistor, a second transistor, a third transistor, a battery cell interface and a charge-discharge interface; the battery cell protection chip comprises a charging control end and a discharging control end;
the first transistor is connected with the discharge control end and the battery cell interface;
the second transistor is connected with the charging control end, the first transistor and the third transistor;
the third transistor is connected with the charging control end and the charging and discharging interface;
when the battery cell is normally charged, the first transistor is turned on, and the second transistor or the third transistor is turned on; when the battery cell is overcharged, the second transistor and the third transistor which are not short-circuited when the battery cell is normally charged are disconnected.
Further, the cell protection circuit further comprises a current sampling circuit; the current sampling circuit is respectively connected with the battery cell interface, the first transistor and the battery cell protection chip and is used for collecting real-time current in the battery cell protection circuit and sending the real-time current to the battery cell protection chip.
Further, the current sampling circuit comprises a sampling resistor; the first end of the sampling resistor is connected with the negative electrode of the battery cell and the VSS end of the battery cell protection chip, and the second end of the sampling resistor is connected with the first transistor and the VM end of the battery cell protection chip.
Further, the cell protection circuit further comprises a first current limiting resistor; the first end of the first current-limiting resistor is connected with the positive electrode of the battery cell and the positive electrode of the charging and discharging port, and the second end of the first current-limiting resistor is connected with the VDD end of the battery cell protection chip;
the battery cell protection circuit further comprises a second current-limiting resistor; the first end of the second current-limiting resistor is connected with the negative electrode of the charging and discharging port and the third transistor, and the second end of the second current-limiting resistor is connected with the VM end of the battery cell protection chip.
Further, the cell protection circuit further comprises a first filter capacitor; a first end of the first filter capacitor is connected with a VDD end of the battery cell protection chip, and a second end of the first filter capacitor is connected with a VM end of the battery cell protection chip;
the battery cell protection circuit further comprises a second filter capacitor; and the first end of the second filter capacitor is connected with the second end of the sampling resistor, and the second end of the second filter capacitor is connected with the first end of the second current-limiting resistor.
Further, the cell protection circuit further comprises an electrostatic protection circuit; the first end of the electrostatic protection circuit is connected with a connecting node of the positive pole of the charge-discharge port and the positive pole of the battery cell, and the second end of the electrostatic protection circuit is connected with a connecting node of the second transistor and the negative pole of the charge-discharge port.
Further, the electrostatic protection circuit includes an electrostatic protection capacitor.
Further, the first transistor, the second transistor and the third transistor are MOS transistors.
Further, the first transistor, the second transistor and the third transistor are N-type MOS transistors.
A battery cell management system comprises a battery cell, a charger and the battery cell protection circuit.
The battery cell protection circuit comprises a battery cell protection chip, a first transistor, a second transistor, a third transistor, a battery cell interface and a charge-discharge interface, wherein the first transistor is connected with the discharge control end and the battery cell interface, the second transistor is connected with the charge control end, the first transistor and the third transistor, the third transistor is connected with the charge control end and the charge-discharge interface, when the battery cell is normally charged, the first transistor is switched on, the second transistor or the third transistor is switched on, the battery cell is normally charged, when the battery cell is overcharged, the second transistor and the third transistor which are not short-circuited are switched off when the battery cell is normally charged, the battery cell stops charging, namely, the charge control end of the battery cell protection chip is used for controlling the second transistor and the third transistor, when a charge protection device (the second transistor or the third transistor) fails/is short-circuited, the overcharge test is normally carried out, the overcharge test is realized, and only an IC (the battery cell protection chip) is used, the overcharge test can be realized by the third transistor and the third transistor, the cost of the overcharge protection circuit is reduced, and the occupation area of electronic elements in the battery cell protection circuit is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
Fig. 1 is a schematic circuit diagram of a cell protection circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a cell management system according to an embodiment of the present invention.
In the figure: 10. a cell protection circuit; 11. a battery cell interface; 12. a charge-discharge interface; 13. a current sampling circuit; 14. an electrostatic protection circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under 823030," "under 8230; below," "under 8230," "under," "over," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "at 8230, below" and "at 8230, below" may include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, detailed structures and steps will be provided in the following description so as to explain the technical solution provided by the present invention. The preferred embodiments of the present invention are described in detail below, however, other embodiments of the present invention are possible in addition to these detailed descriptions.
The embodiment provides a cell protection circuit 10, which is applied to a cell management system, as shown in fig. 2, where the cell management system includes a cell Bat and a Charger. And the battery cell protection circuit 10 is connected with the battery cell Bat and the Charger, and is used for protecting the battery cell Bat when the battery cell Bat is subjected to a charging/charge-abuse test.
The embodiment provides a battery cell protection circuit 10, which is connected to a battery cell Bat, and as shown in fig. 1, includes a battery cell protection chip U1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a battery cell interface 11, and a charge/discharge interface 12; the battery cell protection chip U1 comprises a charging control end CO and a discharging control end DO; the first transistor Q1 is connected with the discharge control end DO and the cell interface 11; the second transistor Q2 is connected with the charging control end CO, the first transistor Q1 and the third transistor Q3; the third transistor Q3 is connected with the charging control terminal CO and the charging and discharging interface 12; when the battery cell Bat is normally charged, the first transistor Q1 is turned on, and the second transistor Q2 or the third transistor Q3 is turned on; when the battery cell Bat is overcharged, the second transistor Q2 and the third transistor Q3, which are not short-circuited when the battery cell Bat is normally charged, are turned off.
As an example, the cell protection circuit 10 includes a cell interface 11 and a charge and discharge interface 12. In this example, the cell interface 11 is used to connect the cell Bat, and the charge-discharge interface 12 is used to connect the Charger. Illustratively, the cell interface 11 includes a cell positive electrode B + and a cell negative electrode B-, the cell positive electrode B + is used for connecting a positive electrode of the cell Bat, and the cell negative electrode B-is used for connecting a negative electrode of the cell Bat. The charging and discharging interface 12 comprises a charging and discharging port anode P + and a charging and discharging port cathode P-, the charging and discharging port anode P + is used for connecting the anode of the Charger, and the charging and discharging port cathode P-is used for connecting the cathode of the Charger.
Optionally, the battery cell positive electrode B + and the charge-discharge port positive electrode P + are connected through a fuse F1, and the fuse F1 is disconnected when a large current occurs in the battery cell protection circuit 10, so as to protect the battery cell Bat.
As another example, the cell protection circuit 10 further includes a cell protection chip U1, a first transistor Q1, a second transistor Q2, and a third transistor Q3. The battery cell protection chip U1 includes a charging control terminal CO and a discharging control terminal DO. The first end of the first transistor Q1 is connected with the discharging control end DO, the second end of the first transistor Q1 is connected with the battery cell cathode B-, and the third end of the first transistor Q1 is connected with the second transistor Q2. The first terminal of the second transistor Q2 is connected to the charge control terminal CO, the second terminal of the second transistor Q2 is connected to the third terminal of the first transistor Q1, and the third terminal of the second transistor Q2 is connected to the third transistor Q3. The first end of the third transistor Q3 is connected with the charging control end CO, the second end of the third transistor Q3 is connected with the third end of the second transistor Q2, and the third end of the third transistor Q3 is connected with the negative pole P-of the charging and discharging port. In this example, when performing an abuse charging test on the battery cell Bat, the charging/discharging interface 12 is connected to the Charger, the discharging control terminal DO of the battery cell protection chip U1 outputs a high level signal to control the first transistor Q1 to be turned on, the charging control terminal CO outputs a high level signal to control the second transistor Q2 and the third transistor Q3 to be turned on, and at the same time, the second transistor Q2 or the third transistor Q3 is short-circuited, for example, the source and the drain of the second transistor Q2 or the third transistor Q3 are short-circuited, or one of the second transistor Q2 or the third transistor Q3 is damaged, which is equivalent to a short circuit, and the Charger starts to charge the battery cell Bat. When the voltage of the battery cell Bat rises to a certain voltage level and the overcharge delay is maintained, that is, after the battery cell Bat is overcharged, the charge control terminal CO of the battery cell protection chip U1 outputs a low level signal, and before the battery cell Bat is overcharged, the second transistor Q2 and the third transistor Q3 which are not short-circuited/disabled are disconnected, so that the main loop of the battery cell protection circuit 10 is cut off, and the Charger stops charging the battery cell Bat, thereby passing the overcharge test.
In this embodiment, the cell protection circuit 10 includes a cell protection chip U1, a first transistor Q1, a second transistor Q2, a third transistor Q3, a cell interface 11 and a charge/discharge interface 12, by connecting the first transistor Q1 with the discharge control terminal DO and the cell interface 11, connecting the second transistor Q2 with the charge control terminal CO, the first transistor Q1 and the third transistor Q3, and connecting the third transistor Q3 with the charge control terminal CO and the charge/discharge interface 12, when the cell Bat is normally charged, the first transistor Q1 is turned on, the second transistor Q2 and the third transistor Q3 are turned on, and at the same time, the second transistor Q2 or the third transistor Q3 is shorted, the cell Bat is normally charged, when the cell Bat is overcharged, the second transistor Q2 and the third transistor Q3 which are not shorted when the cell Bat is normally charged, the cell Bat stops charging, that is, the cell Bat is overcharged by the charge control terminal CO of the cell protection chip U1, and the third transistor Q3 are turned off, and the cell Bat is protected by the abuse protection circuit (the cell protection circuit) and the cell protection circuit can reduce the cost of the third transistor Q3, and the cell Bat protection circuit can be implemented by the abuse of the cell protection chip 10, and the third transistor Q3, and the cell protection circuit can be implemented by the electronic chip.
In an embodiment, as shown in fig. 1, the cell protection circuit 10 further includes a current sampling circuit 13; the current sampling circuit 13 is connected to the cell interface 11, the first transistor Q1, and the cell protection chip U1, respectively, and the current sampling circuit 13 is configured to collect a real-time current corresponding to the cell Bat and send the real-time current to the cell protection chip U1.
As an example, the cell protection circuit 10 further includes a current sampling circuit 13, and the current sampling circuit 13 is respectively connected to the cell interface 11, the first transistor Q1, and the cell protection chip U1. In this example, the current sampling circuit 13 is connected to the cell interface 11, the first transistor Q1 and the cell protection chip U1, so that the current sampling circuit 13 can collect real-time current corresponding to the cell Bat in real time, thereby implementing overcurrent protection of the cell Bat. In this embodiment, the first transistor Q1 is connected to the discharge control terminal DO and the cell interface 11, the second transistor Q2 is connected to the charge control terminal CO, the first transistor Q1 and the third transistor Q3, and the third transistor Q3 is connected to the charge control terminal CO and the charge/discharge interface 12, so that it is ensured that the first transistor Q1 is turned on and the second transistor Q2 or the third transistor Q3 is turned on when the cell Bat is normally charged, and when the cell Bat is overcharged, the second transistor Q2 and the third transistor Q3 are turned off when the cell Bat is normally charged, so that overcharge protection of the cell Bat can be realized.
In this embodiment, the cell protection circuit 10 further includes a current sampling circuit 13, and the current sampling circuit 13 is respectively connected to the cell interface 11, the first transistor Q1 and the cell protection chip U1, so that the current sampling circuit 13 can collect the real-time current corresponding to the cell Bat and send the real-time current to the cell protection chip U1, so that the cell protection chip U1 realizes the over-current protection of the cell Bat according to the real-time current corresponding to the cell Bat.
In one embodiment, as shown in fig. 1, the current sampling circuit 13 includes a sampling resistor RS; the first end of the sampling resistor RS is connected with the battery cell cathode B-and the VSS end of the battery cell protection chip U1, and the second end of the sampling resistor RS is connected with the VM end of the first transistor Q1 and the VM end of the battery cell protection chip U1.
As an example, the current sampling circuit 13 includes a sampling resistor RS, a first end of the sampling resistor RS is connected to the cell negative electrode B-and the VSS end of the cell protection chip U1, and a second end of the sampling resistor RS is connected to the first transistor Q1 and the VM end of the cell protection chip U1. In this example, the first end of the sampling resistor RS is connected to the cell negative electrode B — and the VSS end of the cell protection chip U1, and the second end of the sampling resistor RS is connected to the VM end of the first transistor Q1 and the cell protection chip U1, so that when the cell Bat is normally charged or overcharged, that is, when the cell Bat is charged, the real-time current of the cell protection circuit 10 is obtained from the sampling resistor RS, and the cell protection chip U1 can determine whether the current in the loop is too large according to the real-time current, thereby implementing overcurrent protection of the cell Bat.
In this embodiment, the current sampling circuit 13 includes a sampling resistor RS, and the first end of the sampling resistor RS is connected to the battery cell negative electrode B-and the VSS end of the battery cell protection chip U1, and the second end of the sampling resistor RS is connected to the first transistor Q1 and the VM end of the battery cell protection chip U1, so that the battery cell protection chip U1 can obtain the real-time current of the battery cell protection circuit 10 from the sampling resistor RS, thereby implementing the overcurrent protection of the battery cell Bat.
In an embodiment, as shown in fig. 1, the cell protection circuit 10 further includes a first current limiting resistor R1; the first end of the first current-limiting resistor R1 is connected with the battery cell positive electrode B + and the charge-discharge port positive electrode P +, and the second end of the first current-limiting resistor R1 is connected with the VDD end of the battery cell protection chip U1; the cell protection circuit 10 further includes a second current-limiting resistor R2; the first end of the second current-limiting resistor R2 is connected with the negative pole P-of the charge-discharge port and the third transistor Q3, and the second end of the second current-limiting resistor R2 is connected with the VM end of the battery cell protection chip U1.
As an example, the cell protection circuit 10 further includes a first current-limiting resistor R1, a first end of the first current-limiting resistor R1 is connected to the cell positive electrode B + and the charge/discharge port positive electrode P +, and a second end of the first current-limiting resistor R1 is connected to the VDD end of the cell protection chip U1, so as to prevent an excessive current from flowing into the VDD end of the cell protection chip U1, and improve the safety of the cell protection chip U1.
As another example, the cell protection circuit 10 further includes a second current-limiting resistor R2, a first end of the second current-limiting resistor R2 is connected to the negative electrode P-of the charge/discharge port and the third transistor Q3, and a second end of the second current-limiting resistor R2 is connected to the VM end of the cell protection chip U1, so as to prevent an excessive current from flowing into the VM end of the cell protection chip U1, and improve the safety of the cell protection chip U1.
In this embodiment, the first end of the first current-limiting resistor R1 is connected to the cell positive electrode B + and the charge/discharge port positive electrode P +, the second end of the first current-limiting resistor R1 is connected to the VDD terminal of the cell protection chip U1, the first end of the second current-limiting resistor R2 is connected to the charge/discharge port negative electrode P-and the third transistor Q3, and the second end of the second current-limiting resistor R2 is connected to the VM terminal of the cell protection chip U1, so that a large current in the cell protection circuit 10 can be prevented from flowing into the cell protection chip U1, and the safety of the cell protection chip U1 is improved.
In an embodiment, as shown in fig. 1, the cell protection circuit 10 further includes a first filter capacitor; a first end of the first filter capacitor is connected with a VDD end of the battery cell protection chip U1, and a second end of the first filter capacitor is connected with a VM end of the battery cell protection chip U1; the cell protection circuit 10 further includes a second filter capacitor; the first end of the second filter capacitor is connected with the second end of the sampling resistor RS, and the second end of the second filter capacitor is connected with the first end of the second current limiting resistor R2.
As an example, the first end of the first filter capacitor is connected to the VDD terminal of the cell protection chip U1, and the second end of the first filter capacitor is connected to the VM terminal of the cell protection chip U1, so as to filter the electrical signals input to the VDD terminal of the cell protection chip U1 and the VM terminal of the cell protection chip U1. Illustratively, the first filter capacitor may comprise a capacitor C1 as in fig. 1.
As another example, the cell protection circuit 10 further includes a second filter capacitor, a first end of the second filter capacitor is connected to the second end of the sampling resistor RS, and a second end of the second filter capacitor is connected to the first end of the second current limiting resistor R2, and is configured to filter the clutter signal of the cell protection circuit 10. Illustratively, the second filter capacitor may be a single capacitor, or a plurality of capacitors connected in series. For example, the second filter capacitor may be a capacitor C2 and a capacitor C3 connected in series as in fig. 1.
In this embodiment, the electric signals input to the VDD terminal of the electric core protection chip U1 and the VM terminal of the electric core protection chip U1 are filtered by the first filter capacitor, and the electric core protection chip U1 is prevented from being interfered by other signals by the second filter capacitor, so that the reliability of the electric core protection chip U1 in the working process is improved.
In an embodiment, as shown in fig. 1, the cell protection circuit 10 further includes an electrostatic protection circuit 14; the first end of the electrostatic protection circuit 14 is connected with a connection node between the positive electrode P + of the charge and discharge port and the positive electrode B + of the battery cell, and the second end of the electrostatic protection circuit 14 is connected with a connection node between the second transistor Q2 and the negative electrode P-of the charge and discharge port.
In this embodiment, the cell protection circuit 10 further includes an electrostatic protection circuit 14, and the first end of the electrostatic protection circuit 14 is connected to the connection node between the positive electrode P + of the charge/discharge port and the positive electrode B + of the cell, and the second end of the electrostatic protection circuit 14 is connected to the connection node between the second transistor Q2 and the negative electrode P-of the charge/discharge port, so that the charging/discharging interface 12 can prevent static electricity from being input at the moment when the Charger charge is connected, and the safety of the cell protection circuit 10 is improved.
In an embodiment, as shown in fig. 1, the electrostatic protection circuit 14 includes an electrostatic protection capacitor, and is configured to prevent static electricity from being input to the charge/discharge interface 12 at the moment when the Charger charge is connected, so as to improve the safety of the cell protection circuit 10. For example, the electrostatic protection capacitor may include a capacitor C4 and a capacitor C5 connected in series as in fig. 1.
In an embodiment, the first transistor, the second transistor and the third transistor are MOS transistors.
In this embodiment, the first transistor, the second transistor, and the third transistor are MOS transistors, so that it is ensured that, when the battery cell Bat is normally charged, the first transistor Q1 is turned on, and the second transistor Q2 or the third transistor Q3 is turned on, and when the battery cell Bat is overcharged, the second transistor Q2 and the third transistor Q3 that are turned on when the battery cell Bat is normally charged are turned off, so that overcharge protection of the battery cell Bat can be implemented.
In an embodiment, the first transistor, the second transistor and the third transistor are N-type MOS transistors.
As an example, the first transistor, the second transistor, and the third transistor are N-type MOS transistors.
As an example, first terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are gates, second terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are sources, and third terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3 are drains.
In this embodiment, the first transistor Q1, the second transistor Q2, or the third transistor Q3 can be turned on when the battery cell Bat is normally charged by using N-type MOS transistors as the first transistor, the second transistor, or the third transistor, and when the battery cell Bat is overcharged, the second transistor Q2, or the third transistor Q3, which is turned on when the battery cell Bat is normally charged, is turned off, so as to implement overcharge protection of the battery cell Bat.
The present embodiment provides a cell management system, as shown in fig. 2, including a cell Bat, a Charger, and the above-mentioned cell protection circuit 10.
The above-mentioned embodiments are only used for illustrating the technical solution of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A battery cell protection circuit is connected with a battery cell and is characterized by comprising a battery cell protection chip, a first transistor, a second transistor, a third transistor, a battery cell interface and a charge-discharge interface; the battery cell protection chip comprises a charging control end and a discharging control end;
the first transistor is connected with the discharge control end and the battery cell interface;
the second transistor is connected with the charging control end, the first transistor and the third transistor;
the third transistor is connected with the charging control end and the charging and discharging interface;
when the battery cell is normally charged, the first transistor is turned on, and the second transistor or the third transistor is turned on; when the battery cell is overcharged, the second transistor and the third transistor which are not short-circuited when the battery cell is normally charged are disconnected.
2. The cell protection circuit of claim 1, further comprising a current sampling circuit; the current sampling circuit is respectively connected with the battery cell interface, the first transistor and the battery cell protection chip, and is used for collecting real-time current in the battery cell protection circuit and sending the real-time current to the battery cell protection chip.
3. The cell protection circuit of claim 2, wherein the current sampling circuit comprises a sampling resistor; the first end of the sampling resistor is connected with the negative electrode of the battery cell and the VSS end of the battery cell protection chip, and the second end of the sampling resistor is connected with the first transistor and the VM end of the battery cell protection chip.
4. The cell protection circuit of claim 2, further comprising a first current limiting resistor; the first end of the first current-limiting resistor is connected with the positive electrode of the battery cell and the positive electrode of the charging and discharging port, and the second end of the first current-limiting resistor is connected with the VDD end of the battery cell protection chip;
the battery cell protection circuit further comprises a second current-limiting resistor; the first end of the second current-limiting resistor is connected with the negative electrode of the charging and discharging port and the third transistor, and the second end of the second current-limiting resistor is connected with the VM end of the battery cell protection chip.
5. The cell protection circuit of claim 4, wherein the cell protection circuit further comprises a first filter capacitance; a first end of the first filter capacitor is connected with a VDD end of the battery cell protection chip, and a second end of the first filter capacitor is connected with a VM end of the battery cell protection chip;
the battery cell protection circuit further comprises a second filter capacitor; and the first end of the second filter capacitor is connected with the second end of the sampling resistor, and the second end of the second filter capacitor is connected with the first end of the second current-limiting resistor.
6. The cell protection circuit of claim 1, wherein the cell protection circuit further comprises an electrostatic protection circuit; the first end of the electrostatic protection circuit is connected with a connecting node of the positive pole of the charge-discharge port and the positive pole of the battery cell, and the second end of the electrostatic protection circuit is connected with a connecting node of the second transistor and the negative pole of the charge-discharge port.
7. The cell protection circuit of claim 6, wherein the electrostatic protection circuit comprises an electrostatic protection capacitor.
8. The cell protection circuit of any one of claims 1 to 7, wherein the first transistor, the second transistor, and the third transistor are MOS transistors.
9. The cell protection circuit of claim 8, wherein the first transistor, the second transistor, and the third transistor are N-type MOS transistors.
10. A cell management system, comprising a cell, a charger, and the cell protection circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220233044.9U CN217789320U (en) | 2022-01-27 | 2022-01-27 | Battery cell protection circuit and battery cell management system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220233044.9U CN217789320U (en) | 2022-01-27 | 2022-01-27 | Battery cell protection circuit and battery cell management system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217789320U true CN217789320U (en) | 2022-11-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220233044.9U Active CN217789320U (en) | 2022-01-27 | 2022-01-27 | Battery cell protection circuit and battery cell management system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217789320U (en) |
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2022
- 2022-01-27 CN CN202220233044.9U patent/CN217789320U/en active Active
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