CN217739298U - Residual voltage detection loop - Google Patents
Residual voltage detection loop Download PDFInfo
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- CN217739298U CN217739298U CN202220579827.2U CN202220579827U CN217739298U CN 217739298 U CN217739298 U CN 217739298U CN 202220579827 U CN202220579827 U CN 202220579827U CN 217739298 U CN217739298 U CN 217739298U
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Abstract
The utility model provides a residual voltage detection return circuit, mainly is applicable to the residual voltage detection of terminal feeder, contains, the transformer: the voltage transformation circuit is used for transforming the voltage of the terminal feeder line and receiving a residual voltage signal; diode rectification circuit: the rectifier is used for rectifying the current processed by the transformer; a transistor control loop: a switch for controlling the latching relay circuit; retention relay circuit: the output end of the latching relay loop is connected with a processor; an optical coupling loop: the relay control circuit is used for controlling the relay control circuit to charge; mutual inductor: the second signal is used for collecting a terminal feeder line; an analog-to-digital conversion chip: the analog-to-digital conversion device is used for performing analog-to-digital conversion on the signal; a drive circuit: the optical coupling loop is used for driving the optical coupling loop to be switched on and off; a processor: for controlling the drive circuit; has the advantages that: under the condition that the feeder terminal is power-off and under the condition that the feeder terminal normally operates, the residual voltage detection loop can normally work, the reliability of residual voltage detection is improved, and a hardware circuit is simplified.
Description
Technical Field
The utility model relates to a power grid detection area especially relates to the residual voltage of terminal feeder detects.
Background
Residual voltage is the peak voltage of a designated end of the protector when discharge current flows, and can also be called the voltage appearing between terminals of the lightning protection device when the lightning discharge current passes through the lightning protection device, and when an accident occurs, the generated residual voltage has a remarkable influence on electric power equipment and a power grid.
In order to improve the reliability of power supply and reduce the power failure times of the line, the distribution line is provided with a reclosing function, but when the distribution line is reclosed in a permanent fault, the protection device trips again, and a short-time fault voltage cycle, namely residual voltage, appears on the fault line. The feeder line terminal adopts local power taking, and after the upper power supply loop trips, the feeder line terminal loses power. After once more getting electricity, feeder terminal need detect the residual voltage, avoids closing a floodgate in trouble circuit, and current residual voltage detection technique main problems divide two kinds: firstly, part design circuit is simple relatively, and the reliability is lower, and secondly, part design circuit is more complicated, and the reliability is higher, but the cost is very high.
SUMMERY OF THE UTILITY MODEL
Aiming at the problems of low reliability of a simple circuit and high cost of a complex circuit in the prior art, the technical scheme provides a residual voltage detection loop which is mainly suitable for residual voltage detection of a feeder line terminal and comprises,
a transformer: the primary side of the transformer is coupled with the feeder terminal, and the secondary side of the transformer is connected with a diode rectifying loop;
the input end of the diode rectifying loop is connected with the secondary side of the transformer, and the output end of the diode rectifying loop is connected with the input end of a transistor control loop;
the output end of the transistor control loop is respectively connected with the input end of a retentivity relay loop and the output end of an optical coupling loop;
the output end of the latching relay loop is connected with a processor;
the input end of the optocoupler loop is connected with the output end of a driving circuit;
mutual inductor: the primary side of the mutual inductor is connected with the feeder terminal, and the secondary side of the mutual inductor is connected with the input end of an analog-to-digital conversion chip;
an analog-to-digital conversion chip: the output end of the analog-to-digital conversion chip is connected with the input end of the processor;
a drive circuit: the input end of the driving circuit is connected with the output end of the processor;
a processor: the processor is connected with the driving circuit.
Preferably, the diode rectifying circuit includes a first diode, a second diode, a third diode, and a fourth diode;
a first node and a second node are respectively arranged at two ends of the secondary side of the transformer,
the first node is arranged between a first diode and a third diode,
the second node is arranged between a second diode and a fourth diode;
the cathode of the first diode is connected with the anode of the third diode, the cathode of the second diode is connected with the anode of the fourth diode, the anode of the first diode is connected with the anode of the second diode through a third node, and the cathode of the third diode is connected with the cathode of the fourth diode through a fourth node;
and taking the third node as the input end of the diode rectifying loop, and taking the fourth node as the output end of the diode rectifying loop.
Preferably, the transistor control loop includes a first transistor and a second transistor;
the source electrode of the first transistor is connected with the grid electrode of the second transistor, the grid electrode of the first transistor is connected with the fourth node through a second resistor and is connected with the third node through a third resistor, the third resistor is connected with a second capacitor in parallel, the second capacitor is connected with a first current limiting diode in parallel, the negative electrode of the current limiting diode is connected with the grid electrode of the first transistor, and the positive electrode of the first current limiting diode is connected with the drain electrode of the first transistor;
the source electrode of the second transistor is connected with the first resistor through a closing coil L1, the grid electrode of the second transistor is connected with the fourth node through an eighth resistor and is connected with the negative electrode of a second current limiting diode, the negative electrode of the second current limiting diode is connected with the drain electrode of the second transistor, and the second current limiting diode is connected with a third capacitor in parallel.
Preferably, the transistor control circuit further includes a first capacitor, a third current limiting diode, and a fourth resistor;
the first capacitor is connected with the closing coil L1 in parallel;
the negative electrode of the third current limiting diode is connected with the first resistor, the negative electrode of the third current limiting tube is connected with the source electrode of the second transistor, and the third current limiting diode is connected with the closing coil L1 in parallel;
the fourth resistor is connected with the third node through a reset coil, and the reset coil is coupled.
Preferably, the optocoupler loop includes an optocoupler, a collector of a primary side of the optocoupler is connected to the fourth resistor through the reset coil, and an emitter of the optocoupler is connected to a drain of the second transistor;
and the light emitting diode on the secondary side of the optical coupler is coupled with the base of the optical coupler.
Preferably, in the transformer, the primary side of the transformer is connected to one of the feeder terminals, the secondary side of the transformer is connected to the diode rectifying circuit, and nodes of the transformer are respectively between the first diode and the first diode, and between the first diode and the first diode.
Preferably, the latching relay includes the closing coil L1 and the reset coil, the reset coil is connected in parallel with a fourth current limiting diode, a negative electrode of the fourth current limiting diode is connected to the fourth node through the fourth resistor, and a positive electrode of the fourth current limiting diode is connected to an emitter of the optocoupler;
the latching relay further comprises a fourth capacitor and a switch, the fourth capacitor is connected with the fourth current limiting diode in parallel, one side of the switch is connected with a power supply through a fifth resistor, and the other side of the switch is grounded.
Preferably, the driving circuit includes a sixth resistor, and the sixth resistor is disposed between the cathode of the light emitting diode and the collector of a driving transistor;
the base electrode of the driving triode is connected with the processor through a seventh resistor, and the emitting electrode of the driving triode is grounded.
Preferably, the system further comprises a storage battery connected with the processor.
Has the beneficial effects that: under the condition that the feeder terminal is power-off and under the condition that the feeder terminal normally operates, the residual voltage detection loop can normally work, the reliability of residual voltage detection is improved, and a hardware circuit is simplified.
Drawings
Fig. 1 is a schematic diagram of the structure of the detection circuit according to the preferred embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that, in the present invention, the embodiments and features of the embodiments may be combined with each other without conflict.
The present invention will be further described with reference to the accompanying drawings and specific embodiments, but the present invention is not limited thereto.
This technical scheme provides a residual voltage detection return circuit, mainly is applicable to feeder terminal's residual voltage and detects, as shown in figure one, contains:
a transformer T1: the primary side of the transformer T1 is coupled with a feeder terminal, and the secondary side of the transformer T1 is connected with a diode rectifying loop 1;
the input end of the diode rectifying loop 1 is connected with the secondary side of the transformer T1, and the output end of the diode rectifying loop 1 is connected with the input end of a transistor control loop 2;
the output end of the transistor control loop 2 is respectively connected with the input end of a retentivity relay loop 3 and the output end of an optical coupling loop 4;
the output end of the retentivity relay loop 3 is connected with a processor CPU;
the input end of the optical coupling loop 4 is connected with the output end of a driving circuit 5;
a mutual inductor T2: the primary side of the mutual inductor T2 is connected with a feeder terminal, and the secondary side of the mutual inductor T2 is connected with the input end of an analog-to-digital conversion chip AD;
analog-to-digital conversion chip AD: the output end of the analog-to-digital conversion chip AD is connected with the input end of the CPU;
the drive circuit 5: the input end of the drive circuit 5 is connected with the output end of the CPU;
a processor CPU: the processor CPU is connected to the driving circuit 5.
Specifically, in this embodiment, the transformer T1 is configured to change the high voltage at the feeder terminal into a reasonable voltage for collection and detection, the diode rectifier circuit 1 is configured to rectify and filter the current transmitted from the feeder terminal, the transistor control circuit 2 is configured to control the retention relay RLY1 so that it can be closed and retained under operation, the retention relay RLY1 can detect a residual voltage signal by detecting a node state of the relay, the analog-to-digital conversion chip AD is configured to directly convert the ac power at the feeder terminal into a dc power for measurement by the processor CPU, when the feeder terminal is powered off, the residual voltage value is equal to 50 ÷ un, the duration is 60ms, the residual voltage detection circuit normally operates, the relay closing coil L1 acts, the relay node is closed, and under the residual voltage value of 50 ÷ un, the transformer T1 outputs ac 10V.
In the preferred embodiment of the present invention, the diode rectifying circuit 1 includes a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4;
a first node and a second node are respectively arranged at two ends of the secondary side of the transformer T1,
the first node is arranged between a first diode and a third diode,
the second node is arranged between a second diode and a fourth diode;
the cathode of the first diode is connected with the anode of the third diode, the cathode of the second diode is connected with the anode of the fourth diode, the anode of the first diode is connected with the anode of the second diode through a third node, and the cathode of the third diode is connected with the cathode of the fourth diode through a fourth node;
the third node is used as the input end of the diode rectifying circuit 1, and the fourth node is used as the output end of the diode rectifying circuit 1.
Specifically, in this embodiment, the rectifier circuit is a full-bridge rectifier circuit, the full-bridge rectifiers D1 to D4 employ diodes, the voltage drop of the single tube in the forward direction is 0.7V, the rectifier bridge outputs a sinusoidal half wave, the effective value is about 8.6V, and for the alternating current in the power grid, the alternating current needs to be rectified by the diode rectifier circuit 1 to be a direct current in the detection circuit, so that various elements can be utilized to output different level signals for the CPU to determine.
In the preferred embodiment of the present invention, the transistor control circuit 2 comprises a first transistor Q1 and a second transistor Q2;
the source electrode of the first transistor Q1 is connected with the grid electrode of the second transistor Q2, the grid electrode of the first transistor Q1 is connected with the fourth node through a second resistor R2 and is connected with the third node through a third resistor R3, the third resistor R3 is connected with a second capacitor C2 in parallel, the second capacitor C2 is connected with a first current limiting diode V1 in parallel, the negative electrode of the current limiting diode is connected with the grid electrode of the first transistor Q1, and the positive electrode of the first current limiting diode V1 is connected with the drain electrode of the first transistor Q1;
the source electrode of the second transistor Q2 is connected with the first resistor R1 through a closing coil L1, the grid electrode of the second transistor Q2 is connected with the fourth node through an eighth resistor R8 and is connected with the negative electrode of a second current limiting diode V2, the negative electrode of the second current limiting diode V2 is connected with the drain electrode of the second transistor Q2, and the second current limiting diode V2 is connected with a third capacitor C3 in parallel.
Specifically, in this embodiment, in order to reduce the power of the voltage limiting diode and the resistor and reduce the heat generation of the relay, a circuit composed of the second resistor R2, the third capacitor C3, the second capacitor C2, and the first voltage limiting diode is used to control the first transistor Q1, the capacitor is charged by the sine half-wave voltage through the resistor, the charging time is about 300ms, and the gate voltage does not exceed 5.1V by the clamping action. After the first transistor Q1 is conducted, the grid voltage of the second transistor Q2 is pulled down to 0, the second transistor Q2 is turned off, the current of the resistor and the relay closing coil L1 is changed into 0, the operating time of the resistor, the voltage limiting diode, the relay and the like is 300ms, and the power of the device is reduced.
In a preferred embodiment of the present invention, the transistor control circuit 2 further includes a first capacitor C1, a third current limiting diode V3, and a fourth resistor R4;
the first capacitor C1 is connected with the closing coil L1 in parallel;
the negative electrode of a third current limiting diode V3 is connected with the first resistor R1, the negative electrode of the third current limiting tube is connected with the source electrode of the second transistor Q2, and the third current limiting diode V3 is connected with the closing coil L1 in parallel;
the fourth resistor R4 is connected to the third node through a reset coil L2, and the reset coil L2 is coupled.
Specifically, in this embodiment, the clamping action of the third current limiting diode V3 makes the voltage of the closing coil L1 not exceed the rated voltage all the time.
In a preferred embodiment of the present invention, the optical coupler loop 4 includes an optical coupler OP1, a collector of a primary side of the optical coupler OP1 is connected to the fourth resistor through a reset coil L2, and an emitter of the optical coupler OP1 is connected to a drain of the second transistor Q2;
and the light emitting diode on the secondary side of the optical coupler OP1 is coupled with the base electrode on the primary side of the optical coupler OP 1.
Specifically, in this embodiment, the processor CPU drives the primary side of the optocoupler OP1 to emit light, the secondary side of the optocoupler OP1 is turned on, the capacitor is charged by the sinusoidal half-wave voltage through the resistor, the charging time is about 12ms, and after the relay reset voltage is reached, the relay node is turned on.
The utility model discloses in the preferred embodiment, a feeder terminal is connected to transformer T1 primary side, and diode rectifier circuit 1 is connected to the secondary side, and its node is respectively between first diode and first diode, between first diode and the first diode.
Specifically, in this embodiment, a timer is built in the processor CPU, after the primary side of the optical coupler OP1 is driven to emit light, the secondary side of the optical coupler OP1 is turned on, and when the relay does not reach the reset voltage, whether the relay is damaged is determined by a threshold preset by the timer, and after the relay is determined to be damaged, the residual voltage signal at the current feeder terminal is directly measured by the transformer T2.
In a preferred embodiment of the present invention, the latching relay RLY1 includes a closing coil L1 and a reset coil L2, the reset coil L2 is connected in parallel with a fourth current limiting diode V4, the negative electrode of the fourth current limiting diode V4 is connected to a fourth node through a fourth resistor R4, and the positive electrode of the fourth current limiting diode V4 is connected to the emitter of the opto-coupler OP 1;
the latching relay RLY1 also includes a fourth capacitor C4 and a switch, the fourth capacitor C4 is connected in parallel with a fourth current limiting diode V4, one side of the switch is connected with a power supply through a fifth resistor R5, and the other side of the switch is grounded.
Specifically, in this embodiment, the voltage of the reset coil L2 may not exceed the rated voltage all the time through the fourth voltage limiting diode, so as to ensure that the coil is not overheated, and the fourth capacitor C4 has a larger capacitance value.
In the preferred embodiment of the present invention, the driving circuit 5 includes a sixth resistor R6, the sixth resistor R6 is disposed between the cathode of the light emitting diode and the collector of a driving transistor Q3;
the base electrode of the driving triode Q3 is connected with the CPU through a seventh resistor R7, and the emitting electrode of the driving triode Q3 is grounded.
Specifically, in this embodiment, after the line voltage recovers to be normal, the CPU clears away the residual voltage signal, and sends the residual voltage reset signal, switches on through drive triode Q3, and then drives the primary side of opto-coupler OP1 and give out light, and the secondary side of opto-coupler OP1 switches on, and the electric capacity is charged through resistance to sinusoidal half-wave voltage, and the charging time is about 12ms, and after reaching relay RLY1 reset voltage, the relay node is opened, because V4 clamping effect, relay closing coil L1 voltage is no longer than 5.1V all the time.
The present invention further comprises a battery connected to the processor CPU in a preferred embodiment.
Specifically, in this embodiment, the storage battery ensures that the analog-to-digital conversion can work by supplying power to the processor CPU under the condition that the line loses power, the residual voltage signal is measured by the analog-to-digital conversion chip AD after passing through the transformer T2, and the processor CPU determines whether the residual voltage signal is the residual voltage signal by analyzing the measurement signal.
The above description is only an example of the preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and those skilled in the art should be able to realize the equivalent alternatives and obvious variations of the present invention.
Claims (8)
1. The utility model provides a residual voltage detection return circuit, mainly is applicable to the residual voltage detection of terminal feeder, its characterized in that contains:
a transformer: the primary side of the transformer is coupled with the feeder terminal, and the secondary side of the transformer is connected with a diode rectifying loop;
the input end of the diode rectifying loop is connected with the secondary side of the transformer, and the output end of the diode rectifying loop is connected with the input end of a transistor control loop;
the output end of the transistor control loop is respectively connected with the input end of a retentivity relay loop and the output end of an optocoupler loop;
the output end of the retentivity relay loop is connected with a processor;
the input end of the optical coupling loop is connected with the output end of a driving circuit;
mutual inductor: the primary side of the mutual inductor is connected with the feeder terminal, and the secondary side of the mutual inductor is connected with the input end of an analog-to-digital conversion chip;
an analog-to-digital conversion chip: the output end of the analog-to-digital conversion chip is connected with the input end of the processor;
a drive circuit: the input end of the driving circuit is connected with the output end of the processor;
a processor: for controlling the drive circuit.
2. The residual voltage detection circuit as claimed in claim 1, wherein the diode rectifying circuit comprises a first diode, a second diode, a third diode, a fourth diode;
a first node and a second node are respectively arranged at two ends of the secondary side of the transformer,
the first node is arranged between a first diode and a third diode,
the second node is arranged between a second diode and a fourth diode;
the cathode of the first diode is connected with the anode of the third diode, the cathode of the second diode is connected with the anode of the fourth diode, the anode of the first diode is connected with the anode of the second diode through a third node, and the cathode of the third diode is connected with the cathode of the fourth diode through a fourth node;
and taking the third node as the input end of the diode rectifying loop, and taking the fourth node as the output end of the diode rectifying loop.
3. The residual voltage detection circuit as claimed in claim 2, wherein said transistor control circuit includes a first transistor, a second transistor;
the source electrode of the first transistor is connected with the grid electrode of the second transistor, the grid electrode of the first transistor is connected with the fourth node through a second resistor and is connected with the third node through a third resistor, the third resistor is connected with a second capacitor in parallel, the second capacitor is connected with a first current limiting diode in parallel, the negative electrode of the current limiting diode is connected with the grid electrode of the first transistor, and the positive electrode of the first current limiting diode is connected with the drain electrode of the first transistor;
the source electrode of the second transistor is connected with the first resistor through a closing coil, the grid electrode of the second transistor is connected with the fourth node through an eighth resistor and is connected with the negative electrode of a second current limiting diode, the negative electrode of the second current limiting diode is connected with the drain electrode of the second transistor, and the second current limiting diode is connected with a third resistor in parallel.
4. The residual voltage detection circuit as claimed in claim 3, wherein said transistor control circuit further comprises a first capacitor, a third current limiting diode, a fourth resistor;
the first capacitor is connected with the closing coil in parallel;
the negative electrode of the third current limiting diode is connected with the first resistor, the negative electrode of the third current limiting tube is connected with the source electrode of the second transistor, and the third current limiting diode is connected with the closing coil in parallel;
the fourth resistor is connected with the third node through a reset coil, and the reset coil is coupled.
5. The residual voltage detection circuit according to claim 4, wherein said optical coupler circuit comprises an optical coupler, a collector of a primary side of said optical coupler is connected to said fourth resistor through said reset coil, and an emitter of said optical coupler is connected to a drain of said second transistor;
and the light emitting diode on the secondary side of the optical coupler is coupled with the base of the optical coupler.
6. The residual voltage detection circuit as claimed in claim 5, wherein said holding relay comprises said closing coil and said reset coil, said reset coil is connected in parallel with a fourth current limiting diode, a cathode of said fourth current limiting diode is connected to said fourth node through said fourth resistor, and an anode of said fourth current limiting diode is connected to an emitter of said optocoupler;
the latching relay further comprises a fourth capacitor and a switch, the fourth capacitor is connected with the fourth current limiting diode in parallel, one side of the switch is connected with a power supply through a fifth resistor, and the other side of the switch is grounded.
7. The invention as claimed in claim 6, wherein the driving circuit comprises a sixth resistor disposed between the cathode of the led and the collector of a driving transistor;
the base electrode of the driving triode is connected with the processor through a seventh resistor, and the emitting electrode of the driving triode is grounded.
8. The residual voltage detection circuit according to claim 1, further comprising a battery connected to said processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220579827.2U CN217739298U (en) | 2022-03-15 | 2022-03-15 | Residual voltage detection loop |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220579827.2U CN217739298U (en) | 2022-03-15 | 2022-03-15 | Residual voltage detection loop |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217739298U true CN217739298U (en) | 2022-11-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220579827.2U Active CN217739298U (en) | 2022-03-15 | 2022-03-15 | Residual voltage detection loop |
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| Country | Link |
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| CN (1) | CN217739298U (en) |
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- 2022-03-15 CN CN202220579827.2U patent/CN217739298U/en active Active
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