CN217693347U - Dual-mode anti-interference processing module of small aerial antenna - Google Patents
Dual-mode anti-interference processing module of small aerial antenna Download PDFInfo
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- CN217693347U CN217693347U CN202221001005.2U CN202221001005U CN217693347U CN 217693347 U CN217693347 U CN 217693347U CN 202221001005 U CN202221001005 U CN 202221001005U CN 217693347 U CN217693347 U CN 217693347U
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Abstract
The utility model discloses a dual-mode anti-interference processing module of a small aerial antenna, which comprises a radio frequency and digital signal processing part; the radio frequency signal processing part comprises 2 down-conversion channels PCB, 2 local oscillator PCB and 2 up-conversion output PCBs which are respectively corresponding to the 2 modes of B3 and L1/B1, wherein each down-conversion channel PCB comprises 4 down-conversion channels; the local oscillator PCB is connected with the down-conversion PCB and the up-conversion PCB; the digital signal processing part comprises a serial port drive PCB and a signal processing PCB, the signal processing PCB comprises AD conversion units, an FPGA and a DAC, and each AD conversion unit comprises 4 ADCs; the ADC is connected with the down-conversion channel, the ADC and the DAC are both connected with the FPGA, and the DAC is connected with the up-conversion output PCB; the serial port drive PCB comprises an ARM, and the ARM is connected with each FPGA and the local oscillation PCB. The utility model discloses can realize the 4 array element anti-interference processing of bimodulus simultaneously, the interference killing feature is strong.
Description
Technical Field
The utility model relates to a small-size aerial antenna's bimodulus anti-interference processing module.
Background
The existing anti-interference processing module adopts a radio frequency and signal processing separated design and is connected through a radio frequency cable, so that the size is overlarge, the cable is complicated, and the anti-interference trend of miniaturization modularization cannot be met.
SUMMERY OF THE UTILITY MODEL
Problem to prior art exists, the utility model provides a small-size aerial's bimodulus anti-interference processing module, the miniaturized airborne aviation that is suitable for of overall dimension can realize the bimodulus 4 array element anti-interference processing at GPS L1 and BDS B3B 1 frequency point simultaneously, and has better interference killing feature.
In order to achieve the technical purpose, the utility model adopts the following technical scheme:
a dual-mode anti-interference processing module of a small aerial antenna comprises: a radio frequency signal processing section and a digital signal processing section;
the radio frequency signal processing section includes: 2 down-conversion channels PCB, 2 local oscillator PCB and 2 up-conversion output PCB which are all corresponding to 2 modes of B3 and L1/B1, wherein the down-conversion channel PCB of each mode comprises 4 down-conversion channels; the local oscillation PCB of each mode is connected with the down-conversion channel and the up-conversion output PCB of the corresponding mode and is used for down-conversion and up-conversion processing;
the digital signal processing section includes: the system comprises a serial port drive PCB and 2 signal processing PCBs corresponding to 2 modes of B3 and L1/B1, wherein each signal processing PCB comprises an AD conversion unit, an FPGA and a DA converter, and each AD conversion unit comprises 4 AD converters; for each mode of B3 and L1/B1, the input ends of 4 AD converters are connected with the output ends of 4 down-conversion channels, the output end of each AD converter and the input end of a DA converter are connected with the FPGA, and the output end of the DA converter is connected with the up-conversion output PCB; and an ARM processor is arranged on the serial port drive PCB and is connected with each FPGA and the local oscillation PCB.
Furthermore, an MCX-JE connector is arranged on each signal processing PCB, and an MCX-KYD15-1 connector is arranged on each down-conversion channel PCB and each up-conversion output PCB; and between the signal processing PCB and the down-conversion channel PCB and the up-conversion output PCB in each mode, the radio frequency signal transmission between the signal processing PCB and the up-conversion output PCB and the down-conversion channel PCB is realized by the mutual insertion of the MCX-JE connector and the MCX-KYD15-1 connector.
Furthermore, the serial port drive PCB is in communication connection with the signal processing PCB through a low-frequency cable with the model number of J63A/3-MDC1-15 PL.
Further, the dual-mode anti-interference processing module further includes an external connector: 8 radio frequency signal input connectors correspondingly connected with the down-conversion channels, 2 radio frequency signal output connectors correspondingly connected with the up-conversion output PCBs and a low-frequency connector connected with the serial port drive PCBs.
Furthermore, the radio frequency signal input connector and the radio frequency signal output connector are both MCX-KYD15-1 in model.
Furthermore, the low-frequency connector is J30J-31ZKW-J.
Furthermore, the low-frequency connector J30J-31ZKW-J is provided with a serial port and a power supply port, the serial port is connected with an IO port of an ARM processor, and the power supply port is used for providing a working power supply for the dual-mode anti-interference processing module.
Further, the dual-mode anti-interference processing module further comprises 2 radio frequency channel cover plates, 2 local oscillator cover plates and 2 signal processing cover plates; the 2 radio frequency channel cover plates are used for protecting down-conversion channel PCBs and up-conversion output PCBs in various modes, the 2 local oscillator cover plates are used for protecting local oscillator PCBs in various modes, and the 2 signal processing cover plates are used for protecting signal processing PCBs in various modes.
Furthermore, the materials of various cover plates are all aluminum alloy materials.
Advantageous effects
1. The array antenna unit can be matched with GPSL1/BDS B1 and BDS B3 dual four-array elements, and has the capability of resisting interference of 3 directions of GPSL1/BDS B1 and BDS B3 dual-frequency points;
2. the anti-interference module adopts a one-cavity multi-layer MCX-JE/MCX-KYD-1 connector mutual insertion structure to be matched, so that the radio-frequency-free cable assembly on the structure is realized, the volume and the weight of the structure are greatly reduced, the internal space utilization is realized to the maximum extent, and simultaneously, a large amount of material cost and assembly cost are also saved;
3. the dual-mode anti-interference processing unit adopts an ARM processor, and a serial port is led out through the ARM processor, so that the results of self detection and interference detection of an anti-interference processing PCB can be output, and the control of an upper computer is facilitated;
4. the radio frequency input connector and the radio frequency output connector of the dual-mode anti-interference processing unit module have a short circuit protection function, so that the dual-mode anti-interference processing unit module has an anti-burnout capability.
Drawings
Fig. 1 is a schematic diagram of a dual-mode anti-interference processing module according to this embodiment;
fig. 2 is an external view of the dual-mode anti-interference processing module according to the embodiment;
fig. 3 is a top view of the dual-mode anti-interference processing module according to this embodiment;
fig. 4 is a front view of the dual-mode anti-interference processing module according to this embodiment;
fig. 5 is a right side view of the dual-mode anti-interference processing module according to the embodiment;
fig. 6 is a schematic diagram of a one-cavity multilayer MCX-JE/MCX-KYD15-1 connector plug-in structure of the dual-mode anti-interference processing module according to this embodiment.
Detailed Description
The following is a detailed description of the embodiments of the present invention, and the present embodiment uses the technical solution of the present invention as a basis for developing, and gives detailed implementation and specific operation process, and it is right to further explain the technical solution of the present invention.
The dual-mode anti-interference processing module of the small aerial antenna provided by the embodiment has the circuit principle as shown in fig. 1, and the appearance as shown in fig. 2-5, and comprises a radio frequency signal processing part, a digital signal processing part, an external connector part and a cover plate part.
1. Radio frequency signal processing section
The radio frequency signal processing section includes: 4B 3 down-conversion channels, 4L 1/B1 down-conversion PCBs, 1B 3 local oscillation PCB, 1L 1/B1 local oscillation PCB, 1B 3 up-conversion output PCB and 1L 1/B1 up-conversion output PCB; the B3 local oscillator PCB is connected with each B3 down-conversion channel PCB and the B3 up-conversion output PCB; the L1/B1 local oscillation PCB is connected with each L1/B1 down-conversion channel PCB and each L1/B1 up-conversion output PCB; and the local oscillator PCB of each mode is used for down-conversion and up-conversion processing.
In the present invention, B3 is an abbreviation of BDS B3, L1 is an abbreviation of GPS L1, and B1 is an abbreviation of BDS B1.
For the down-conversion and up-conversion processing, 4B 3 power protection PCBs, 4L 1/B1 power protection PCBs, 1B 3 clock switching PCB, 1L 1/B1 clock switching PCB, 1B 3 power +5V switching PCB, and 1L 1/B1 power +5V switching PCB are additionally required, and the down-conversion and up-conversion processing of each mode is completed by using the prior art, which is not elaborated in detail in this embodiment.
2. Digital signal processing section
The digital signal processing section includes: 1B 3 signal processing PCB, 1L 1/B1 signal processing PCB and 1 serial port drive PCB; each signal processing PCB includes an AD conversion unit, an FPGA, and a DA converter, and each AD conversion unit includes 4 AD converters.
The input ends of the 4 AD converters on the B3 signal processing PCB are connected with the output ends of the 4B 3 down-conversion channels, and the output ends of the 4 AD converters are connected with the FPGA on the signal processing PCB; and the input end of the DA converter on the B3 signal processing PCB is connected with the FPGA on the signal processing PCB, and the output end of the DA converter is connected with the B3 up-conversion output PCB.
The input end of the 4 AD converters on the L1/B1 signal processing PCB is connected with the output ends of the 4L 1/B1 down-conversion channels, and the output end of the 4 AD converters is connected with the FPGA on the signal processing PCB; the input end of the DA converter on the L1/B1 signal processing PCB is connected with the FPGA on the signal processing PCB, and the output end of the DA converter is connected with the L1/B1 up-conversion output PCB.
And an ARM processor is arranged on the serial port drive PCB and is connected with each FPGA and the local oscillation PCB and used for controlling the through mode and the locking mode of the radio frequency channel.
All the PCBs are fixed in the cavity of the whole machine through screws.
3. Internal connection of RF signal processing part and digital signal processing part
An MCX-JE connector is arranged on each signal processing PCB, and an MCX-KYD15-1 connector is arranged on each down-conversion channel PCB and each up-conversion output PCB; the signal processing PCB of each mode is inserted into the MCX-KYD15-1 connector through the MCX-JE connector between the signal processing PCB and the down-conversion channel PCB and the up-conversion output PCB, and as shown in FIG. 6, radio frequency signal transmission between the signal processing PCB and the up-conversion output PCB and the down-conversion channel PCB is realized.
The serial port drive PCB is in communication connection with the signal processing PCB through a low-frequency cable with the model number of J63A/3-MDC1-15 PL.
4. External connector part
The external connector is a connection interface between the dual-mode anti-interference processing module and the outside, and comprises: 8 radio frequency signal input connectors correspondingly connected with the down-conversion channels, 2 radio frequency signal output connectors correspondingly connected with the up-conversion output PCBs, and a low-frequency connector connected with the serial port drive PCBs are arranged on the side face of the cavity of the dual-mode anti-interference processing module.
In the embodiment, all the radio frequency signal input connectors and the radio frequency signal output connectors are MCX-KYD15-1 in model; the model number of the low-frequency connector is J30J-31ZKW-J, a serial port (comprising a UART, an RS232 and/or an RS 422) and a power supply port are arranged on the low-frequency connector J30J-31ZKW-J, the serial port is connected with an IO port of an ARM processor and used for signal processing PCB output self-detection and interference detection results, and the power supply port is used for providing a working power supply for the dual-mode anti-interference processing module. As shown in table 1.
TABLE 1 interface definition for dual-mode anti-interference processing module
| Serial number | Name (R) | Connector model number | Interface definition |
| 1 | X1 | MCX-KYD15-1 | BDS B3-1 radio frequency input |
| 2 | X2 | MCX-KYD15-1 | BDS B3-2 radio frequency input |
| 3 | X3 | MCX-KYD15-1 | BDS B3-3 radio frequency input |
| 4 | X4 | MCX-KYD15-1 | BDS B3-4 radio frequency input |
| 5 | X5 | MCX-KYD15-1 | GPS L1/BDS B1-1 radio frequency input |
| 6 | X6 | MCX-KYD15-1 | GPS L1/BDS B1-2 radio frequency input |
| 7 | X7 | MCX-KYD15-1 | GPS L1/BDS B1-3 |
| 8 | X8 | MCX-KYD15-1 | GPS L1/BDS B1-4 radio frequency input |
| 9 | X9 | MCX-KYD15-1 | GPS L1/BDS B1 radio frequency output |
| 10 | X10 | MCX-KYD15-1 | BDS B3 radio frequency output |
| 11 | X11 | J30J-31ZKW-J | Serial communication and power supply |
5. Cover plate part
The cover plate of the embodiment mainly comprises 2 radio frequency channel cover plates, 2 local oscillator cover plates and 2 signal processing cover plates; the 2 radio frequency channel cover plates are used for protecting down-conversion channel PCBs and up-conversion output PCBs in various modes, the 2 local oscillator cover plates are used for protecting local oscillator PCBs in various modes, and the 2 signal processing cover plates are used for protecting signal processing PCBs in various modes.
In a specific embodiment, the cover plate portion includes 1B 3 channel cover plate, 1B 3 signal processing cover plate, 1B 1/L1 channel cover plate, 1B 1/L1 signal processing cover plate, 2 local oscillator cover plates, 1 complete machine cavity, and 1 serial port drive plate cover plate; in the cavity of the double-mode anti-interference processing unit, a signal processing PCB is positioned on the upper layer of a radio frequency down-conversion channel PCB, and a local oscillation PCB is positioned in a gap between the radio frequency down-conversion channel PCB and the signal processing PCB; the radio frequency channel cover plate is arranged at the bottom of the whole machine cavity of the signal processing unit and is used for protecting the down-conversion channel PCB; the signal processing cover plate is arranged at the top of the cavity of the whole signal processing unit and is used for protecting the signal processing PCB; the local oscillator cover plate is arranged above the local oscillator PCB and used for protecting the local oscillator PCB. The B3 channel cover plate, the B3 signal processing cover plate, the L1/B1 channel cover plate, the L1/B1 signal processing cover plate, the local oscillator cover plate, the whole machine cavity and the serial port drive plate cover plate are all made of aluminum alloy materials.
6. Working principle of dual-mode anti-interference processing module
Each down-conversion channel PCB comprises a down-conversion circuit, a power amplifier PA and an intermediate frequency filter BPF, the local oscillator PCB comprises a local oscillator and an ARM single chip microcomputer, and the up-conversion output PCB comprises an up-conversion circuit and the like.
The down-conversion channel PCBs in various modes perform SAW (surface acoustic wave) filtering, down-conversion, power amplification and intermediate frequency filtering on the received radio frequency signals, convert the radio frequency signals into intermediate frequency signals and output the intermediate frequency signals to the signal processing PCBs in corresponding modes; the method comprises the following steps that 4 paths of intermediate frequency signals of any frequency points of GPSL1/BDS B1 and BDS B3 are subjected to AD conversion in a signal processing PCB, then array anti-interference signal processing is completed in an FPGA, and then DA conversion is carried out to output anti-interference processed intermediate frequency analog signals; and the up-conversion output PCB receives the intermediate frequency analog signal subjected to the anti-interference processing from the signal processing PCB and outputs the intermediate frequency analog signal through up-conversion.
The low-frequency connector J30J-31ZKW-J is provided with a serial port to be connected to the ARM processor, and can be controlled by the ARM processor to achieve the functions of updating the working data of the whole machine, outputting interference information, controlling debugging of the whole machine and the like.
It should be noted that the utility model discloses require the integrated configuration mode between each PCB to be used for the array antenna unit of collocation GPSL1 BDS B1 and BDS B3 bimodulus four-array element, the low noise that involves in the concrete module is put, the sound table filtering, down conversion, power amplification, intermediate frequency filtering, ADC, FPGA is anti-jamming, DAC, ARM control close the way merit and divide, direct and processing technology means such as locking mode control, all belong to prior art, the utility model discloses no longer specifically explain.
The above embodiments are preferred embodiments of the present application, and those skilled in the art can make various changes or modifications without departing from the general concept of the present application, and such changes or modifications should fall within the scope of the claims of the present application.
Claims (9)
1. A dual-mode anti-interference processing module of a small aerial antenna is characterized by comprising: a radio frequency signal processing section and a digital signal processing section;
the radio frequency signal processing section includes: 2 down-conversion channels PCB, local oscillator PCB and up-conversion output PCB which are all corresponding to 2 modes of B3 and L1/B1, wherein the down-conversion channel PCB of each mode comprises 4 down-conversion channels; the local oscillation PCB of each mode is connected with the down-conversion channel and the up-conversion output PCB of the corresponding mode and is used for down-conversion and up-conversion processing;
the digital signal processing section includes: the system comprises a serial port drive PCB and 2 signal processing PCBs corresponding to 2 modes of B3 and L1/B1, wherein each signal processing PCB comprises an AD conversion unit, an FPGA and a DA converter, and each AD conversion unit comprises 4 AD converters; for each mode of B3 and L1/B1, the input ends of 4 AD converters are connected with the output ends of 4 down-conversion channels, the output end of each AD converter and the input end of a DA converter are connected with the FPGA, and the output end of the DA converter is connected with the up-conversion output PCB; and an ARM processor is arranged on the serial port drive PCB and is connected with each FPGA and the local oscillation PCB.
2. The dual-mode anti-interference processing module according to claim 1, wherein each signal processing PCB is provided with an MCX-JE connector, and each down-conversion channel PCB and up-conversion output PCB are provided with an MCX-KYD15-1 connector; and between the signal processing PCB and the down-conversion channel PCB and the up-conversion output PCB in each mode, the radio frequency signal transmission between the signal processing PCB and the up-conversion output PCB and the down-conversion channel PCB is realized by the mutual insertion of the MCX-JE connector and the MCX-KYD15-1 connector.
3. The dual-mode anti-interference processing module of claim 1, wherein the serial driver PCB and the signal processing PCB are communicatively connected via a low frequency cable of type J63A/3-MDC1-15 PL.
4. The dual-mode anti-interference processing module of claim 1, further comprising an external connector: 8 radio frequency signal input connectors correspondingly connected with the down-conversion channels, 2 radio frequency signal output connectors correspondingly connected with the up-conversion output PCBs and a low-frequency connector connected with the serial port drive PCBs.
5. The dual mode anti-interference processing module of claim 4, wherein the radio frequency signal input connector and the radio frequency signal output connector are both MCX-KYD15-1.
6. The dual-mode anti-interference processing module of claim 4, wherein the low-frequency connector is of type J30J-31ZKW-J.
7. The dual-mode anti-interference processing module according to claim 6, wherein the low-frequency connectors J30J-31ZKW-J are provided with a serial port and a power supply port, the serial port is connected to an IO port of an ARM processor, and the power supply port is configured to provide a working power supply to the dual-mode anti-interference processing module.
8. The dual-mode anti-interference processing module of claim 1, further comprising 2 rf channel covers, 2 local oscillator covers, and 2 signal processing covers; 2 radio frequency channel apron is used for protecting the down conversion channel PCB and the up conversion output PCB of various modes, 2 local oscillator apron is used for protecting the local oscillator PCB of various modes, 2 signal processing apron is used for protecting the signal processing PCB of various modes.
9. The dual-mode anti-interference processing module of claim 8, wherein the cover plates are made of aluminum alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221001005.2U CN217693347U (en) | 2022-04-28 | 2022-04-28 | Dual-mode anti-interference processing module of small aerial antenna |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221001005.2U CN217693347U (en) | 2022-04-28 | 2022-04-28 | Dual-mode anti-interference processing module of small aerial antenna |
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| Publication Number | Publication Date |
|---|---|
| CN217693347U true CN217693347U (en) | 2022-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221001005.2U Expired - Fee Related CN217693347U (en) | 2022-04-28 | 2022-04-28 | Dual-mode anti-interference processing module of small aerial antenna |
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| Country | Link |
|---|---|
| CN (1) | CN217693347U (en) |
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- 2022-04-28 CN CN202221001005.2U patent/CN217693347U/en not_active Expired - Fee Related
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