CN217693293U - Level conversion circuit - Google Patents

Abstract

The utility model discloses a level conversion circuit. The level conversion circuit comprises a third PMOS tube, a fourth PMOS tube, a first bidirectional diode unit, a second bidirectional diode unit and a first phase inverter, wherein when a low logic signal level is input at a low voltage input end, the low logic signal level is converted into a first voltage output level through the first phase inverter and enters the second bidirectional diode unit, the first voltage output level passes through the fourth PMOS tube, the high voltage output level of the fourth PMOS tube is pulled down to the first voltage output level, the first voltage output level of a low logic signal is output from a high voltage output end, when a high logic signal level is input at the low voltage input end, the high logic signal level enters the first bidirectional diode unit, the drain electrodes of the third PMOS tube and the fourth PMOS tube are pulled up to the high voltage output level, and the high voltage output level of the high logic signal is output from the output end. Which ensures that the level shifter circuit can operate in an over-voltage condition.

Description

Level conversion circuit

Technical Field

The utility model relates to an integrated circuit technical field especially relates to a level shift circuit.

Background

In many semiconductor integrated circuits, there is often a shadow of a level shift circuit, and particularly in some interface circuits, it is often required to work across a voltage domain, so the level shift circuit is widely applied. The level conversion circuit comprises a high-voltage level conversion circuit and a low-voltage level conversion circuit, wherein the high-voltage level conversion circuit converts a low-voltage signal into a high-voltage signal so as to realize the control of a low-voltage logic on the high-voltage logic, and the low-voltage level conversion circuit converts the high-voltage signal into a low-voltage signal so as to realize the control of the high-voltage logic on the low-voltage logic. Generally, a level shift circuit often refers to a high voltage level shift circuit, and a conventional level shift circuit is composed of four high voltage transistors. Two high voltage PMOS tubes are used for pull-up, and two high voltage NMOS tubes are used for pull-down. The grid electrodes of the two high-voltage NMOS tubes are used as two input ends of the level conversion circuit, and the voltage of the input ends is low voltage potential. The drains of the two high-voltage PMOS tubes are used as two output ends of the level conversion circuit, and the voltage of the output end is a high-voltage potential. Because the two high-voltage NMOS tubes work under the condition of low voltage, the pull-down capability of the two high-voltage NMOS tubes is very weak, when the low voltage value is low to a certain degree, the level conversion circuit cannot work, namely, the function of level conversion cannot be realized, particularly, under a small-size process node, the power supply voltage of the circuit far exceeds the range which can be born by a device, and therefore, the high-voltage high-speed circuit conversion cannot be realized by using the structure of the traditional level conversion circuit under the condition.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a level shift circuit to all MOS pipes in solving the level shift circuit do not exceed its withstand voltage scope, realize the fast-speed level shift's of signal problem.

In order to solve the above problem, the utility model provides a level conversion circuit, include: low-voltage input end, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe and output, its characterized in that, it still includes:

a third PMOS tube, a fourth PMOS tube, a first bidirectional diode unit,A second bi-directional diode unit, a first inverter, a gate of the first NMOS transistor electrically connected to the low voltage input terminal, a drain of the first NMOS transistor electrically connected to one end of the first bi-directional diode unit, another end of the first bi-directional diode unit electrically connected to a drain of the third PMOS transistor, a gate of the second NMOS transistor electrically connected to an output of the first inverter, an input of the first inverter electrically connected to the low voltage input terminal, a drain of the second NMOS transistor electrically connected to one end of the second bi-directional diode unit, another end of the second bi-directional diode unit electrically connected to a drain of the fourth PMOS transistor, a source of the first PMOS transistor electrically connected to a third power supply, a drain of the first PMOS transistor electrically connected to a source of the third PMOS transistor, the drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor, the source of the second PMOS transistor is electrically connected to a third power supply, the drain of the second PMOS transistor is electrically connected to the source of the fourth PMOS transistor, the gate of the third PMOS transistor is connected to a first bias voltage, the gate of the fourth PMOS transistor is connected to a first bias voltage, when a low-logic signal (low-logic signal level is 0V) is input to the low-voltage input terminal, the low-logic signal level is converted into a first voltage output level through a first inverter, the first voltage output level enters the second NMOS transistor and the second bidirectional diode unit, the high-voltage output level is pulled down to the first voltage output level through the fourth PMOS transistor, the first PMOS transistor and the second PMOS transistor, so that the pull-up path thereof is closed, and a low-logic signal (first voltage output level is VBIAS _ P + | V) _TP And |) is output from an output end, when a high logic signal (the high logic signal level is VDD 1) is input to the low-voltage input end, the high logic signal level enters the first bidirectional diode unit through the first NMOS transistor, and the drains of the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are pulled up to the high-voltage output level, so that the high logic signal (the high-voltage output level is VDD 3) is output from the output end.

Optionally, the first bidirectional diode unit includes: seventh and eleventh NMOS and PMOS transistors, the second bidirectional diode unit including: the gate of the seventh NMOS transistor is electrically connected with the source of the eleventh PMOS transistor, the source of the seventh NMOS transistor is electrically connected with the drain of the first NMOS transistor, the drain of the seventh NMOS transistor is electrically connected with the drain of the eleventh PMOS transistor, the gate of the eleventh PMOS transistor is electrically connected with the source of the seventh NMOS transistor, the gate of the eighth NMOS transistor is electrically connected with the source of the twelfth PMOS transistor, the source of the eighth NMOS transistor is electrically connected with the drain of the second NMOS transistor, the drain of the eighth NMOS transistor is electrically connected with the drain of the twelfth PMOS transistor, and the gate of the twelfth PMOS is electrically connected with the source of the eighth NMOS transistor.

Optionally, the level shift circuit further comprises: a level feedback unit, the level feedback unit comprising: the source electrode of the ninth PMOS tube is electrically connected with the grid electrode of the second PMOS tube, the drain electrode of the ninth PMOS tube is electrically connected with the drain electrode of the third PMOS tube and the source electrode of the eleventh PMOS tube, the source electrode of the tenth PMOS tube is electrically connected with the grid electrode of the first PMOS tube, and the drain electrode of the tenth PMOS tube is electrically connected with the drain electrode of the fourth PMOS tube and the source electrode of the twelfth PMOS tube.

Optionally, the level shift circuit further includes a power-on reset unit, where the power-on reset unit includes a seventh PMOS transistor and a fifth NMOS transistor, a source of the seventh PMOS transistor is electrically connected to the third power supply, a drain of the seventh PMOS transistor is electrically connected to the output terminal, a source of the fifth NMOS transistor is grounded, and a drain of the fifth NMOS transistor is electrically connected to one end of the first bidirectional diode unit.

Optionally, the level shift circuit further comprises: the voltage drop control unit comprises a third NMOS tube, a fourth NMOS tube, an eighth PMOS tube and a sixth NMOS tube, wherein the grid electrode of the third NMOS tube is connected with a third bias voltage, the source electrode of the third NMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube is electrically connected with the source electrode of the seventh NMOS tube, the grid electrode of the fourth NMOS tube is connected with the third bias voltage, the source electrode of the fourth NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is electrically connected with the source electrode of the eighth NMOS tube, the grid electrode of the eighth PMOS tube is connected with the second bias voltage, the source electrode of the eighth PMOS tube is electrically connected with the output end and the drain electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube is electrically connected with the drain electrode of the fourth PMOS tube and the drain electrode of the tenth PMOS tube, the source electrode of the sixth NMOS tube is electrically connected with the drain electrode of the fifth NMOS tube, and the drain electrode of the sixth NMOS tube is electrically connected with the drain electrode of the third NMOS tube.

Optionally, the level shift circuit further comprises: and the input end of the second phase inverter is connected with a second reset signal, and the output end of the second phase inverter is electrically connected with the grid electrode of the fifth NMOS tube.

Optionally, the level shift circuit further comprises: the grid electrode of the fifth PMOS tube is electrically connected with the third power supply and the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube is electrically connected with the grid electrode of the first PMOS tube, the source electrode of the sixth PMOS tube is electrically connected with the third power supply, the grid electrode of the sixth PMOS tube is electrically connected with the third power supply, and the drain electrode of the sixth PMOS tube is electrically connected with the grid electrode of the second PMOS tube.

Compared with the prior art, the level conversion circuit comprises a third PMOS tube, a fourth PMOS tube, a first bidirectional diode unit, a second bidirectional diode unit and a first phase inverter, wherein the grid electrode of the first NMOS tube is electrically connected with a low-voltage input end, the drain electrode of the first NMOS tube is electrically connected with one end of the first bidirectional diode unit, the other end of the first bidirectional diode unit is electrically connected with the drain electrode of the third PMOS tube, the grid electrode of the second NMOS tube is electrically connected with the output end of the first phase inverter, the input end of the first phase inverter is electrically connected with a low-voltage input end, the drain electrode of the second NMOS tube is electrically connected with one end of the second bidirectional diode unit, the other end of the second bidirectional diode unit is electrically connected with the drain electrode of the fourth PMOS tube, and the source electrode of the first PMOS tube is electrically connected with a third power supplyThe drain electrode of the first PMOS tube is electrically connected with the source electrode of the third PMOS tube, the drain electrode of the second PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, the source electrode of the second PMOS tube is electrically connected with the third power supply, the drain electrode of the second PMOS tube is electrically connected with the source electrode of the fourth PMOS tube, the grid electrode of the third PMOS tube is connected with a first bias voltage, the grid electrode of the fourth PMOS tube is connected with the first bias voltage, when a low-logic signal (the low-logic signal level is 0V) is input at the low-voltage input end, the low-logic signal level is converted into a first voltage output level through the first inverter and enters the second NMOS tube and the second bidirectional diode unit, the first voltage output level passes through the fourth PMOS tube, the first PMOS tube and the second PMOS tube, the high-voltage output level of the fourth PMOS tube is pulled down to the first voltage output level, so the pull-up channel is closed, and the low-logic signal (the first voltage output level is VBIAS _ P + | V) _TP And |) is output from the output end, when a high logic signal (the high logic signal level is VDD 1) is input from the low-voltage input end, the high logic signal level enters the first bidirectional diode unit through the first NMOS transistor, the drains of the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are pulled high to the high-voltage output level, and the high logic signal (the high-voltage output level is VDD 3) is output from the output end. The voltage-stabilizing circuit can ensure that all MOS tubes in the level conversion circuit work within the maximum withstand voltage, so that the level conversion circuit can work in an overvoltage state.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the level shift circuit of the present invention.

Fig. 2 is a schematic structural diagram of another derivative circuit of the level shifter circuit of the present invention.

Fig. 3 is a schematic structural diagram of another derivative circuit of the level shifter circuit of the present invention.

Fig. 4 is a schematic structural diagram of another derivative circuit of the level shifter circuit of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 1 shows an embodiment of the level shift circuit of the present invention. In this embodiment, the level conversion circuit includes: low-voltage input end 0, first NMOS pipe 1, second NMOS pipe 3, first PMOS pipe 41, second PMOS pipe 42 and output 5, it still includes:

a third PMOS transistor 43, a fourth PMOS transistor 44, a first bi-directional diode unit 63, a second bi-directional diode unit 64, wherein the gate of the first NMOS transistor 1 is electrically connected to the low voltage input terminal 0, the drain of the first NMOS transistor 1 is electrically connected to one end of the first bi-directional diode unit 63, the other end of the first bi-directional diode unit 63 is electrically connected to the drain of the third PMOS transistor 43, the gate of the second NMOS transistor 3 is electrically connected to the output terminal of the first inverter 2, the input end of the first inverter 2 is electrically connected to the low voltage input end 0, the drain of the second NMOS transistor 3 is electrically connected to one end of the second bidirectional diode unit 64, the other end of the second bidirectional diode unit 64 is electrically connected to the drain of the fourth PMOS transistor 44, the source of the first PMOS transistor 41 is electrically connected to the third power supply, the drain of the first PMOS transistor 41 is electrically connected to the source of the third PMOS transistor 43, the drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44, the source of the second PMOS transistor 42 is electrically connected to the third power supply, the drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44, the gate of the third PMOS transistor 43 is connected to the first bias voltage, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage, when a low logic signal (low logic signal level is 0V) is inputted to the low voltage input terminal 0, the low logic signal level is converted into a first voltage output level by the first inverter 2, and enters the second NMOS transistor 3 and the second bidirectional diode unit 64, the first voltage output level passes through the fourth PMOS transistor 44, the first PMOS transistor 41, the second PMOS transistor 42, its high voltage output level is pulled down to the first voltage output level, so the pull-up path is closed, and a low logic signal (the first voltage output level is VBIAS _ P + | V) is sent. _TP I) is output from the output terminal 5, when the low voltage input terminal 0 inputs a high logic signal (the high logic signal level is VDD 1), the high logic signal level passes through the first NMOS transistor1 enters the first bidirectional diode unit 63, and the drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled high to a high voltage output level, outputting a high logic signal (the high voltage output level is VDD 3) from the output terminal 5.

It should be noted that, when the conventional level shift circuit is applied to different power supplies, the power supply voltage is in the operating range of the PMOS transistor and the NMOS transistor in the level shift circuit, but if the low-voltage logic is shifted to the high-voltage logic whose level exceeds the withstand voltage range of the MOS transistor itself, the conventional level shift circuit cannot be used.

Specifically, when the low-voltage input terminal 0 inputs a low-logic signal (the low-logic signal level is 0V), the first NMOS transistor is turned off, and the low-logic signal level is converted into a first voltage output level (the voltage is about VBIAS _ P + | V) by the first inverter 2 _TP |) into the second NMOS transistor 3 and the second bidirectional diode unit 64, the gate signal of the first PMOS transistor 41 is pulled low (voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the first PMOS transistor 41 is logic low (voltage is about VBIAS _ P + | V) _TP In |), since the gate signal of the third PMOS transistor 43 is input with the first bias voltage VBIAS _ P, the third PMOS transistor 43 is turned on, the drain of the third PMOS transistor 43 is pulled up to a high voltage, and similarly, the gate of the second PMOS transistor 42 is pulled up to a high voltage (voltage about VDD 3), the first voltage output level is pulled down to the first voltage output level through the fourth PMOS transistor 44, the first PMOS transistor 41, and the second PMOS transistor 42, so as to close its pull-up path, and the low logic signal (the first voltage output level is VBIAS _ P + | V) is transmitted to the second PMOS transistor 42 _TP |) is outputted from the output terminal 5, when the low voltage input terminal 0 inputs a high logic signal (the high logic signal level is VDD 1), the second NMOS transistor 3 is turned off, the high logic signal level enters the first bidirectional diode unit 63 through the first NMOS transistor 1, and the gate signal of the second PMOS transistor 42 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP |), the drain is pulled up to the high voltage VDD3, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS _ P, so that the fourth PMOS transistorWhen the transistor 44 is turned on, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the drain of the fourth PMOS transistor 44 is pulled up to the high voltage, and similarly, the gate of the first PMOS transistor 41 is pulled up to the high voltage (voltage about VDD 3), and the drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled up to the high voltage output level, so as to output the high logic signal (high voltage output level is VDD 3) from the output terminal 5.

The level shift circuit of this embodiment is electrically connected to the low voltage input terminal 0 through the gate of the first NMOS transistor 1, the drain of the first NMOS transistor 1 is electrically connected to one end of the first bidirectional diode unit 63, the other end of the first bidirectional diode unit 63 is electrically connected to the drain of the third PMOS transistor 43, the gate of the second NMOS transistor 3 is electrically connected to the output of the first inverter 2, the input of the first inverter 2 is electrically connected to the low voltage input terminal 0, the drain of the second NMOS transistor 3 is electrically connected to one end of the second bidirectional diode unit 64, the other end of the second bidirectional diode unit 64 is electrically connected to the drain of the fourth PMOS transistor 44, the source of the first PMOS transistor 41 is electrically connected to the third power supply, the drain of the first PMOS transistor 41 is electrically connected to the source of the third PMOS transistor 43, the drain of the second PMOS transistor 42 is electrically connected to the source of the fourth PMOS transistor 44, the third PMOS transistor 43 is electrically connected to the gate of the fourth PMOS transistor 44, and the gate of the fourth PMOS transistor 44 is connected to the bias voltage. The utility model discloses a when low-voltage input end 0 input low logic signal (low logic signal level is 0V), first NMOS pipe is by, and first NMOS pipe is closed, and low logic signal level converts first voltage output level (voltage is about VBIAS _ P + | V) into through first phase inverter 2 _TP |) into the second NMOS transistor 3 and the second bidirectional diode unit 64, the gate signal of the first PMOS transistor 41 is pulled low (voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the first PMOS transistor 41 is logic low (voltage is about VBIAS _ P + | V) _TP |) because the gate signal of the third PMOS transistor 43 is inputted with the first bias voltage VBIAS _ P, the third PMOS transistor 43 is in a conducting state, the drain of the third PMOS transistor 43 is pulled up to a high voltage, and similarly, the second PMOS transistor 43 is pulled up to a high voltageThe gate of the transistor 42 is pulled high (voltage is about VDD 3), the first voltage output level is pulled low to the first voltage output level through the fourth PMOS transistor 44, the first PMOS transistor 41 and the second PMOS transistor 42, so that the pull-up path is closed, and a low logic signal (the first voltage output level is VBIAS _ P + | V) _TP |) is outputted from the output terminal 5, when the low voltage input terminal 0 inputs a high logic signal (the high logic signal level is VDD 1), the second NMOS transistor 3 is turned off, the high logic signal level enters the first bidirectional diode unit 63 through the first NMOS transistor 1, and the gate signal of the second PMOS transistor 42 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP In this case, the drain of the level shifter circuit is pulled up to the high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the input of the first bias voltage VBIAS _ P, the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the drain of the fourth PMOS transistor 44 is pulled up to the high voltage, and similarly, the gate of the first PMOS transistor 41 is pulled up to the high voltage (voltage about VDD 3), the drains of the second PMOS transistor 42, the third PMOS transistor 43, and the fourth PMOS transistor 44 are pulled up to the high voltage output level, so as to output the high logic signal (high voltage output level VDD 3) from the output terminal 5, which can ensure that all MOS transistors in the level shifter circuit operate within the maximum withstand voltage thereof, thereby enabling the level shifter circuit to operate in an overvoltage state.

Further, the first bidirectional diode unit 63 includes: seventh NMOS transistor 631 and eleventh PMOS transistor 632, the second bidirectional diode unit 64 includes: the eighth NMOS 641 and the twelfth PMOS 642, the gate of the seventh NMOS 631 is electrically connected to the source of the eleventh PMOS 632, the source of the seventh NMOS 631 is electrically connected to the drain of the first NMOS 1, the drain of the seventh NMOS 631 is electrically connected to the drain of the eleventh PMOS 632, the gate of the eleventh PMOS 632 is electrically connected to the source of the seventh NMOS 631, the gate of the eighth NMOS 641 is electrically connected to the source of the twelfth PMOS 642, the source of the eighth NMOS 641 is electrically connected to the drain of the second NMOS 3, the drain of the eighth NMOS 641 is electrically connected to the drain of the twelfth PMOS 642, and the gate of the twelfth PMOS 642 is electrically connected to the source of the eighth NMOS 641.

It should be noted that the first and second bi-directional diode units 63 and 64 function as a voltage drop, that is, a "kick voltage", such that the source voltage of the NMOS below is always one V lower than the source voltage of the PMOS above _TH (|V _TP L or V _TN )。

Specifically, when the input signal at the low voltage input terminal 0 is low (voltage is about 0), the first NMOS transistor 1 is turned off, and the drain of the second NMOS transistor 3 is pulled low (voltage is about 0). The voltage enters the fourth PMOS transistor 44 and the tenth PMOS transistor 48 through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642. The signal of the tenth PMOS transistor 48 is input with the first bias voltage VBIAS _ P, so that the tenth PMOS transistor 48 is in a conducting state, and the gate signal of the first PMOS transistor 41 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the first PMOS transistor 41 is logic low (voltage is about VBIAS _ P + | V) _TP I), its drain is pulled high to the high voltage VDD3. Since the gate signal of the third PMOS transistor 43 is inputted with the first bias voltage VBIAS _ P, the third PMOS transistor 43 is in a conducting state, the drain of the third PMOS transistor 43 is pulled up to the high voltage VDD3, and similarly, the ninth PMOS transistor 47 is also in a conducting state, the gate of the second PMOS transistor 42 is pulled up to the high voltage (voltage about VDD 3), the pull-up path is closed, thereby ensuring that the drain of the tenth PMOS transistor 48 is logic low (voltage about V), and the voltage is about V _TN ) The state of (c). When the input signal at the low voltage input terminal 0 is at a high level (voltage is about VDD 1), the first NMOS transistor 1 is turned on, and the drain thereof is pulled low (voltage is about 0), thereby turning off the second NMOS transistor 3. The voltage enters the third PMOS transistor 43 and the ninth PMOS transistor 47 through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632. The signal at the drain of the ninth PMOS 47 is also pulled low (voltage is about V) _TN ) Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS _ P, the ninth PMOS transistor 47 is turned on, and the gate signal of the second PMOS transistor 42 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP I), thenThe drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and since the gate of the fourth PMOS transistor 44 is connected to the input of the first bias voltage VBIAS _ P, the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and similarly, the tenth PMOS transistor 48 is also in a conducting state, the gate of the first PMOS transistor 41 is pulled up (voltage about VDD 3), the pull-up path is closed, thereby ensuring that the drain of the ninth PMOS transistor 47 is in a logic low state (voltage about V) _TN ) The state of (1).

Further, the level shift circuit further includes a level feedback unit 4, and the level feedback unit 4 includes: a ninth PMOS transistor 47 and a tenth PMOS transistor 48, wherein a source of the ninth PMOS transistor 47 is electrically connected to the gate of the second PMOS transistor 42, a drain of the ninth PMOS transistor 47 is electrically connected to the drain of the third PMOS transistor 43 and the source of the eleventh PMOS transistor 632, a source of the tenth PMOS transistor 48 is electrically connected to the gate of the first PMOS transistor 41, and a drain of the tenth PMOS transistor 48 is electrically connected to the drain of the fourth PMOS transistor 44 and the source of the twelfth PMOS transistor 642.

Specifically, when the input signal at the low voltage input terminal 0 is low level (voltage is about 0), the signal of the tenth PMOS transistor 48 in the level feedback unit 4 is input with the first bias voltage VBIAS _ P, so that the tenth PMOS transistor 48 is in a conducting state, and the gate signal of the first PMOS transistor 41 is pulled low (voltage is about VBIAS _ P + | V |) _TP |). Since the gate signal of the first PMOS transistor 41 is logic low (voltage is about VBIAS _ P + | V) _TP I), its drain is pulled high to the high voltage VDD3. Since the gate signal of the third PMOS transistor 43 is inputted with the first bias voltage VBIAS _ P, the third PMOS transistor 43 is in a conducting state, the drain of the third PMOS transistor 43 is pulled up to the high voltage VDD3, and similarly, the ninth PMOS transistor 47 is also in a conducting state, the gate of the second PMOS transistor 42 is pulled up to the high voltage (voltage about VDD 3), the pull-up path is closed, thereby ensuring that the drain of the tenth PMOS transistor 48 is logic low (voltage about V), and the voltage is about V _TN ) The state of (1). When the input signal at the low voltage input terminal 0 is a high level signal (voltage is about VDD 1), the signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage is about V) _TN ) Since the gate of the ninth PMOS tube 47 is connected to the first bias voltage VBIAS _ P, the ninth PMOS tube 47 is turned onIn this state, the gate signal of the second PMOS transistor 42 is pulled low (voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP I), the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS _ P, so that the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and similarly, the tenth PMOS transistor 48 is also in a conducting state, the gate of the first PMOS transistor 41 is pulled up (voltage about VDD 3), the pull-up path is closed, and the drain of the ninth PMOS transistor 47 is ensured to be logic low (voltage about V), thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage about VDD 3) _TN ) The state of (c).

Further, the level shift circuit further includes a power-on reset unit 6, where the power-on reset unit 6 includes a seventh PMOS transistor 45 and a fifth NMOS transistor 73, a source of the seventh PMOS transistor 45 is electrically connected to the third power supply, a drain of the seventh PMOS transistor 45 is electrically connected to the output terminal, a source of the fifth NMOS transistor 73 is grounded, and a drain of the fifth NMOS transistor 73 is electrically connected to one end of the first bidirectional diode unit 63.

It should be noted that, when the power-on reset circuit is operated, the power supply is not powered on, that is, the power supply is not powered on, and the power supply voltage may slowly rise but does not reach the voltage value for normal operation. When the power supply is normal, namely the power supply is powered on, the power-on reset circuit cannot work, and the whole function (level conversion) of the circuit can be carried out. It is present to help the circuit in the power-up process (when the power supply does not reach the normal state) with the voltage at each node in the normal state.

Specifically, when the power supply VDD3 is powered on, the second reset signal S2_ PORN is input, and since the second reset signal S2_ PORN is logic low (voltage is about 0), the drain of the fifth NMOS transistor 73 is pulled low (voltage is about 0). The seventh NMOS transistor 631 and the eleventh PMOS transistor 632 form the first bidirectional diode unit 63, and the signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage is about V) _TN ) Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS _ P, the ninth PMOS transistor 47 is turned on, and the gate signal of the second PMOS transistor 42 is pulled low(Voltage is approximately VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP I), the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS _ P, so that the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and similarly, the tenth PMOS transistor 48 is also in a conducting state, the gate of the first PMOS transistor 41 is pulled up (voltage about VDD 3), the pull-up path is closed, and the drain of the ninth PMOS transistor 47 is ensured to be logic low (voltage about V), thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage about VDD 3) _TN ) The state of (1). And since the reset signal S3_ PORN is logic low (about VBIAS _ P + | V) _TP I), the seventh PMOS transistor 45 is turned on to pull up the output terminal 5 to the high voltage VDD3, so that the logic high (voltage about VDD 3) of the output terminal 5 is not affected regardless of whether the input signal is logic high or low. When the power supply VDD3 is powered on, the reset signal S2_ PORN is input, the logic of the S3_ PORN is high, the power-on reset circuit does not work, the circuit can normally work, and the level conversion work can be carried out.

Further, the level shift circuit further includes: a voltage drop control unit 7, the voltage drop control unit 7 includes a third NMOS transistor 61, a fourth NMOS transistor 62, an eighth PMOS transistor 46, and a sixth NMOS transistor 74, a gate of the third NMOS transistor 61 is connected to a third bias voltage, a source of the third NMOS transistor 61 is electrically connected to a drain of the first NMOS transistor 1, a drain of the third NMOS transistor 61 is electrically connected to a source of the seventh NMOS transistor 631, a gate of the fourth NMOS transistor 62 is connected to a third bias voltage, a source of the fourth NMOS transistor 62 is electrically connected to a drain of the second NMOS transistor 3, a drain of the fourth NMOS transistor 62 is electrically connected to a source of the eighth PMOS transistor 641, a gate of the eighth PMOS transistor 46 is connected to a second bias voltage, a source of the eighth PMOS transistor 46 is electrically connected to the output terminal 5 and a drain of the seventh NMOS transistor 45, a drain of the eighth PMOS transistor 46 is electrically connected to a drain of the fourth PMOS transistor 44 and a drain of the tenth PMOS transistor 48, a source of the sixth NMOS transistor 74 is electrically connected to a drain of the fifth PMOS transistor 73, a drain of the sixth NMOS transistor 74 is electrically connected to a drain of the third NMOS transistor 61, and a drain of the third NMOS transistor 74 is electrically connected to a drain of the third NMOS transistor 61.

Specifically, when the input signal at the low voltage input terminal 0 is low (voltage is about 0), the first NMOS transistor 1 is turned off, and the drain of the second NMOS transistor 3 is pulled low (voltage is about 0). The gate of the fourth NMOS transistor 62 receives the third bias voltage VBIAS _ N, so that the fourth NMOS transistor 62 is in a conducting state, and the drain thereof is logic low (voltage is about 0). The voltage enters the fourth PMOS transistor 44 and the tenth PMOS transistor 48 through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642. The signal of the tenth PMOS transistor 48 is input with the first bias voltage VBIAS _ P, so that the tenth PMOS transistor 48 is in a conducting state, and the gate signal of the first PMOS transistor 41 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the first PMOS transistor 41 is logic low (voltage is about VBIAS _ P + | V) _TP I), its drain is pulled high to the high voltage VDD3. Since the gate signal of the third PMOS transistor 43 is inputted with the first bias voltage VBIAS _ P, the third PMOS transistor 43 is in a conducting state, the drain of the third PMOS transistor 43 is pulled up to the high voltage VDD3, and similarly, the ninth PMOS transistor 47 is also in a conducting state, the gate of the second PMOS transistor 42 is pulled up to the high voltage (voltage about VDD 3), the pull-up path is closed, thereby ensuring that the drain of the tenth PMOS transistor 48 is logic low (voltage about V), and the voltage is about V _TN ) The state of (c). And since the reset signal S3_ PORN is logic low (about VBIAS _ P + | V) _TP I), the seventh PMOS transistor 45 is turned on to pull up the output terminal 5 to the high voltage VDD3, and when the input signal at the low voltage input terminal 0 is high level (voltage is about VDD 1), the first NMOS transistor 1 is turned on, and the drain thereof is pulled down (voltage is about 0), thereby turning off the second NMOS transistor 3. The gate of the third NMOS transistor 61 receives the third bias voltage VBIAS _ N, so that the third NMOS transistor 61 is in a conducting state, and the drain thereof is logic low (voltage is about 0). The voltage enters the third PMOS transistor 43 and the ninth PMOS transistor 47 through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632. The signal at the drain of the ninth PMOS 47 is also pulled low (voltage is about V) _TN ) Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS _ P, the ninth PMOS transistor 47 is turned on, and the gate signal of the second PMOS transistor 42 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P +)V _TP I), the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS _ P, so that the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and similarly, the tenth PMOS transistor 48 is also in a conducting state, the gate of the first PMOS transistor 41 is pulled up (voltage about VDD 3), the pull-up path is closed, and the drain of the ninth PMOS transistor 47 is ensured to be logic low (voltage about V), thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage about VDD 3) _TN ) The state of (1). Similarly, the eighth PMOS transistor 46 is turned on, and the output terminal 5 is pulled up to the high voltage VDD3 by the drain of the fourth PMOS transistor 44.

Further, the level shift circuit further includes: the input end of the second inverter 72 is connected to a second reset signal, and the output end of the second inverter is electrically connected to the gate of the fifth NMOS transistor 73.

Specifically, when the input signal at the low voltage input terminal 0 is low (voltage is about 0), the first NMOS transistor 1 is turned off, the output of the first inverter 2 is logic high (voltage is about VDD 1), and the drain of the second NMOS transistor 3 is pulled low (voltage is about 0). The gate of the fourth NMOS transistor 62 receives the third bias voltage VBIAS _ N, so that the fourth NMOS transistor 62 is in a conducting state, and the drain thereof is logic low (voltage is about 0). The voltage enters the fourth PMOS transistor 44 and the tenth PMOS transistor 48 through the eighth NMOS transistor 641 and the twelfth PMOS transistor 642. When the input signal at the low voltage input terminal 0 is at a high level (voltage is about VDD 1), the first NMOS transistor 1 is turned on, the drain thereof is pulled low (voltage is about 0), the output of the first inverter 2 is at a logic low (voltage is about 0), and the second NMOS transistor 3 is turned off. The gate of the third NMOS transistor 61 receives the third bias voltage VBIAS _ N, so that the third NMOS transistor 61 is in a conducting state, and the drain thereof is logic low (voltage is about 0). The voltage enters the third PMOS transistor 43 and the ninth PMOS transistor 47 through the seventh NMOS transistor 631 and the eleventh PMOS transistor 632. When the power supply VDD3 is powered on, the second reset signal S2_ PORN is input, since the second reset signal S2_ PORN is logic low (voltage is about 0), the output end of the second inverter 72 is logic high (voltage is about VDD 2), the drain of the fifth NMOS transistor 73 is pulled down (voltage is about 0), and the gate of the sixth NMOS transistor 74 is connected to the third bias voltage VBIAS _ N, the sixth NMOS transistor 74Is also pulled low (voltage is about 0). The seventh NMOS transistor 631 and the eleventh PMOS transistor 632 form the first bidirectional diode unit 63, and the signal at the drain of the ninth PMOS transistor 47 is also pulled low (voltage is about V) _TN ) Since the gate of the ninth PMOS transistor 47 is connected to the first bias voltage VBIAS _ P, the ninth PMOS transistor 47 is turned on, and the gate signal of the second PMOS transistor 42 is pulled low (the voltage is about VBIAS _ P + | V) _TP |). Since the gate signal of the second PMOS transistor 42 is logic low (voltage is about VBIAS _ P + | V) _TP I), the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and the gate of the fourth PMOS transistor 44 is connected to the first bias voltage VBIAS _ P, so that the fourth PMOS transistor 44 is in a conducting state, the drain of the fourth PMOS transistor 44 is pulled up to the high voltage VDD3, and similarly, the tenth PMOS transistor 48 is also in a conducting state, the gate of the first PMOS transistor 41 is pulled up (voltage about VDD 3), the pull-up path is closed, and the drain of the ninth PMOS transistor 47 is ensured to be logic low (voltage about V), thereby ensuring that the drain of the ninth PMOS transistor 47 is logic low (voltage about VDD 3) _TN ) The state of (1). And since the reset signal S3_ PORN is logic low (about VBIAS _ P + | V) _TP I), the seventh PMOS transistor 45 is turned on to pull up the output terminal 5 to the high voltage VDD3, so that the logic high (voltage about VDD 3) of the output terminal 5 is not affected regardless of whether the input signal is logic high or low.

Further, the level shift circuit further includes: the transistor comprises a fifth PMOS tube 8 and a sixth PMOS tube 9, wherein the source electrode of the fifth PMOS tube 8 is electrically connected with a third power supply, the grid electrode of the fifth PMOS tube 8 is electrically connected with the third power supply and the grid electrode of the sixth PMOS tube 9, the drain electrode of the fifth PMOS tube 8 is electrically connected with the grid electrode of the first PMOS tube 41, the source electrode of the sixth PMOS tube 9 is electrically connected with the third power supply, the grid electrode of the sixth PMOS tube 9 is electrically connected with the third power supply, and the drain electrode 9 of the sixth PMOS tube is electrically connected with the grid electrode of the second PMOS tube 41.

Specifically, when the gates of the first PMOS transistor 41 and the second PMOS transistor 42 are higher than VDD3, a discharge path to the power supply VDD3 can be provided, and the other PMOS transistors in the circuit can also be Dummy transistors.

As shown in fig. 2, the ninth PMOS transistor 47 and the tenth PMOS transistor 48 are removed from fig. 1, and the source of the third PMOS transistor 43 is coupled to the gate of the second PMOS transistor 42, and the source of the fourth PMOS transistor 44 is coupled to the gate of the first PMOS transistor 41. Which is consistent with the effect of fig. 1.

As shown in fig. 3, the seventh NMOS transistor 631, the eleventh PMOS transistor 632, the eighth NMOS transistor 641 and the twelfth PMOS transistor 642 are removed from fig. 1. The pressure drop control measure will be at least one.

As shown in fig. 4, the ninth PMOS transistor 47 and the tenth PMOS transistor 48 are removed from fig. 1, and the source of the third PMOS transistor 43 is coupled to the gate of the second PMOS transistor 42, the source of the fourth PMOS transistor 44 is coupled to the gate of the first PMOS transistor 41, and the seventh NMOS transistor 631, the eleventh PMOS transistor 632, the eighth NMOS transistor 641, and the twelfth PMOS transistor 642 are removed. The pressure drop control measure will be at least one.

The above detailed description of the embodiments of the present invention is only exemplary, and the present invention is not limited to the above described embodiments. It will be apparent to those skilled in the art that any equivalent modifications or substitutions can be made to the present invention without departing from the spirit and scope of the invention, and therefore, all equivalent changes, modifications, improvements, etc. made without departing from the spirit and scope of the invention are intended to be covered by the scope of the invention.

Claims (7)

1. A level shifting circuit, comprising: low-voltage input end, first NMOS pipe, second NMOS pipe, first PMOS pipe, second PMOS pipe and output, its characterized in that, it still includes:

a third PMOS tube, a fourth PMOS tube, a first bidirectional diode unit, a second bidirectional diode unit, a first inverter, wherein the gate of the first NMOS tube is electrically connected with the low voltage input terminal, the drain of the first NMOS tube is electrically connected with one end of the first bidirectional diode unit, the other end of the first bidirectional diode unit is electrically connected with the drain of the third PMOS tube, the gate of the second NMOS tube is electrically connected with the output terminal of the first inverter, the input terminal of the first inverter is electrically connected with the low voltage input terminal, the drain of the second NMOS tube is electrically connected with one end of the second bidirectional diode unit, the other end of the second bidirectional diode unit is electrically connected with the drain of the fourth PMOS tube, the source of the first PMOS tube is electrically connected with a third power supply, and the drain of the first PMOS tube is electrically connected with the source of the third PMOS tube, the drain of the second PMOS tube is electrically connected with the source of the fourth PMOS tube, the source of the second PMOS tube is electrically connected with a third power supply, the drain of the second PMOS tube is electrically connected with the source of the fourth PMOS tube, the gate of the third PMOS tube is connected with a first bias voltage, the gate of the fourth PMOS tube is connected with the first bias voltage, when the low-voltage input end inputs a low-logic signal, the low-logic signal level is converted into a first voltage output level through a first inverter and enters a second NMOS tube and the second bidirectional diode unit, the first voltage output level is pulled down to the first voltage output level through the fourth PMOS tube, the first PMOS tube and the second PMOS tube, so that the pull-up channel is closed, the low-logic signal is output from the output end, when the low-voltage input end inputs a high-logic signal, and the high logic signal level enters the first bidirectional diode unit through the first NMOS tube, and the drain electrodes of the second PMOS tube, the third PMOS tube and the fourth PMOS tube are pulled high to a high voltage output level to output a high logic signal from an output end.

2. The level shift circuit of claim 1, wherein the first bidirectional diode unit comprises: seventh and eleventh NMOS and PMOS transistors, the second bidirectional diode unit including: the gate of the seventh NMOS transistor is electrically connected with the source of the eleventh PMOS transistor, the source of the seventh NMOS transistor is electrically connected with the drain of the first NMOS transistor, the drain of the seventh NMOS transistor is electrically connected with the drain of the eleventh PMOS transistor, the gate of the eleventh PMOS transistor is electrically connected with the source of the seventh NMOS transistor, the gate of the eighth NMOS transistor is electrically connected with the source of the twelfth PMOS transistor, the source of the eighth NMOS transistor is electrically connected with the drain of the second NMOS transistor, the drain of the eighth NMOS transistor is electrically connected with the drain of the twelfth PMOS transistor, and the gate of the twelfth PMOS is electrically connected with the source of the eighth NMOS transistor.

3. The level shift circuit of claim 2, further comprising: a level feedback unit, the level feedback unit comprising: the source electrode of the ninth PMOS tube is electrically connected with the grid electrode of the second PMOS tube, the drain electrode of the ninth PMOS tube is electrically connected with the drain electrode of the third PMOS tube and the source electrode of the eleventh PMOS tube, the source electrode of the tenth PMOS tube is electrically connected with the grid electrode of the first PMOS tube, and the drain electrode of the tenth PMOS tube is electrically connected with the drain electrode of the fourth PMOS tube and the source electrode of the twelfth PMOS tube.

4. The circuit of claim 3, further comprising: the power-on reset unit comprises a seventh PMOS tube and a fifth NMOS tube, wherein the source electrode of the seventh PMOS tube is electrically connected with a third power supply, the drain electrode of the seventh PMOS tube is electrically connected with the output end, the source electrode of the fifth NMOS tube is grounded, and the drain electrode of the fifth NMOS tube is electrically connected with one end of the first bidirectional diode unit.

5. The level shift circuit of claim 4, further comprising: the voltage drop control unit comprises a third NMOS tube, a fourth NMOS tube, an eighth PMOS tube and a sixth NMOS tube, wherein the grid electrode of the third NMOS tube is connected with a third bias voltage, the source electrode of the third NMOS tube is electrically connected with the drain electrode of the first NMOS tube, the drain electrode of the third NMOS tube is electrically connected with the source electrode of the seventh NMOS tube, the grid electrode of the fourth NMOS tube is connected with the third bias voltage, the source electrode of the fourth NMOS tube is electrically connected with the drain electrode of the second NMOS tube, the drain electrode of the fourth NMOS tube is electrically connected with the source electrode of the eighth NMOS tube, the grid electrode of the eighth PMOS tube is connected with the second bias voltage, the source electrode of the eighth PMOS tube is electrically connected with the output end and the drain electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube is electrically connected with the drain electrode of the fourth PMOS tube and the drain electrode of the tenth PMOS tube, the source electrode of the sixth NMOS tube is electrically connected with the drain electrode of the fifth NMOS tube, and the drain electrode of the sixth NMOS tube is electrically connected with the drain electrode of the third NMOS tube.

6. The level shift circuit of claim 5, further comprising: and the input end of the second phase inverter is connected with a second reset signal, and the output end of the second phase inverter is electrically connected with the grid electrode of the fifth NMOS tube.

7. The level shift circuit of claim 6, further comprising: the grid electrode of the fifth PMOS tube is electrically connected with the third power supply and the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube is electrically connected with the grid electrode of the first PMOS tube, the source electrode of the sixth PMOS tube is electrically connected with the third power supply, the grid electrode of the sixth PMOS tube is electrically connected with the third power supply, and the drain electrode of the sixth PMOS tube is electrically connected with the grid electrode of the second PMOS tube.

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