CN217691071U

CN217691071U - Semiconductor processing apparatus and semiconductor processing system

Info

Publication number: CN217691071U
Application number: CN202220659111.3U
Authority: CN
Inventors: 温子瑛
Original assignee: Wuxi Huaying Microelectronics Technology Co Ltd
Current assignee: Wuxi Huaying Microelectronics Technology Co Ltd
Priority date: 2022-03-23
Filing date: 2022-03-23
Publication date: 2022-10-28
Anticipated expiration: 2032-03-23

Abstract

The utility model provides a semiconductor processing device, it includes: a lower chamber having a first support region supporting a wafer; an upper chamber having a second support region, wherein when the upper chamber and the lower chamber are closed, the wafer is disposed between the first support region and the second support region; a temperature control assembly disposed proximate to the upper chamber and/or the lower chamber, which adjusts a temperature of the upper chamber and/or the lower chamber by adjusting a temperature thereof; a first channel formed in an edge region of the first support region or the second support region, the first channel providing a first space for circulation of one or more chemical fluids that erode the edge region of the wafer; and adjusting the temperature of the upper chamber and/or the lower chamber by using the temperature control assembly so as to adjust the corrosion width of the edge of the wafer. In this way, the etch width of the edge of the wafer can be fine-tuned.

Description

Semiconductor processing apparatus and semiconductor processing system

[ technical field ] A method for producing a semiconductor device

The present invention relates to the field of surface treatment of semiconductor wafers or similar workpieces, and more particularly to semiconductor processing apparatus and semiconductor processing systems.

[ background of the invention ]

In semiconductor manufacturing, semiconductor wafers are subjected to numerous processes to meet high standards within the semiconductor industry. In the advanced process of semiconductor wafers, the edges of the wafers are required to be uniform, flat, damage free and smooth. The high requirement for uniform and precise etching of the wafer edge surface presents a significant challenge to semiconductor wafer processing.

Fig. 1a is a top view of a semiconductor wafer 100. Semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on substrate layer 101. FIG. 1b isbase:Sub>A cross-sectional view A-A of FIG. 1base:Sub>A. The measurement points 1-8 are locations where relevant data of the semiconductor wafer during operation is measured. As shown in fig. 1b, the etch width is the difference between the radii of the substrate layer 101 and the thin film layer 102. The etch width should be substantially the same at each measurement point 1-8. The smaller the difference between the maximum etch width and the minimum etch width, the higher the uniformity, for example, when the edge width is designed to be 0.7mm, many advanced process technologies require that the difference between the maximum etch width and the minimum etch width is not more than 0.1mm, otherwise the etch width is not uniform. If the difference between the maximum corrosion width and the minimum corrosion width exceeds 0.1mm, the effect of subsequent processing operation is directly influenced, and finally, the performance of an integrated circuit chip is poor, and the manufacturing yield of the chip is influenced.

The semiconductor wafer wet processing technology has the advantages of simple principle, flexible technology, low cost and the like. There are several conventional methods for wet etching the edge of the surface of a semiconductor wafer, for example, polishing the edge region of a semiconductor wafer, rotating the semiconductor wafer, and removing a thin film layer from the substrate layer by a combination of physical friction and chemical etching. Polishing methods are used primarily in semiconductor wafer fabrication where the precision requirements are low, since the remaining thin film layers and substrate layers are easily damaged. Edge damage can cause wafer edges to slip during thermal processing, eventually leading to wafer scrap. Another common method is to vacuum chuck the semiconductor wafer. The vacuum adsorption method uses a vacuum suction head to suck the wafer, the vacuum suction head has the functions of sucking the wafer, protecting the part of the thin film to be kept in the vacuum suction head, exposing the part of the thin film to be removed out of the vacuum suction head, and then soaking the vacuum suction head and the wafer in a chemical etching solution to etch off the part of the thin film exposed out of the vacuum suction head. However, the vacuum adsorption method causes unsmooth removal of thin layers and uneven etching width. Another common method is a film-sticking method, in which a plastic film such as pure anticorrosive PTFE or PE is used to protect the portion of the film to be retained, and then the whole is exposed to a chemically corrosive gas environment or immersed in a chemically corrosive liquid to corrode the exposed portion. The sticking method often causes the uneven etching width because the center of the pre-cut film may not be aligned with the substrate center of the wafer; and the process has multiple steps and needs to be finished by using various devices, wherein the devices comprise film sticking, wet etching, cleaning, film removing and the like. The working principle of the novel spraying method is that a special nozzle is adopted to accurately spray fluid for corrosion to a region needing to be corroded at the edge of a rotating wafer, so that accurate, uniform, flat and nondestructive corrosion is realized. Although the spraying method can achieve a higher corrosion effect, the spraying method has extremely high requirements on the design of equipment and the processing precision of parts, the equipment cost is very high, the requirements on process conditions are also severe, and the process cost is high.

In addition, most materials have a certain temperature expansion coefficient. Semiconductor wafer edge processing devices fabricated from materials with large temperature coefficients of expansion may have different widths of erosion at the wafer edge during fabrication and during use due to differences in fabrication and use temperatures, temperature variations during transport, or other unknown factors.

In addition, different processes and manufacturers often require different etching widths on the edge of the wafer, such as 0.5mm for some etching widths, 0.6mm for some etching widths, 0.3mm for some etching widths, etc. In order to meet the requirements of different processes and manufacturers, semiconductor wafer edge processing devices with different etching sizes need to be manufactured, and the manufacturing cost is high.

In view of the above, there is a need for a new type of semiconductor wafer edge processing apparatus that can solve the above problems.

[ Utility model ] content

An object of the utility model is to provide a brand-new semiconductor processing apparatus and semiconductor processing system, it can solve the problem that prior art exists, realizes right the adjustment of the corruption width at the edge of wafer.

To achieve the above object, according to an aspect of the present invention, the present invention provides a semiconductor processing apparatus, comprising: a lower chamber having a first support region supporting a wafer; an upper chamber having a second support region, wherein the wafer is received between the first support region and the second support region when the upper chamber and the lower chamber are closed; a temperature control assembly disposed proximate to the upper chamber and/or the lower chamber, which adjusts a temperature of the upper chamber and/or the lower chamber by adjusting a temperature thereof; a first channel formed in an edge region of the first support region or the second support region, the first channel providing a first space for circulation of one or more chemical fluids that erode the edge region of the wafer; and adjusting the temperature of the upper chamber and/or the lower chamber by using the temperature control assembly, so that the position of the edge of the first support area and/or the second support area is finely adjusted by using the thermal expansion and cold contraction characteristics of the upper chamber and/or the lower chamber, the width of the edge area of the wafer extending into the first space is adjusted, and the corrosion width of the edge of the wafer is finally adjusted.

According to another aspect of the present invention, the present invention provides a semiconductor processing system, including: the semiconductor processing apparatus described above; and a material storage device coupled to the semiconductor processing apparatus for storing and exchanging one or more chemical fluids with the semiconductor processing apparatus.

Embodiments of the present invention may be used in processing operations involving semiconductor wafers such that the edge surfaces are uniformly and accurately eroded. Meanwhile, the influence of temperature change on the accuracy of the corroded edge can be reduced.

Compared with the existing solutions, the embodiments of the present invention can provide various advantages.

The utility model discloses a set up temperature control component to can adjust the temperature of cavity and/or lower cavity as required, thereby adjust the size of cavity and/or lower cavity, and then can adjust the corruption width at the edge of wafer.

The features, aspects, and advantages of the present invention will become apparent from the following detailed description and the accompanying drawings. The present invention includes any combination of one or more features or elements, whether explicitly described or otherwise described in the embodiments. The present invention is intended to be read in its entirety such that any separable features or elements of the invention, in any aspect or embodiment thereof, are to be considered combinable unless the context of the invention otherwise clearly dictates.

It is therefore to be understood that this summary is provided merely for purposes of summarizing some embodiments so as to provide a basic understanding of some aspects of the invention. Therefore, the above-described embodiments are merely examples and should not be construed as narrowing the scope or idea of the present invention in any way. The features, aspects, and advantages of various embodiments will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of some embodiments.

[ description of the drawings ]

The present invention will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which:

FIG. 1a is a top view of a semiconductor wafer.

FIG. 1b isbase:Sub>A cross-sectional view A-A of FIG. 1base:Sub>A.

Fig. 2a is a schematic cross-sectional view of a semiconductor processing apparatus 200 according to an embodiment of the present invention.

Fig. 2b is an enlarged schematic view of circle a in fig. 2 a.

Fig. 2c is an enlarged schematic view of circle B in fig. 2B.

Fig. 2d is an enlarged schematic view of circle C in fig. 2C.

Fig. 2e is a bottom view of the upper chamber 220 of the semiconductor processing apparatus 200 of fig. 2 a.

Fig. 2f is a top view of the lower chamber 210 of the semiconductor processing apparatus 200 of fig. 2 a.

Fig. 3a is a schematic cross-sectional view of a semiconductor processing apparatus 300 according to an embodiment of the present invention.

Fig. 3b is an enlarged schematic view of circle D in fig. 3 a.

Fig. 3c is an enlarged schematic view of the circle D with the protrusion 342 shown in fig. 3 a.

Fig. 3d is a bottom view of the upper chamber 320 of the semiconductor processing apparatus 300 of fig. 3 a.

Fig. 3e is a top view of the lower chamber 320 of the semiconductor processing apparatus 300 of fig. 3 a.

Fig. 4a is a schematic cross-sectional view of a semiconductor processing apparatus 400 according to an embodiment of the present invention.

Fig. 4b is an enlarged schematic view of circle E in fig. 4a.

Fig. 4c is an enlarged schematic view of circle F in fig. 4 b.

Fig. 4d is a top view of the lower chamber 420 of the semiconductor processing apparatus 400 of fig. 4a.

Fig. 4e is a bottom view of the upper chamber 410 of the semiconductor processing apparatus 400 of fig. 4a.

Fig. 5 illustrates an exemplary system 500 comprising a semiconductor processing device and a material storage device in accordance with the present invention.

Fig. 6 is an exemplary method of using an apparatus to process an edge region of a semiconductor wafer in an embodiment of the invention.

Fig. 7 is a schematic diagram of a semiconductor processing apparatus with a wafer edge erosion width capable of being fine-tuned according to an embodiment of the present invention.

[ EXAMPLES ]

Some embodiments of the invention will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments are shown. Indeed, various embodiments of the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. For example, unless otherwise specified, the words first, second, etc. should not be construed as implying a particular order. Moreover, something may be described as being higher than something (unless otherwise stated) but actually lower than something, and vice versa; likewise, something described as being on the left side may be on the right side and vice versa. Like reference numerals refer to like elements throughout.

Fig. 1a to 1b are schematic structural views of a semiconductor wafer 100. Fig. 1a is a top view of a semiconductor wafer 100. FIG. 1b isbase:Sub>A cross-sectional view of section A-A of FIG. 1base:Sub>A. As shown in fig. 1a-1b, the semiconductor wafer 100 includes a substrate layer 101 and a thin film layer 102 deposited on an upper surface of the substrate layer 101, and the substrate layer 101 may be partially covered by the thin film layer 102. In another embodiment, the substrate layer 101 may be completely covered by the thin film layer 102. In another embodiment, both sides of the surface of the substrate layer 101 may be covered by the thin film layer 102, respectively.

In this embodiment, the thin film layer 102 should be removed from the substrate layer 101 by processing the semiconductor wafer. As shown in fig. 1a-1b, the radius of the thin film layer 102 is smaller than the substrate layer 101 and the etch width refers to the difference between the two radii. The measurement points 1-8 in FIG. 1a are test locations where data relating to the semiconductor wafer is measured. The etch width should be substantially the same at measurement points 1-8, with the smaller the difference between the maximum and minimum, the better the etch uniformity. For example, when the edge width is designed to be 0.7mm, the advanced process requires that the difference between the maximum etch width and the minimum etch width should not be greater than 0.1mm. In some embodiments, the thin layers covering both sides of the surface of the substrate layer 101 should be partially or completely removed. The etch width on each side of the surface of substrate layer 101 may be the same or different.

Referring to fig. 2a to 2f, this embodiment shows a schematic structural diagram of a semiconductor processing apparatus 200. Fig. 2a is a schematic cross-sectional view of a semiconductor processing apparatus 200. Fig. 2b is an enlarged schematic view of circle a in fig. 2 a. Fig. 2c is an enlarged schematic view of circle B in fig. 2B (through hole omitted). Fig. 2d is an enlarged schematic view of circle C in fig. 2C. Fig. 2e is a bottom view of the upper chamber 220 of the semiconductor processing apparatus 200 of fig. 2 a. Fig. 2f is a top view of the lower chamber 210 of the semiconductor processing apparatus 200 of fig. 2 a.

In an embodiment, as illustrated in fig. 1 and 2, the semiconductor device 200 includes a lower chamber 210 having a first support region 212. The first support region 212 may support the wafer 100. As shown in fig. 2a, the first support region 212 has an upper surface facing the wafer 100. The wafer 100 may be placed on the upper surface of the first support region 212. In some embodiments, the device 200 includes an upper chamber 220 having a second support region 222. As shown in fig. 2a, the second support region 222 has a lower surface facing the wafer 100. The upper chamber 220 is closed to the lower chamber 210 and the wafer 100 is placed between the first support region 212 and the second support region 222. With the lower chamber as the origin, the upper chamber 220 can be moved between two relative positions. While in the first position, the wafer 100 may be loaded and/or unloaded to the first support zone 212. In the second position, as shown in fig. 2a, the upper chamber 220 and the lower chamber 210 are closed such that the wafer 100 is held by the upper surface of the first support region 212 and the lower surface of the second support region 222 and processed.

In some embodiments, or any combination of the preceding embodiments, with reference to fig. 2a to 2c, the device 200 comprises a first channel 230 constituted by an edge region of the first support region 212 or the second support region 222. The first channel 230 provides a first space 232 for one or more chemical fluids to erode the edge region of the wafer 100. Referring to fig. 2a to 2c, the first channel 230 is constituted by an edge region of the second support region 222 in the upper chamber 220. The first passage 230 is formed on the lower surface of the upper chamber 220, and one side of the first passage 230 is opened to face the wafer 100. In this embodiment, the first channel 230 provides a first space 232 for one or more chemical fluids to flow therein to erode the edge region of the wafer 100. Referring to fig. 2a to 2c, a first space 232 may be formed by the first channel 230 and the inner surface of the wafer 100. In this embodiment, the first channel 230 is annular and surrounds an edge region of the wafer 100. The entire edge area of the wafer 100 is received in the first space 232. In another embodiment, the first passage 230 may be designed in an arc of less than 360 degrees, and an edge region of the wafer 100 may be accommodated in a specific region of the first space 232. The one or more chemical fluids may then erode the wafer edge region along the arc of the first channel 230.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, referring to fig. 2a to 2c, the upper chamber 220 comprises a raised portion 240 that abuts against an edge of the wafer 100. The raised portion may directly contact and abut the edge of the wafer 100. Referring to fig. 2a, the central axis X-X of the wafer 100 is perpendicular to the upper surface of the wafer 100. The central axis X '-X' of the second support region 222 is perpendicular to the lower surface of the second support region 222. The raised portion 240 will align the central axis X-X of the wafer 100 with the central axis X '-X' of the second support region 222. When the upper chamber 220 is in the first position, the wafer 100 is loaded onto the first support region 212. The central axis X-X of the wafer 100 may not be aligned with the central axis X '-X' of the second support region 222. During movement of the upper chamber 220 from the first position to the second position, the raised portion 240 contacts the edge of the wafer 100 and then pushes the wafer 100 against the edge of the wafer 100 to move over the upper surface of the first support region 212. When the upper chamber 220 is in the second position, the wafer is held on the upper surface of the first support region 212 and the central axis X-X of the wafer 100 is parallel to the central axis X '-X' of the second support region 222. Or the central axis X-X of the wafer 100 may overlap the central axis X '-X' of the second support region 222.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the raised portion 240 is adjacent to the second support region 222 and extends toward the lower chamber 210. Referring to fig. 2a and 2b, the convex portion 240 is connected with the second support region 222. When the upper chamber 220 is in the second position, the raised portion 240 extends to the lower chamber 210. As shown in fig. 2a and 2b, in this embodiment, the raised portion 240 is located next to the first channel 230. Referring to fig. 2a, a central axis X-X of the wafer 100 is perpendicular to an upper surface of the wafer 100 and a central axis X '-X' of the second support region 222 is perpendicular to a lower surface of the upper chamber 220. The upper surface 100 of the wafer is parallel to the lower surface of the second support region 222. In one embodiment, when the upper chamber 220 is in the second position, a portion of the upper surface of the wafer 100 overlaps the lower surface of the second support region 222, and the central axis X-X of the wafer 100 overlaps the central axis X '-X' of the second support region 222.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the raised portion 240 may be designed as a closed loop around the wafer 100. Referring to fig. 2a, the convex portion 240 comprises a closed loop. The closed loop may surround the entire edge area of the wafer 100. Thus, the raised portion 240 may fully abut against the edge region of the wafer 100, such that the central axis X-X of the wafer 100 overlaps with the central axis X '-X' of the second support region 222. In some embodiments, the closed loop may be a circular arc having an arc less than 360 degrees and a particular portion abutting an edge region of the wafer 100 such that the central axis X-X of the wafer 100 is aligned and/or overlaps with the central axis X '-X' of the second support region 222 by the raised portion 240. In some embodiments, the raised portion 240 may be an open loop.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the raised portion 240 comprises an inner angle facing the central axis X '-X' of the second support region 222. Referring to fig. 2c, the raised portion 240 includes an inner surface 242 inclined at an angle α to the first reference direction Y-Y. The first reference direction Y-Y is parallel to the lower surface of the second support region 222. The angle alpha is in the range of 20 deg. -90 deg.. As shown in fig. 2b and 2c, the interior angle is formed by the junction of the interior surface 242 and the interior surface of the first channel 230 and faces the central axis X '-X' of the second support region 222. In some embodiments, the interior corners abut the edge region of the wafer 100. As shown in fig. 2b, during the movement of the upper chamber 220 from the first position to the second position, the inner corners of the convex portions 240 contact the edge region of the wafer 100 and then push the wafer 100 against the edge of the wafer 100. When the upper chamber 220 is in the second position, the wafer is fixed and the central axis X-X of the wafer 100 is parallel to the central axis X '-X' of the second support region 222. Alternatively, the central axis X-X of the wafer 100 overlaps the central axis X '-X' of the second support region 222.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the first channel 250 is comprised by the edge region 214 of the lower chamber 210, and the first channel 250 provides a first channel space 252 for the communication of one or more chemical fluids. Referring to fig. 2a, 2b and 2f, the first channel 250 is formed by the edge region 214 of the lower chamber 210 and is adjacent to the first support region 212 of the lower chamber 210. The first channel 250 forms a first channel space 252 to which one or more chemical fluids may flow from the first space 232 of the first passage 230 to the first channel space 252.

In some embodiments of the apparatus 200, or any combination of the preceding embodiments, the aisle 260 is located between the upper chamber 220 and the lower chamber 210. Referring to fig. 2b and 2f, the lower chamber 210 has a first upper surface 262 between the first support region 212 and the first channel 250. The passageway 260 is located between a first upper surface 262 of the lower chamber 210 and the inner surface 242 of the raised portion 240. A passageway 260 connects the first space 232 with the first channel space 252 such that the one or more chemical fluids flow from the first space 232 to the first channel space 252 through the passageway 260. In one embodiment, the passageway 260 may be blocked by the raised portion 240 to prevent the one or more chemical fluids from flowing from the first space 232 to the first channel space 252. In another embodiment, the passageway 260 is blocked by the first support region 210, preventing the one or more chemical fluids from flowing from the first space 232 to the first channel space 252.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, as shown in fig. 2a to 2c, the first channel 230 is located at an edge region of the second support region 222. The upper chamber 220 includes a first through-hole 270, and one or more chemical fluids flow between the first space 232 and the outside of the device 200 through the first through-hole 270. The first through-hole 270 may communicate the first space 232 from the outside of the device 200 through the upper chamber 220. In one embodiment, one or more chemical fluids may flow between the first space 232 and the exterior of the device 200 through the first through-hole 270. In another embodiment, the upper chamber 220 may include two or more through holes substantially identical to the first through hole 270 (shown in fig. 2a and 2e as a second through hole 272). In this embodiment, at least one first through-hole (e.g., first through-hole 270) may be used as an inlet and the remaining first through-holes (e.g., second first through-hole 272) may be used as outlets. The first space 232 may be connected to the outside through the first through hole 270 and the second through hole 272. In this embodiment, one or more chemical fluids may flow from the exterior of the device 200 into the first space 232 of the first channel 230 via the first through-hole 270 and out of the first space 232 to the exterior of the device 200 via the second through-hole 272.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the second channel 280 is comprised by an edge region of the first support region 212 and provides a second space 282 for etching the edge region of the wafer 100 using one or more chemical fluids. Referring to fig. 2a to 2c, the second channel 280 is formed by an edge region of the first support region 212 in the lower chamber 210. Referring to fig. 2a to 2c, the second channel 280 is located on the upper surface of the lower chamber 210, and one side of the second channel 280 is open to face the wafer. In this embodiment, the second channel 280 provides the first space 232 for one or more chemical fluids to erode the edge region of the wafer 100. Referring to fig. 2a to 2c, the second space may be formed by the inner surface of the second channel 280 and the wafer 100. In one embodiment, the second channel 280 is annular and surrounds an edge region of the wafer 100. In another embodiment, the second channel 280 may be designed to have an arc of less than 360 degrees and the edge area of the wafer 100 is exposed to a specific position in the second space 282. One or more chemical fluids are then used to etch a particular edge region of the wafer along the arc of the second channel 280. In some embodiments, the second channel 280 is designed to be the same shape as the first channel 230. The second channel 280 is located between the first support region 212 and the first channel 250 proximate the first upper surface 262. The passageway 260 is located between a first upper surface 262 of the lower chamber 210 and the inner surface 242 of the upper chamber. The passageway 260 is for one or more chemical fluids to flow from the second space 282 to the first channel space 252 through the passageway 260. In one embodiment, the passageway 260 can be blocked by the raised portion 240 to prevent the one or more chemical fluids from flowing from the second space 282 into the first channel space 252. In another embodiment, the passage 260 may be blocked by the first support region 210 to prevent one or more chemical fluids from flowing from the second space 282 to the first channel space 252.

In some embodiments of the apparatus 200 or any combination of the preceding embodiments, the lower chamber 210 presents a second through-hole 290 for one or more chemical fluids to flow between the second space 282 and the exterior of the device 200. Referring to fig. 2a and 2b, the second through hole 290 may communicate with the second space 282 of the second channel 280 from the outside of the device 200 through the lower chamber 210. In one embodiment, one or more chemical fluids may flow between the second space 282 and the exterior of the device 200 via the second through-hole 290. In another embodiment, one or more chemical fluids may flow from the exterior of the apparatus 200 to the second space 282 of the second channel 280 via the second via 290, and then from the second space 282 of the second channel 280 to the first channel space 252 of the first channel 250 via the passageway 260. In some embodiments, the lower chamber 210 may further include one or more second through-holes (e.g., secondary second through-holes 292 shown in fig. 2 a) substantially identical to the second through-holes 290. In one embodiment, at least one second via (e.g., second via 290) is used as an inlet and the remaining second vias (e.g., second through holes 292) are used as outlets. The second space 282 is connected to the outside of the device 200 through the second through hole 290 and the second through hole 292. In one embodiment, one or more chemical fluids may flow from the exterior of the apparatus 200 into the second space 282 of the second channel 280 via the second through-hole 290 and out of the apparatus 200 from the second space 282 via the second through-hole 292. In another embodiment, one or more chemical fluids may flow from the exterior of the apparatus 200 into the second space 282 of the second channel 280 via the second through-hole 290 and the second through-hole 292, and then from the second space 282 of the second channel 280 into the first channel space 252 of the first channel 250 via the passageway 260.

Referring to fig. 3a to fig. 3e, schematic structural diagrams of a semiconductor processing apparatus 300 according to an embodiment of the present invention are shown. Fig. 3a is a schematic cross-sectional view of a semiconductor processing apparatus 300 according to an embodiment of the present invention. Fig. 3b is an enlarged schematic view of circle D in fig. 3 a. Fig. 3c is an enlarged schematic view of the circle D with the raised portion 342 shown in fig. 3 a. Fig. 3d is a bottom view of the upper chamber 320 of the semiconductor processing apparatus 300 of fig. 3 a. Fig. 3e is a top view of the lower chamber 320 of the semiconductor processing apparatus 300 of fig. 3 a.

In this embodiment, referring to fig. 3a-3e, the apparatus 300 includes a lower chamber 310 having a first support region 312. The lower chamber 310 and the first support region 312 may refer to the lower chamber 210 and the first support region 212 shown in fig. 2a to 2f, respectively. The device 300 includes an upper chamber 320 having a second support region 322. The upper chamber 320 and the second support region 322 may be referenced to the upper chamber 220 and the second support region 222, respectively, shown in fig. 2a-2f above. As described above, the upper chamber 320 and the lower chamber 310 are closed to secure the wafer 100 between the first support region 312 and the second support region 322. The apparatus 300 includes a first channel 330 formed by an edge region of the first support region 312 or the second support region 322. The first channel 330 may refer to the first channel 230 described above in fig. 2a-2 f. The first channel 330 is formed by an edge region of the second support region 322 in the upper chamber 320 and provides a first space 332 for one or more chemical fluids to flow through to erode the edge region of the wafer 100. The first space 332 may refer to the first space 232 described above with reference to fig. 2a to 2 f. In some embodiments, the first space 332 of the first channel 330 may also be formed by the inner surface of the first channel 330, the lower chamber 310, and the wafer 100. The entire or partial edge region of the wafer 100 exposed in the first space 332 of the first channel 330 is contacted and corroded by one or more chemical fluids

In some embodiments of the apparatus 300 or any combination of the preceding embodiments, as shown in fig. 3a to 3d, the upper chamber 320 comprises a raised portion 340 for abutting against an edge of the wafer 100 and aligning the central axis X-X of the wafer 100 with the central axis X '-X' of the second support zone 322. The raised portion 340 may refer to the raised portion 240 described above with reference to fig. 2a to 2 e. In some embodiments, the raised portion 340 includes a plurality of tabs 342 that uniformly surround and abut the edge region of the wafer 100. Each projection 342 extends from the raised portion 340 into the first space 332 of the first channel 330. Referring to fig. 3c and 3d, the convex portion 340 includes four protrusions (e.g., protrusions 342 a-342 d). Each lug 342 includes an inner surface 344 that is inclined at an angle beta to the reference direction Y-Y. The angle beta is in the range of 20 deg. -90 deg.. The inner surface faces the edge of the wafer 100. The reference direction Y-Y is parallel to the upper surface of the wafer 100 or perpendicular to the central axis X '-X' of the second support region 322. For example, in fig. 3c, the tab 342a includes an inner surface 344a that is inclined at an angle β relative to the reference direction Y-Y. The inner surface 344a may abut an edge of the wafer 100 and urge the wafer 100 to align the central axis X-X of the wafer 100 with the central axis X '-X' of the second support region 322. The raised portion 340 includes a plurality of tabs 342. In some embodiments, raised portion 340 may include six tabs 342. In some embodiments, raised portion 340 may include eight tabs 342. In some embodiments, raised portion 340 may include twelve tabs 342.

In some embodiments of the apparatus 300, or any combination of the preceding embodiments, referring to fig. 3a-3 c, a first channel 350 is formed at the edge region 314 of the lower chamber 310 and provides a first channel space 352 to flow one or more chemical fluids. The first channel 350, the edge region 314 of the lower chamber 310, and the first channel space 352 of the first channel 350 may be referred to the first channel 250, the edge region 214 of the lower chamber 220, and the first channel space 252 of the first channel 250, respectively, described above with reference to fig. 2a through 2 f. In some embodiments, an aisle 360 is formed between the upper chamber 320 and the lower chamber 310 connecting the first space 332 with the first channel space 352, and one or more chemical fluids flow from the first space 332 to the first channel space 352 through the aisle 360. The aisle 360 may refer to the aisle 260 described above with reference to fig. 2a-2 f. In some embodiments, the passageway 360 is formed between the raised portion 340 and the first upper surface 362 of the lower chamber 310. As shown in fig. 3a to 3c and 3e, first upper surface 362 is adjacent first support region 312 and is located between first support region 312 and first channel 350.

In some embodiments of the apparatus 300 or any combination of the preceding embodiments, as shown in fig. 3a, 3b, and 3d, the upper chamber 320 can include a first through-hole 370 to allow one or more chemical fluids to flow between the first space 332 and the exterior of the device 300. The first via 370 may refer to the first via 270 described above with reference to fig. 2a-2 e. In some embodiments, the upper chamber 320 may further include one or more first through-holes (e.g., the second first through-hole 372 shown in fig. 3a and 3 d) substantially identical to the first through-hole 370. The arrangement of the one or more first through holes may refer to the arrangement of the one or more first through holes described above with reference to fig. 2a and 2 e.

In some embodiments of the apparatus 300, or any combination of the preceding embodiments, referring to fig. 3a, 3b, and 3e, the lower chamber 310 includes a second through-hole 380. As shown in fig. 3a and 3b, the second through-hole 380 is used for one or more chemical fluids to flow between the first space 332 and the outside of the device 300. The second through hole 380 communicates with the first space 332 of the first channel 330 from the outside of the device 300 through the lower chamber 310. In some embodiments, one or more chemical fluids may flow from outside of device 300 to first space 332 via second through-hole 380, and then from first space 332 to first channel space 352 of first channel 350 through passageway 360. In some embodiments, one or more chemical fluids may flow from the exterior of device 300 to first space 332 of first passage 330 through first through-hole 370, and then from first space 332 to first channel space 352 through passageway 360 and to the exterior of device 300 through second through-hole 380.

In some embodiments of the device 300, or any combination of the preceding embodiments, the second channel 390 is comprised of the edge region 324 of the upper chamber 320 and is located above the first channel 350. Referring to fig. 3a to 3d, the second channel 390 is formed by the edge region 324 of the upper chamber 320 and is adjacent to the convex portion 340. The second channel 390 provides a second channel space for circulation of chemicals. The opening of the second channel 390 faces the lower chamber 310. Second channel 390 is positioned above first channel 350 such that first channel space 352 of first channel 350 may communicate with a second channel space of second channel 390. Second channel 390 is of the same design as first channel 350. As shown in fig. 3d and 3e, the first and

second slots

350, 390 are annular. In addition, the first and

second slots

350 and 390 may be designed to have an arc shape of less than 360 degrees.

In some embodiments of the device 300, or any combination of the preceding embodiments, as shown in fig. 3a through 3c, a resilient member 392 may be placed between the first channel 350 and the second channel 390. In some embodiments, resilient member 392 is placed in first channel space 352 or second channel space. In some embodiments, a resilient member 392 is placed in first channel space 352 and second channel space. In some embodiments, resilient member 392 may be used to prevent one or more chemical fluids from flowing from first space 332 to first channel space 352. As shown in fig. 3a to 3c, for example, the width of the elastic member 392 is wider than the widths of the first and

second channels

350 and 390. The inner surface of first channel 350 and/or the inner surface of second channel 390 bear against resilient member 392, preventing the flow of one or more chemical fluids from first space 332 to first channel space 352.

In some embodiments of the apparatus 300, or any combination of the preceding embodiments, the resilient member 392 may be an O-ring.

Referring to fig. 4a to 4e, schematic structural diagrams of a semiconductor processing apparatus 400 according to an embodiment of the present invention are shown. Fig. 4b is an enlarged schematic view of circle E in fig. 4a. Fig. 4c is an enlarged schematic view of circle F in fig. 4 b. Fig. 4d is a top view of the lower chamber 420 of the semiconductor processing apparatus 400 of fig. 4a. Fig. 4e is a bottom view of the upper chamber 410 of the semiconductor processing apparatus 400 of fig. 4a.

In one embodiment, referring to fig. 4a-4e, the apparatus 400 includes a lower chamber 410 having a first support region 412. The lower chamber 410 and the first support region 412 may refer to the lower chamber 210 and the first support region 212 shown in fig. 2a to 2 f. The device 400 includes an upper chamber 420 having a second support region 422. The upper chamber 420 and the second support region 422 may be referred to the upper chamber 220 and the second support region 222, respectively, shown in fig. 2a-2f above. The device 400 includes a first channel 430 formed by an edge region of the first support region 412. The first channel 430 may refer to the first channel 230 described above in fig. 2a-2 f. Referring to fig. 4a to 4c and 4e, a first channel 430 is formed at an edge region of the first support region 412 in the lower chamber 420 and provides a first space 432 to flow one or more chemical fluids to etch the edge region of the wafer 100. The first space 432 of the first channel 430 may also be formed by the inner surface of the first channel 430 and the wafer 100. All or a portion of the edge region of the wafer 100 is received in the first space 432 of the first channel 430 and may contact and erode the edge region of the wafer 100 using one or more chemical fluids.

In some embodiments of the apparatus 400 or any combination of the preceding embodiments, as shown in fig. 4a-4 d, the upper chamber 420 includes a raised portion 440 that abuts an edge of the wafer 100 and aligns the central axis X-X of the wafer 100 with the central axis X '-X' of the second support region 422. The raised portion 440 may refer to the raised portion 240 described above with reference to fig. 2a-2 e. In some embodiments, raised portion 440 faces lower chamber 410 and is located near lower surface 424 of second support region 422. In some embodiments, the raised portion 440 includes a plurality of bumps evenly distributed around the wafer 100 against the edge region of the wafer 100. The bumps may refer to bumps 342 described above with reference to fig. 3a-3 d.

In some embodiments of the apparatus 400 or any combination of the preceding embodiments, the raised portion 440 includes an inner surface 442 that is inclined at an angle relative to the central axis X '-X' of the second support region 442, and the inner surface 442 abuts against an edge region of the wafer 100. Referring to fig. 4a to 4d, the inner surface 442 faces the wafer 100 and is in contact with an edge of the wafer 100. The inner surface 442 is inclined at an angle gamma with respect to the reference axis Z-Z. The angle gamma may range from 20 deg. -90 deg.. The reference axis Z-Z is parallel to the central axis X '-X' of the second support region 442. In some embodiments, the inner surface 442 of the raised portion 440 contacts and is configured to abut an edge of the wafer 100, thereby aligning the central axis X-X of the wafer 100 with the central axis X '-X' of the second support region 422. In some embodiments, the inner surface 442 of the raised portion 440 may push the wafer 100 such that the central axis X-X of the wafer 100 overlaps the central axis X '-X' of the second support region 422.

In some embodiments of the apparatus 400, or any combination of the preceding embodiments, referring to fig. 4a, 4c, and 4e, a first channel 450 is formed by the edge region 414 of the lower chamber 410 and provides a first channel space 452 that is available for the communication of one or more chemical fluids. The first channel 450, the edge region 414 of the lower chamber 410, and the first channel space 452 of the first channel 450 may be referred to the first channel 250, the edge region 214 of the lower chamber 220, and the first channel space 252 of the first channel 250, respectively, described above with reference to fig. 2a through 2 f. In some embodiments, a passageway 460 is located between the upper chamber 420 and the lower chamber 410, connecting the first space 432 with the first channel space 452 for the flow of one or more chemical fluids from the first space 432 to the first channel space 452 through the passageway 460. The aisle 460 may refer to the aisle 260 described above with reference to fig. 2a-2 f. In some embodiments, as shown in fig. 4c, a passageway 460 is located between the wafer 100 and a first upper surface 462 of the lower chamber 410. As shown in fig. 4c and 4e, first upper surface 462 is positioned between first passage 430 and first channel 450.

In some embodiments of the device 400, or any combination of the preceding embodiments, referring to fig. 4a-4 c and 4e, the lower chamber 420 comprises a first through-hole 470 such that one or more chemical fluids flow between the first space 432 and the exterior of the device 400. The first via 470 may refer to the first via 270 described above in fig. 2a-2 e. In some embodiments, the lower chamber 420 further includes one or more first vias (e.g., second first via 472 as shown in fig. 4a and 4 e) that are substantially identical to the first via 470. The arrangement of the one or more first through holes may be described with reference to fig. 2a and 2 e.

In some embodiments of the apparatus 400 or any combination of the preceding embodiments, referring to fig. 4a, 4b, and 4e, the second channel 480 is located at an edge region of the first support region 412 and provides a second space 482 for etching the edge region of the wafer 100 using one or more chemical fluids. The second channel 480 may refer to the second channel 280 described above in fig. 2b, 2c, and 2 f. In some embodiments, the first channel 430 and the second channel 480 may be connected by a passageway 484 such that one or more chemical fluids flow between the first space 432 of the first channel 430 and the second space 482 of the second channel 480. Referring to fig. 4b and 4c, a passageway 484 connecting the first channel 430 and the second channel 480 is formed by the wafer 100 and the first support region 412 of the lower chamber 410. One or more chemical fluids may flow between first space 432 and second space 482 through passageway 484. In some embodiments, one or more chemical fluids may flow from second space 482 through passageway 484, first space 432, and passageway 460 to first channel space 452.

In some embodiments of the device 400, or any combination of the preceding embodiments, referring to fig. 4a, 4b, and 4e, the lower chamber 410 includes a second through-hole 490, such that one or more chemical fluids flow between the second space 482 and the exterior of the device 400. The second via 490 may be the second via 290 described with reference to fig. 2a-2 c. In some embodiments, the lower chamber 410 further includes one or more second through-holes (e.g., the secondary second through-holes 492 shown in fig. 4a and 4 e) that are substantially identical to the second through-holes 490. The arrangement of the one or more first through holes may refer to the arrangement of the one or more first through holes described above with reference to fig. 2 a.

The utility model discloses can promote wafer edge corrosion's accuracy nature and homogeneity through using the bulge to can obtain the level and smooth surface of wafer substrate layer through the chemical fluid composition of scientific selective corrosion and the velocity of flow of control chemical fluid and the time of contact wafer edge, make things convenient for the follow-up technology operation of wafer. While the cost of the processing operation can be saved. It can selectively process the edge surface of the wafer, especially the precise control of the wafer edge erosion area.

In the above embodiments, the raised portion is disposed on the upper chamber, and in other embodiments, the raised portion may be disposed on the lower chamber. Of course, in some embodiments, other positioning structures may be provided to abut the outer end of the edge of the wafer and align the central axis of the wafer with the central axis of the second support region.

Fig. 5 illustrates an example system 500 of the present invention that includes a semiconductor processing apparatus 510 and a material storage apparatus 520. The device 510 may refer to any of the

devices

200, 300, and 400 described above in fig. 2a-2f, 3a-3e, and 4a-4 e. The apparatus 510 includes a lower chamber having a first support region for supporting a wafer and an upper chamber having a second support region; the upper chamber and the lower chamber are closed to fix the wafer between the first support area and the second support area; the first channel is located at an edge region of the first support region or the second support region, and the first channel provides a first space for etching the edge region of the wafer by one or more chemical fluids. In some embodiments, the upper chamber includes a raised portion that aligns a central axis of the wafer with a central axis of the second support region against an edge of the wafer. Material storage device 520 is connected to device 510 and is a device that stores one or more chemical fluids and allows one or more chemical fluids to be transferred between device 510 and material storage device 520. In some embodiments, the one or more chemical fluids may be selected from H3PO4, HF, HCl, HNO3, H2O2, or any combination thereof.

In some embodiments of the system 500 or any combination of the preceding embodiments, the raised portion is adjacent to the second support region and extends toward the lower chamber. The central axis of the wafer is vertical to the upper surface of the wafer, the central axis of the second supporting area is vertical to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second supporting area. In some embodiments, the raised portion comprises a closed loop around the wafer, and the raised portion rests uniformly against an edge region of the wafer such that a central axis of the wafer overlaps a central axis of the second support zone.

In some embodiments of the system 500 or any combination of the preceding embodiments, the raised portion is adjacent to the second support region and extends toward the lower chamber. The central axis of the wafer is vertical to the upper surface of the wafer, the central axis of the second supporting area is vertical to the lower surface of the upper cavity, and the upper surface of the wafer is parallel to the lower surface of the second supporting area. In some embodiments, the raised portion includes a plurality of bumps annularly distributed around the wafer for evenly abutting an edge region of the wafer.

In some embodiments of the system 500 or any combination of the preceding embodiments, a first channel is present at an edge region of the lower chamber and provides a first channel space for communication of one or more chemical fluids. In some embodiments, a passageway is formed between the upper chamber and the lower chamber connecting the first space with the first channel space such that one or more chemical fluids flow from the first space to the first channel space through the passageway. In some embodiments, a second channel is present in an edge region of the upper chamber and is located above the first channel. In some embodiments, a resilient member may be added between the first channel and the second channel for preventing one or more chemical fluids from flowing from the first space to the first channel space.

In some embodiments of the system 500, or any combination of the preceding embodiments, the system 500 includes a control device 530. Control means 530 may accomplish communication and control of device 510 and material storage device 520. For example, the control device 530 may control the movement of the upper chamber between a first position for loading/unloading the wafer and a second position for closing the upper and lower chambers to process the wafer; the flow velocity and direction of the one or more chemical fluids may be controlled. The control device 530 may detect the flow rate, flow direction, status of one or more chemical fluids and a malfunction of the device 510. In some embodiments, the control device may include a PLC, a controller, a sensor, a storage device (e.g., memory, hard drive, SSD, etc.).

Fig. 6 illustrates an exemplary method 600 for processing an edge region of a semiconductor wafer 100 using an apparatus according to an embodiment of the present invention. The method may employ any of the apparatus 200, apparatus 300, apparatus 400 or apparatus 500 described in figures 2a-2f, 3a-3e, 4a-4e and 5.

In an embodiment, the apparatus 200 (or apparatus 300, apparatus 400, or apparatus 500) receives a wafer and places it on a first support region of a lower chamber, as shown in step 602 of FIG. 6. In step 604, the apparatus closes its upper chamber from its lower chamber to secure the wafer between the first support region and the second support region of the upper chamber. In step 606, a first channel is formed at an edge region of the first support region or the second support region, and the first channel provides a first space. In step 608, the apparatus abuts the edge of the wafer using the raised portion and aligns the central axis of the wafer with the central axis of the second support region. In step 610, the apparatus injects one or more chemical fluids into the first space to etch the edge region of the wafer.

In some embodiments of the method 600 or any combination of the preceding embodiments, a wafer is placed 602 on a first support region of a lower chamber of the apparatus 200 (or apparatus 300, apparatus 400, or apparatus 500) by a wafer transfer device. The upper surface of the first support region faces the wafer. The wafer transfer apparatus may place the wafer on the upper surface of the first support region such that a portion of the lower surface of the wafer is covered by the upper surface of the first support region. In some embodiments, the wafer may be loaded or unloaded to the first support zone with the upper chamber of the apparatus 200 (or the apparatus 300, the apparatus 400, or the apparatus 500) in the first position. That is, the wafer may be transferred from the wafer transfer apparatus to the upper surface of the first support region.

In some embodiments of the method 600 or any combination of the preceding embodiments, the apparatus 200 (or apparatus 300, apparatus 400 or apparatus 500) may close the upper and lower chambers to secure the wafer between the first and second support regions of the upper chamber in step 604. When the upper chamber is in the second position, the lower chamber may be closed with the upper chamber and the wafer secured between the lower chamber and the upper chamber to process the wafer edge region. The upper chamber includes a second support region facing the lower surface of the wafer. The upper chamber and the lower chamber are closed to place the wafer between the first support region and the second support region. At this time, the wafer may be fixed between the lower surface of the second support region and the upper surface of the first support region.

In some embodiments of the method 600 or any combination of the preceding embodiments, at step 606, an edge region of the first support region or the second support region forms a first channel. The first channel may also be formed on a lower surface of the upper chamber, and an opening of the first channel faces the wafer. In some embodiments, the first channel provides a first space for processing an edge region of the wafer. For example, one or more chemical fluids flow in the first channel and erode an edge region of the wafer. In some embodiments, the first channel may be designed as a closed loop. In some embodiments, the first channel may be circular in design. The apparatus 200 (or the apparatus 300, the apparatus 400, or the apparatus 500) or the wafer transfer device places the entire or a part of the edge area of the wafer in the first space for processing. In some embodiments, the first channel may be designed as a circular arc with an arc of less than 360 degrees. The apparatus 200 (or the apparatus 300, the apparatus 400 or the apparatus 500) or the wafer transfer device places a portion of the edge region of the wafer in the first space for processing.

In some embodiments of the method 600 or any combination of the preceding embodiments, the device 200 (or the

device

300, 400, or 500) has a raised portion on the upper chamber or the lower chamber in step 608. The apparatus may use the raised portion against the edge of the wafer. The raised portion contacts an edge of the wafer during movement of the upper chamber from the first position to the second position. The raised portion then abuts the edge of the wafer and urges the wafer to move over the upper surface of the first support region of the lower chamber. When the upper chamber and the lower chamber are closed, the wafer is fixed on the upper surface of the first support area, and the central axis X-X of the wafer is parallel to the central axis X '-X' of the second support area. The distance between the central axis X-X of the wafer and the central axis X '-X' of the second support zone may be in the range of 0mm-0.1 mm. In some embodiments, the raised portion may be adjacent the second support region and extend toward the lower chamber. In one embodiment, the raised portion is proximate the first channel.

In some embodiments, the raised portion comprises an interior angle facing the central axis X '-X' of the second support region. The interior angle is formed by the intersection of the inner surface of the convex portion and the inner surface of the first channel and faces toward the central axis X '-X' of the second support region. In one embodiment, the inner corner abuts the edge region of the wafer. When the upper chamber moves from the first position to the second position, the inner corners of the raised portions contact the edge of the wafer and then abut the edge of the wafer and push the wafer. In other embodiments, the inner surface of the raised portion contacts the edge of the wafer and then pushes the wafer against the edge of the wafer.

In some embodiments of the method 600 or any combination of the preceding embodiments, at step 610, the apparatus 200 (or the apparatus 300, the apparatus 400, or the apparatus 500) may inject one or more chemical fluids into the first space for etching the edge region of the wafer. One or more chemical fluids flow in the first space around the edge of the wafer and erode the edge region of the wafer exposed in the first space. In some embodiments, the device includes a through hole connecting the first space with an exterior of the device. One or more chemical fluids may flow into the first space through the through-hole. In some embodiments, one or more chemical fluids may flow from the first space to the exterior of the device through the through-hole. In other embodiments, the device comprises two through holes, each connecting the first space with the exterior of the device, respectively. The two through holes are at a distance. One or more chemical fluids flow into the first space through one of the through-holes and out of the device from the first space through another of the through-holes.

As mentioned in the background, most materials have a certain temperature expansion coefficient. Semiconductor wafer edge processing devices fabricated from materials having temperature coefficients of expansion may have different erosion widths at the wafer edge during fabrication and during use due to differences in fabrication and use temperatures, variations in temperature differences during transport, or variations in other factors that are not understood. In addition, different processes and manufacturers often require different etching widths on the edge of the wafer, such as 0.5mm for some etching widths, 0.6mm for some etching widths, 0.3mm for some etching widths, etc. To meet the requirements of different processes and manufacturers, it is necessary to manufacture different semiconductor wafer edge processing devices at high cost.

In order to solve these problems, the present invention provides a semiconductor processing apparatus in which the etching width of the edge of the wafer can be finely adjusted. Fig. 7 is a schematic structural diagram of a semiconductor processing apparatus according to an embodiment of the present invention, in which the etching width of the edge of the wafer can be adjusted finely.

The semiconductor processing apparatus of fig. 7 is largely identical in structure to the semiconductor processing apparatus of fig. 3a, except that the semiconductor processing apparatus of fig. 7 further includes: a temperature control assembly 810 disposed proximate the upper chamber and a temperature control assembly 810 disposed proximate the lower chamber. The two temperature control components can be identical in structure or different in structure. The temperature control assembly 810 may adjust the temperature of the upper chamber 320 and the temperature of the lower chamber 310 by adjusting the temperature thereof. The temperature control assembly 810 is used to adjust the temperature of the upper chamber 320 and the lower chamber 310, so as to adjust the position of the edge of the first support area and/or the second support area by using the thermal expansion and contraction of the upper chamber 320 and the lower chamber 310, and further adjust the width of the edge region of the wafer 100 extending into the first space 332, and finally, the etching width of the edge of the wafer 100 is adjusted. Specifically, if the edge of the first support region and/or the second support region is expanded outward due to the expansion of the upper chamber 320 and the lower chamber 310, the width of the edge region of the wafer 100 extending into the first space 332 is reduced, thereby reducing the erosion width of the edge of the wafer 100; if the edge of the first support region and/or the second support region is shrunk inward due to the shrinkage of the upper chamber 320 and the lower chamber 310, the width of the edge region of the wafer 100 extending into the first space 332 is increased, thereby increasing the etching width of the edge of the wafer 100. It should be noted that the expansion and contraction are relative here. Similarly, the temperature control assembly 810 can be added to the semiconductor processing apparatus shown in fig. 2a and 4a.

Due to the arrangement of the temperature control assembly 810, the temperature of the upper chamber and the temperature of the lower chamber can be adjusted as required. By adjusting the temperature of the temperature control assembly 810, the small changes in the dimensions of the upper chamber and the lower chamber caused by environmental temperature changes or other factors can be reduced, and the etching width of the edge of the wafer can be actively adjusted. Thus, the same semiconductor processing apparatus can satisfy the applications of a plurality of different etching widths of the edge of the wafer without manufacturing a plurality of semiconductor processing apparatuses for such applications. Meanwhile, even if the etching width of the edge of the wafer obtained by one semiconductor processing device does not meet the requirement, the etching width of the edge of the wafer obtained by the temperature control component 810 can meet the requirement through the temperature adjustment.

In one embodiment, the temperature control assembly 810 includes a temperature adjusting member 811 and a diffusion member 812, the diffusion member 812 is disposed between the temperature adjusting member 811 and the upper chamber 320, and the temperature adjusting member 811 includes a plurality of electric heating units. By controlling the electric heating unit to control the temperature of the temperature adjusting part 811, the diffusion part 812 transfers heat to the upper chamber 320, thereby adjusting the temperatures of the upper chamber 320 and the lower chamber. Specifically, the electric heating unit may be an electric heating resistance wire.

The temperature control assembly 810 may be separately designed from the upper chamber 320 and the lower chamber 310, assembled together by a connection assembly, or integrally provided. In other embodiments, the temperature control assembly 810 may be disposed only on the lower side of the lower chamber 310 or only on the upper side of the upper chamber 320, as desired.

Through setting up temperature control component 810, can greatly reduced requirements such as processing, transportation and installation of semiconductor processing apparatus, simultaneously can also to the adjustment of the corruption width at the edge of wafer, promoted semiconductor processing apparatus's application.

Certain embodiments may be viewed as a computer program product comprising instructions stored on a non-transitory machine-readable medium. These instructions may be used to program a general-purpose or special-purpose processor to perform the operations described. A machine-readable medium includes any mechanism for storing or transmitting information in a form (e.g., software, processing application) readable by a machine (e.g., a computer). The machine-readable medium may include, but is not limited to, magnetic storage medium (e.g., floppy diskettes), optical storage medium (e.g., CD-ROMs), magneto-optical storage medium, read-only memory (ROMs), random Access Memory (RAMs), erasable programmable memory (e.g., EPROMs and EEPROMs), flash memory, or other type of media suitable for storing electronic instructions. The machine-readable medium may be referred to as a non-transitory machine-readable medium.

The above description is intended to be illustrative, and not restrictive. While the invention has been described with reference to the specific illustrative examples, it should be understood that the invention is not limited to the described embodiments. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Reference herein to "one example (embodiment)" or "an example (embodiment)" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The utility model provides a "a plurality of", "a plurality of" indicate two or more. In the present invention, "and/or" means "and" or ". Furthermore, the terms "first," "second," "third," "fourth," and the like as used herein are intended as labels to distinguish between different elements, and may not necessarily have a sequential meaning in accordance with their numerical designation. Thus, the terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting.

It should also be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.

Although the method operations are described in a particular order, it should be understood that other operations may be performed between the described operations. The described processes may be adjusted so that they occur at slightly different times, or the described operations may be distributed throughout the system. The system allows multiple unrelated programs to be processed simultaneously.

Many modifications and other implementations of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Moreover, although the foregoing description and the associated drawings describe implementations involving particular combinations of elements, functions, and embodiments, the various combinations of elements, functions and implementations may be practiced by others, within the scope of the appended claims. The appended claims are intended to cover other elements, combinations of functions, and equivalents of the elements, functions, and equivalents of the claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A semiconductor processing apparatus, characterized in that: it includes:

a lower chamber having a first support region supporting a wafer;

an upper chamber having a second support region, wherein when the upper chamber and the lower chamber are closed, the wafer is disposed between the first support region and the second support region;

a temperature control assembly disposed proximate to the upper chamber and/or the lower chamber, which adjusts a temperature of the upper chamber and/or the lower chamber by adjusting a temperature thereof;

a first channel formed in an edge region of the first support region or the second support region, the first channel providing a first space for circulation of one or more chemical fluids that erode the edge region of the wafer;

and adjusting the temperature of the upper chamber and/or the lower chamber by using the temperature control assembly, so as to finely adjust the position of the edge of the first support area and/or the second support area by using the thermal expansion and cold contraction of the upper chamber and/or the lower chamber, further adjust the width of the edge area of the wafer extending into the first space, and finally adjust the corrosion width of the edge of the wafer.

2. A semiconductor processing apparatus according to claim 1, wherein the upper and/or lower chamber comprises locating formations for abutting outer ends of the edge of the wafer and aligning the central axis of the wafer with the central axis of the second support zone.

3. The semiconductor processing apparatus of claim 2, wherein the positioning structure is disposed on the upper chamber, and the positioning structure is a raised portion for abutting against an outer end of the edge of the wafer and aligning a central axis of the wafer with a central axis of the second support region.

4. The semiconductor processing apparatus of claim 3, wherein the raised portion of the upper chamber is adjacent to the second support region and extends toward the lower chamber, a central axis of the wafer is perpendicular to an upper surface of the wafer, the central axis of the second support region is perpendicular to a lower surface of the upper chamber, the upper surface of the wafer is parallel to the lower surface of the second support region,

the convex portion includes a curved portion designed in a loop shape around the outer end of the wafer, and the convex portion uniformly abuts against the outer end area of the edge of the wafer so that the central axis of the wafer overlaps with the central axis of the second support area.

5. The semiconductor processing apparatus of claim 4, wherein the raised portion comprises a plurality of bumps evenly distributed around the outer end of the wafer in a ring shape for evenly abutting against the outer end region of the wafer edge.

6. A semiconductor processing apparatus according to claim 3, wherein the raised portion comprises an inner surface inclined at an angle to a central axis of the second support zone, the inner surface abutting an outer end region of an edge of the wafer,

the raised portion includes an inner angle facing a central axis of the second support region, the inner angle abutting an outer end region of an edge of the wafer.

7. The semiconductor processing apparatus of claim 1, wherein the first channel is located at an edge region of the lower chamber and provides a first channel space for flowing the one or more chemical fluids, while a passageway is formed between the upper chamber and the lower chamber that connects the first space and the first channel space such that the one or more chemical fluids flow from the first space into the first channel space through the passageway.

8. The semiconductor processing apparatus of claim 7, wherein the second channel is formed in an edge region of the upper chamber above the first channel,

an elastic component is arranged between the first channel and the second channel and is used for blocking one or more chemical fluids from flowing from the first space to the first channel space,

the edge region of the second support zone forms a first channel and one or more chemical fluids are communicated between the first space and the exterior of the device through a first through hole located in the upper chamber,

wherein the edge region of the first support region forms a second channel providing a second space for flowing one or more chemical fluids for etching the edge region of the wafer,

the lower chamber provides a second through-hole for enabling communication of one or more chemical fluids between the second space of the lower chamber and the exterior of the device,

the edge region of the first support zone constitutes a first channel, the lower chamber comprises a first through hole, and one or more chemical fluids are circulated between the first space and the outside of the device through the first through hole located in the lower chamber.

9. The semiconductor processing apparatus of claim 1,

the temperature control assembly comprises a temperature adjusting component and a diffusion component, the diffusion component is arranged between the temperature adjusting component and the upper chamber and/or the lower chamber, and the temperature adjusting component comprises a plurality of electric heating units.

10. A semiconductor processing system, comprising:

a semiconductor processing apparatus as claimed in any one of claims 1 to 9;

a material storage device coupled to the semiconductor processing apparatus for storing and exchanging one or more chemical fluids with the semiconductor processing apparatus.

11. The semiconductor processing system of claim 10, wherein:

the first channel is located in an edge region of the lower chamber and provides a first channel space through which the one or more chemical fluids can pass, while a passageway is formed between the upper chamber and the lower chamber, the passageway connecting the first space and the first channel space such that the one or more chemical fluids can flow from the first space into the first channel space through the passageway, the second channel being formed in an edge region of the upper chamber and located above the first channel, an elastic member being arranged between the first channel and the second channel and serving to block the flow of the one or more chemical fluids from the first space into the first channel space.