CN217607879U

CN217607879U - Selection module, pixel row selection module and pixel reading circuit

Info

Publication number: CN217607879U
Application number: CN202221099514.3U
Authority: CN
Inventors: 王锋奇; 陈鹏
Original assignee: SmartSens Technology Shanghai Co Ltd
Current assignee: SmartSens Technology Shanghai Co Ltd
Priority date: 2022-04-27
Filing date: 2022-04-27
Publication date: 2022-10-18
Anticipated expiration: 2032-04-27

Abstract

The utility model provides a select module, pixel row and select module and pixel readout circuit, include: the pixel array comprises a group of multi-row selected row selection units, wherein each multi-row selected row selection unit comprises a plurality of AND gates, the input end of each AND gate is connected with a corresponding address signal, and the output end of each AND gate outputs each row selection signal in the pixel array; the < n: m +1> bit address of each AND gate in the multi-row selected row selection unit respectively receives the corresponding/rs _ add < n: m +1>, the < m:0> bit address of each AND gate respectively receives the corresponding rs _ addb < m:0>, and the AND gates in the same group of multi-row selected row selection units sequentially replace the rs _ addb < m:0> with the corresponding bits of the rs _ add < m:0> from low bit to high bit according to a binary system; wherein,/rs _ add < n: m +1> is the negation signal of rs _ add < n: m +1>, m and n are natural numbers, and m is less than n. The utility model discloses can realize that the multirow is selected simultaneously, improve pixel array's reading speed greatly, and then promote image sensor's frame rate.

Description

Selection module, pixel row selection module and pixel reading circuit

Technical Field

The utility model relates to an integrated circuit design field especially relates to a select module, pixel row and select module and pixel readout circuit.

Background

The pixel array signals in the image sensor are generally read out in a row manner, wherein a row driving circuit selects a designated row of the pixel array through a row selection signal, then controls the reset and read-out of the pixel signals of the row through a reset signal and a transmission signal, and finally, the voltage signals of the row are converted into digital signals through a column level ADC for further processing. The reading speed of the pixel array signal directly affects the frame rate of the image sensor, and due to the characteristics that the pixels are read by millions and millions of levels and line by line, the improvement of the frame rate is always a difficult problem.

Therefore, how to increase the frame rate of the image sensor has become one of the technical problems to be solved by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of the above-mentioned shortcomings of the prior art, the present invention provides a selecting module, a pixel row selecting module and a pixel readout circuit, which are used to solve the problem of low frame rate of the image sensor in the prior art.

To achieve the above and other related objects, the present invention provides a selection module, based on a pixel array signal single-row readout architecture, the selection module comprising at least:

the pixel array comprises a group of multi-row selected row selection units, each multi-row selected row selection unit comprises a plurality of AND gates, the input end of each AND gate is connected with a corresponding address signal, and the output end of each AND gate outputs each row selection signal in the pixel array;

the < n: m +1> bit address of each AND gate in the multi-row selected row selection unit respectively receives a corresponding first address signal/rs _ add < n: m +1>, the < m:0> bit address of each AND gate respectively receives a corresponding second address signal rs _ addb < m:0>, and the AND gates in the same group of multi-row selected row selection units sequentially replace the second address signal rs _ addb < m:0> from low bit to high bit according to a binary system to corresponding bits of a third address signal rs _ add < m:0 >;

the first address signal/rs _ add < n: m +1> is an inverted signal of the third address signal rs _ add < n: m +1>, m and n are natural numbers, and m is smaller than n.

Optionally, the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, a second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … … to achieve 2*2 ^m The rows are selected simultaneously.

Optionally, the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for realizing even row selection every two rows.

Optionally, the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for even row selection.

Optionally, the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for realizing every two odd row selection.

Optionally, the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … … for odd row selection.

Optionally, the multi-row selected row selection unit comprises 3*2 ^m An AND gate with the last two bits removed connected to rs _ add<1>And rs _ add<0>The address combination of (2); and sets the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … … to achieve 3*2 ^m The rows are selected simultaneously.

More optionally, the selection module includes n-m groups of multiple selected row selection units, each of the multiple selected row selection units includes the same number of and gates, input ends of the and gates are connected to corresponding address signals, and output ends of the and gates respectively output the selected row selection signals in the pixel array;

the first address signal/rs _ add < m + N-1> of the m + N-1 bit of the N-th group of multi-row selected row selection units is replaced by a third address signal rs _ add < m + N-1>, and N is a positive integer less than or equal to N-m.

More optionally, the selected module includes 2*2 ^n-m -1 group of multi-row selected row selection units, each of which comprises an equal number of and gates, and the input end of each and gate is connected with a corresponding address signal and the output end outputs each row selection signal in the pixel array;

and the selected row selection units of each group of multiple rows replace the second address signal/rs _ add < n: m +1> with the corresponding bit of the third address signal rs _ add < n: m +1> according to a binary system from the low bit to the high bit in sequence.

To achieve the above and other related objects, the present invention also provides a pixel row selection module, which at least comprises:

the first and logic unit, the second and logic unit, the OR gate, the first selected module composed of the selected module selected by the even number lines simultaneously, and the 3*2 ^m-1 A second selection module formed by the selection modules selected in the row simultaneous selection;

the input end of the first AND logic unit receives an address signal and a first enabling signal respectively, the output end of the first AND logic unit is connected with the input end of the first selected module, and when the first enabling signal is effective, the first AND logic unit provides the address signal for the first selected module;

the input end of the second AND logic unit receives an address signal and a second enabling signal respectively, the output end of the second AND logic unit is connected with the input end of the second selected module, and the second AND logic unit provides the address signal for the second selected module when the second enabling signal is effective;

and the first input end of the OR gate is connected with the output end of the first selected module, the second input end of the OR gate is connected with the output end of the second selected module, and row selection signals of the pixel array are output.

To achieve the above and other related objects, the present invention also provides a pixel readout circuit, comprising at least:

the device comprises a pixel array, a reading module and the selecting module; the selection module provides a row selection signal for the pixel array; the readout module receives column readout signals of the pixel array.

the pixel array, the reading module and the pixel row selection module; the pixel row selection module provides row selection signals for the pixel array; the readout module receives column readout signals of the pixel array.

As described above, the utility model discloses a select module, pixel row and select module and pixel readout circuit has following beneficial effect:

1. the utility model discloses a select module, pixel row and select module and pixel readout circuit can realize that the multirow is selected simultaneously, improve pixel array's the speed of reading out greatly, and then promote image sensor's frame rate.

2. The utility model discloses a select module, pixel row and select module and pixel readout circuit and can realize 2*2 ^M Line or 3*2 ^m The rows are simultaneously selected, the purpose of simultaneously selecting the rows with different numbers is achieved by setting different address signals, and the method is high in flexibility and universality.

Drawings

Fig. 1 shows a schematic circuit structure diagram of the selected module according to the present invention.

Fig. 2 is a schematic diagram of another circuit structure of the selected module according to the present invention.

Fig. 3 is a schematic diagram of another circuit structure of the selected module according to the present invention.

Fig. 4 is a schematic circuit diagram of the pixel row selection module according to the present invention.

Fig. 5 shows an example of the pixel row selection module of the present invention.

Fig. 6 is a schematic diagram of a pixel readout circuit according to the present invention.

Fig. 7 is a schematic diagram of another structure of the pixel readout circuit according to the present invention.

Description of the element reference numerals

1. Pixel row selection module

11. First AND logic unit

12. Second AND logic unit

13. OR gate

14. First selection module

15. Second selected module

2. Pixel array

3. Readout module

4. Selection module

5. Pixel row selection module

Detailed Description

The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to fig. 1 to 7. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic concept of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, amount and proportion of each component may be changed arbitrarily and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present embodiment provides a selected block based on a single-row readout architecture of a pixel array signal, the selected block including:

the first address signal/rs _ add < n: m +1> is a negation signal of the third address signal rs _ add < n: m +1>, m and n are natural numbers, and m is smaller than n.

Specifically, the multi-row selected row selection unit comprises 2*2 ^m The output end of each AND gate respectively outputs 2*2 of the pixel array ^m Each row selection signal is marked as rowsel<0>、rowsel<1>……rowsel<2*2 ^m -2>、rowsel<2*2 ^m -1>. The input end of each AND gate comprises<n:0>The bit address. Of AND gates<n:m+1>The bit addresses all receive the corresponding first address signal/rs _ add<n:m+1>. Of AND gates<m:0>The second address signal rs _ addb is binary from the low bit to the high bit of the bit address in sequence<m:0>Is replaced with the third address signal rs _ add<m:0>The corresponding bit of (a); the first AND gate corresponds to binary 000 … … 000, and does not change the input address signal, so that the first AND gate<m:0>The bit address receives a corresponding second address signal rs _ addb<m:0>(ii) a The second AND gate changes the 0 th bit address signal corresponding to binary 000 … … 001, and therefore, of the second AND gate<m:1>The bit address receives a corresponding second address signal rs _ addb<m:1>Of said second AND gate<0>The bit address receives the corresponding third address signal rs _ add<0>(ii) a Accordingly, the third AND gate, corresponding to binary 000 … … 010, changes the 1 st bit address signal, and therefore, of the third AND gate<m:2>And<0>bit address receiving corresponding second address signal rs _ addb<m:2>And rs _ addb<0>Of said third AND gate<1>The bit address receives the corresponding third address signal rs _ add<1>(ii) a The fourth AND gate, corresponding to binary 000 … … 011, changes the 1 st and 0 th bit address signals, and therefore, of the fourth AND gate<m:2>The bit address receives a corresponding second address signal rs _ addb<m:2>Of said fourth AND gate<1:0>The bit address receives the corresponding third address signal rs _ add<1:0>(ii) a And so on, 2*2 ^m Of AND gates<m:0>The bit address receives the corresponding third address signal rs _ add<m:0>。

As a first example, let the second address signal rs _ addb<m:0>=11 … …, rs _ add in the third address signal<n:m+1>=00 … … rs _ add in the third address signal<m:0>=11 … …, then, the first address signal/rs _ add<n:m+1>=11 … …. At this time, the input end signal/rs _ add of the first AND gate<n>、/rs_add<n-1>、/rs_add<n-2>……/rs_add<m+1>、rs_addb<m>、rs_addb<m-1>……rs_addb<1>、rs_addb<0>Are all 1, and the row selection signal rowsel generated after the AND logic<0>High level, for controlling the 0 th row of the selected pixel array; input end signal/rs _ add of the second AND gate<n>、/rs_add<n-1>、/rs_add<n-2>……/rs_add<m+1>、rs_addb<m>、rs_addb<m-1>……rs_addb<1>、rs_add<0>Are all 1, row select signal rowsel<1>High level, for controlling the selected pixel array row 1; similarly, rowsel<2>、rowsel<3>……rowsel<2*2 ^m -1>Are all high levelFor controlling selected pixel array 2 nd to 2*2 ^m -1 row; realize 2*2 ^m The rows are selected simultaneously.

As a second example, let the second address signal rs _ addb < m:0> =11 … …, rs _ add < n: m +1> =00 … … 00 in the third address signal, and rs _ add < m:0> =11 … … in the third address signal, then the first address signal/rs _ add < n: m +1> =11 … …. At this time, the input end signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1>, and rs _ addb <0> of the first and gate are all 1, the row selection signal rowsel <0> is at high level, and the 0 th row of the pixel array is selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1>, and rs _ add <0> at the input end of the second AND gate are all 1, a row selection signal rowsel <1> is high level, and the 1 st row of the pixel array is selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2>, rs _ addb <0> are all 1, rs \uadd <1> is 0, row selection signals rowsel <2> are low level, and row 2 of the middle pixel array is not selected; input end signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2> are all 1, rs \uadd < -1> is 0, rs _add < -0 > is 1, row selection signals rowsel <3> are low level, and the 3 rd row of the pixel array is not selected; by analogy, row selection signals rowsel <4> and rowsel <5> are high level, row selection signals rowsel <6> and rowsel <7> are low level … …, every two rows are selected in one group at intervals, and simultaneous selection of every two even rows (the 2i th row and the 2i +1 th row, i is an even number more than or equal to 0) is realized.

As a third example, let the second address signal rs _ addb < m:0> =11 … …, rs _ add < n: m +1> =00 … … 00 in the third address signal, and rs _ add < m:0> =11 … … in the third address signal, then the first address signal/rs _ add < n: m +1> =11 … …. At the moment, signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1>, and rs _ addb <0> at the input end of the first AND gate are all 1, a row selection signal rowsel <0> is at a high level, and a 0 th row of the pixel array is selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1> are all 1, rs _ add <0> is 0, a row selection signal rowsel <1> is at a low level, and the 1 st row of the pixel array is not selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2>, rs _ addb <0> are all 1, rs \uadd group 1> is 1, row selection signals rowsel <2> are high level, and row 2 of the pixel array is selected; input end signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2> are all 1, rs \\ u add < -1> is 1, rs \\ u ad < -0 > is 0, row selection signals rowsel <3> are low level, and the row 3 of the pixel array is not selected; by analogy, the row selection signal rowsel <4> is high level, the row selection signal rowsel <5> is low level … …, each row is in one group and is selected at intervals, and even rows (2 j, j is a natural number) are selected simultaneously.

As a fourth example, let the second address signal rs _ addb < m:0> =11 … …, rs _ add < n: m +1> =00 … … in the third address signal, and rs _ add < m:0> =11 … … in the third address signal, then the first address signal/rs _ add < n: m +1> =11 … …. At this time, the input end signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2>, rs _ addb <0> are all 1, rs _addb <1> is 0, the row selection signal rowsel <0> is low level, and the 0 th row of the pixel array is not selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2>, rs _ add <0> are all 1, rs \uaddb < (1) > is 0, row selection signals rowsel <1> are low level, and row 1 of the middle pixel array is not selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2>, rs _ addb <0> are all 1, rs \uadd group 1> is 1, row selection signals rowsel <2> are high level, and row 2 of the pixel array is selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2> at the input end of the fourth AND gate are all 1, rs _ add but 1> is 0, row selection signals rowsel <3> are high level, and the 3 rd row of the pixel array is selected; by analogy, row selection signals rowsel <4> and rowsel <5> are at low level, row selection signals rowsel <6> and rowsel <7> are at high level … …, every two rows are grouped into one group, and the odd rows (the 2k th row and the 2k +1 row, and k is an odd number larger than 0) in every two rows are selected at intervals.

As a fifth example, let the second address signal rs _ addb < m:0> =11 … …, rs _ add < n: m +1> =00 … … in the third address signal, and rs _ add < m:0> =11 … … in the third address signal, then the first address signal/rs _ add < n: m +1> =11 … …. At this time, the input end signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1> are all 1, rs \uaddb <0> is 0, the row selection signal rowsel <0> is at low level, and the 0 th row of the pixel array is not selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <1> are all 1, rs \_add 0> is 1, row selection signals rowsel <1> are high level, and the 1 st row of the pixel array is selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2> are all 1, rs \uadd < -1> is 1, rs _addb < -0 > is 0, row selection signals rowsel <2> are low level, and the row 2 of the pixel array is not selected; signals/rs _ add < n >,/rs _ add < n-1>,/rs _ add < n-2> … …/rs _ add < m +1>, rs _ addb < m-1> … … rs _ addb <2> at the input end of the fourth AND gate are all 1, rs _ add is 1, row selection signals rowsel <3> are high level, and the 3 rd row of the pixel array is selected; by analogy, the row selection signal rowsel <4> is at low level, the row selection signal rowsel <5> is at high level … …, each row is grouped and selected at intervals, and the odd rows (2l +1 row, l is a natural number) are selected simultaneously.

It should be noted that the second address signal rs _ addb may be applied as needed<m:0>And the third address signal rs _ add<n:0>Assigned values to achieve different numbers (2*2) ^M M is a natural number) rows; including but not limited to the simultaneous selection of odd/even rows every 4 rows and odd/even rows every 8 rows … …, which are not described herein in detail.

It should be noted that if the second address signal rs _ addb < m:0> is the negation of rs _ add < m:0> in the third address signal, it is changed to a normal read in which only one row is selected for each address.

Example two

As shown in fig. 2, this embodiment provides a selection module, where the selection module includes n-m groups of multiple selected row selection units, each of the multiple selected row selection units includes and gates with the same number, input ends of the and gates are connected to corresponding address signals, and output ends of the and gates respectively output multiple selected row selection signals in a pixel array;

the first address signal/rs _ add < m + N-1> of the m + N-1 th bit of the N-th group of multi-row selected row selection units is replaced by a third address signal rs _ add < m + N-1>, and N is a positive integer less than or equal to N-m.

Specifically, as shown in FIG. 1, the firstThe structure of one row of selected row selection units is the same as that of the row of selected row selection unit 1 in the first embodiment, and details are not repeated here. As shown in FIG. 2, the second multiple row selected row selection unit also includes 2*2 ^m Individual AND gates, of each AND gate<n:m+2>And<m:0>the bit is consistent with the corresponding AND gate in the first row selection unit, and the first of each AND gate<m+1>Bit is replaced with the third address signal rs _ add<m+1>. The third multi-row selected row selection unit also comprises 2*2 ^m Individual AND gates, of each AND gate<n:m+3>And<m+1:0>the bit is consistent with the corresponding AND gate in the first row selection unit, and the first of each AND gate<m+2>Bit is replaced with the third address signal rs _ add<m+2>. In analogy, the n-m group multi-row selected row selection unit also comprises 2*2 ^m Individual AND gates, of each AND gate<n-1:0>The bit is consistent with the corresponding AND gate in the first row selected row selection unit, and the first of each AND gate<n>Bit is replaced with the third address signal rs _ add<n>. The third multi-row selection unit … … and the n-m group of multi-rows selection unit is not shown in the figure, and those skilled in the art can know the selection result based on the description of the present invention, which is not repeated herein.

EXAMPLE III

The present embodiment provides a selection module, which is different from the second embodiment in that the selection module includes 2*2 ^n-m -1 group of multi-row selected row selection units, each of which comprises an equal number of and gates, and the input end of each and gate is connected with a corresponding address signal and the output end outputs each row selection signal in the pixel array;

Specifically, the first row-selected unit corresponds to binary 00 … …, and therefore, the input address signal is not replaced, and the structure of the first row-selected unit is the same as that of row-selected unit 1 in the first embodiment, which is not described herein again. The second multi-row selected row selection unit also comprises 2*2 ^m AND gates corresponding to binary 00 … …, of each AND gate<n:m+2>And<m:0>the bit is consistent with the corresponding AND gate in the first row selected row selection unit, and the first of each AND gate<m+1>Bit is replaced with the third address signal rs _ add<m+1>. The third row selection unit also comprises 2*2 ^m An AND gate corresponding to binary 00 … …, the AND gates<n:m+3>And<m+1:0>the bit is consistent with the corresponding AND gate in the first row selected row selection unit, and the first of each AND gate<m+2>Bit is replaced with the third address signal rs _ add<m+2>. The fourth multi-row selected row selection unit also comprises 2*2 ^m AND gates corresponding to binary 00 … …, of respective AND gates<n:m+3>And<m:0>the bit is consistent with the corresponding AND gate in the first row selection unit, and the first of each AND gate<m+2:m+1>Bit is replaced with the third address signal rs _ add<m+2:m+1>. In the same way, the n-m group multi-row selected row selection unit also comprises 2*2 ^m Individual AND gates, of each AND gate<m:0>The bit is consistent with the corresponding AND gate in the first row selected row selection unit, and the first of each AND gate<n:m+1>All bits are replaced by the third address signal rs _ add<n:m+1>。

Example four

As shown in fig. 3, the present embodiment provides a selection module, which is different from the selection module of the first embodiment in that the selection module of the present embodiment is used to implement 3*2 ^m The rows are selected simultaneously.

Specifically, the selection module comprises a group of multi-row selection units, and the multi-row selection units comprise 3*2 ^m And the output ends of the AND gates respectively output 3*2 of the pixel array ^m Each row selection signal is marked as rowsel<0>、rowsel<1>……rowsel<2*2 ^m -2>、rowsel<3*2 ^m -1>. The input end of each AND gate comprises<n:0>The bit address. Of AND gates<n:m+1>The bit addresses all receive corresponding first address signal/rs _ add<n:m+1>. Of AND gates<m:0>The second address signal rs _ addb is binary from the low bit to the high bit of the bit address in sequence<m:0>Is replaced with the third address signal rs _ add<m:0>And the two removed bits are respectively connected with rs _ add<1>And rs _ add<0>The address combination of (1);the first AND gate corresponds to binary 000 … … 000, and does not change the input address signal, so that the first AND gate<m:0>Bit address receiving corresponding second address signal rs _ addb<m:0>(ii) a The second AND gate changes the 0 th bit address signal corresponding to binary 000 … … 001, and therefore, of the second AND gate<m:1>The bit address receives a corresponding second address signal rs _ addb<m:1>Of said second AND gate<0>The bit address receives the corresponding third address signal rs _ add<0>(ii) a The third AND gate changes the 1 st bit address signal to correspond to binary 000 … … 010, and therefore of said third AND gate<m:2>And<0>bit address receiving corresponding second address signal rs _ addb<m:2>And rs _ addb<0>Of said third AND gate<1>The bit address receives the corresponding third address signal rs _ add<1>(ii) a The last two bits of the binary system are respectively replaced by rs _ add<1>And rs _ add<0>So that the fourth and gate, corresponding to binary 000 … … 100, changes the 2 nd bit address signal, the fourth and gate' s<m:3>And<1:0>the bit address receives a corresponding second address signal rs _ addb<m:3>And rs _ addb<1:0>Of said fourth AND gate<2>The bit address receives the corresponding third address signal rs _ add<2>(ii) a A fifth AND gate corresponding to binary 000 … … for changing the 2 nd and 0 th bit address signals<m:3>And<1>the bit address receives a corresponding second address signal rs _ addb<m:3>And rs _ addb<1>Of said fifth AND gate<2>And<0>the bit address receives the corresponding third address signal rs _ add<2>And rs _ add<0>(ii) a A sixth AND gate corresponding to binary 000 … … for changing the 2 nd and 1 st bit address signals<m:3>And<0>bit address receiving corresponding second address signal rs _ addb<m:3>And rs _ addb<0>Of said sixth AND gate<2:1>The bit address receives the corresponding third address signal rs _ add<2:1>(ii) a And so on, 3*2 ^m -2 of AND gates<m:2>The bit address receives the corresponding third address signal rs _ add<m:2>3*2 ^m -2 of AND gates<1:0>Bit address receiving corresponding second address signal rs _ addb<1:0>(ii) a 3*2 ^m -1 and gate<m:2>And<0>bit address receptionCorresponding third address signal rs _ add<m:2>And rs _ add<0>3*2 ^m -1 and gate<1>The bit address receives a corresponding second address signal rs _ addb<1>(ii) a 3*2 ^m Of AND gates<m:1>The bit address receives the corresponding third address signal rs _ add<m:1>3*2 ^m Of AND gates<0>The bit address receives a corresponding second address signal rs _ addb<0>。

It should be noted that, the last two bits of the address bits are respectively replaced with the address combination of rs _ add <1> and rs _ add <0> to skip, that is, on the basis of the first embodiment, the addresses of

rows

3, 7 and 11 … … are sequentially deleted (i.e., 1 bit is skipped and 0 bit is connected with the addresses of rs _ add <1> and rs _ add <0 >); and so on, which are not repeated herein.

More optionally, let the second address signal rs _ addb<m:0>=11 … …, rs _ add in the third address signal<n:m+1>=00 … … rs _ add in the third address signal<m:0>=11 … …, then, the first address signal/rs _ add<n:m+1>=11 … …. At this time, the input end signal/rs _ add of the first AND gate<n>、/rs_add<n-1>、/rs_add<n-2>……/rs_add<m+1>、rs_addb<m>、rs_addb<m-1>……rs_addb<1>、rs_addb<0>Are all 1, row select signal rowsel<0>Selecting a 0 th row of the pixel array when the level is high; input end signal/rs _ add of the second AND gate<n>、/rs_add<n-1>、/rs_add<n-2>……/rs_add<m+1>、rs_addb<m>、rs_addb<m-1>……rs_addb<1>、rs_add<0>Are all 1, row select signal rowsel<1>Select row 1 of the pixel array for high(ii) a Input end signal/rs _ add of the third AND gate<n>、/rs_add<n-1>、/rs_add<n-2>……/rs_add<m+1>、rs_addb<m>、rs_addb<m-1>……rs_addb<1>、rs_add<0>Are all 1, row select signal rowsel<1>Selecting a 1 st row of the pixel array at a high level; similarly, rowsel<3>、rowsel<4>……rowsel<3*2 ^m -1>All are high level, and the 3 rd to 3*2 pixel arrays are selected ^m -1 row; realize 3*2 ^m The rows are simultaneously selected.

EXAMPLE five

The present embodiment provides a selection module, which is different from the second embodiment in that the multi-row selected row selection unit can also be implemented by using the structure of the second embodiment.

Specifically, similarly, bits < m:0> of each and gate in each multi-row selected row selection unit are consistent with corresponding and gates in the multi-row selected row selection unit of the second embodiment, and the first address signal/rs _ add < m + N-1> of the m + N-1 bit of the nth group of multi-row selected row selection units in each multi-row selected row selection unit is replaced with the third address signal rs _ add < m + N-1>, which is not described in detail herein.

EXAMPLE six

The present embodiment provides a selection module, which is different from the third embodiment in that the multi-row selected row selection unit can also be implemented by using the structure of the second embodiment.

Specifically, similarly, the bits < m:0> of each and gate in each row selected row selection unit are consistent with the corresponding and gate in the row selected row selection unit in the second embodiment, and each row selected row selection unit replaces the second address signal/rs _ add < n: m +1> with the corresponding bits of the third address signal rs _ add < n: m +1> according to a binary system from a low bit to a high bit in sequence, which is not described herein again.

EXAMPLE seven

As shown in fig. 4, the present embodiment provides a pixel row selection module 1, where the pixel row selection module 1 includes:

first and logic unit 11, second and logic unit 12, or gate 13, first selection module 14 and second selection module 15.

As shown in fig. 4, the input terminals of the first and logic unit 11 respectively receive an address signal and a first enable signal en ₀ The output terminal is connected to the input terminal of the first selected module 14 when the first enable signal en is asserted ₀ When active, provides an address signal to the first selected module 14.

Specifically, in this embodiment, the first and logic unit 11 includes two and gates, and one input end of the two and gates is respectively connected to the second address signal rs _ addb<m:0>And rs _ add in the third address signal<n:0>And the other ends are connected with the first enabling signal en ₀ The outputs are connected to said first selection module 14, respectively. In practical use, the structure of the first and logic unit 11 may be set as required, and the above functions may be implemented, which is not limited to this embodiment.

As shown in fig. 4, the input terminals of the second and logic unit 12 respectively receive an address signal and a second enable signal en ₁ The output end of the second selection module 15 is connected with the input end of the second selection module 15 when the second enable signal en is used ₁ When active, provides an address signal to the second selected module 15.

Specifically, in this embodiment, the second and logic unit 12 has the same structure as the first and logic unit 11, and only the received enable signals are different, which is not described herein. In practical use, the structure of the second and logic unit 12 may be set as required to implement the above-mentioned functions, and the present embodiment is not limited thereto.

As shown in FIG. 4, the first selected module 14 is used to implement 2*2 ^a And simultaneously selecting rows, wherein a is an integer which is greater than or equal to 0.

Specifically, the first selecting module 14 may adopt the selecting module of the first embodiment, the second embodiment or the third embodiment, which is not described herein in detail.

As shown in FIG. 4, the second selected module 15 is used to implement 3*2 ^a And simultaneously selecting rows, wherein a is an integer which is greater than or equal to 0.

Specifically, the second selection module 15 may adopt the selection module in the fourth embodiment, the selection module in the fifth embodiment, or the selection module in the sixth embodiment, which are not described herein again.

As shown in fig. 4, a first input terminal of the or gate 13 is connected to the output terminal of the first selected module 14, a second input terminal is connected to the output terminal of the second selected module 15, and a row selection signal rowsel < n:0> of the pixel array is output.

As shown in fig. 4, by the first enable signal en ₀ With said second enable signal en ₁ The switching control of two different address selection modes can be realized.

As shown in fig. 5, as an example, a scheme for simultaneously selecting 4 rows or 3 rows is implemented, which includes the second address signal rs _ addb <1:0> and the third address signal rs _ add <3:0>. When the second address signal rs _ addb <1:0> =11 and the third address signal rs _ add <3:0> =0011, the 0 th, 1 th, 2 th, and 3 rd rows may be selected based on the first selecting module 34 or the 0 th, 1 th, and 2 th rows may be selected based on the second selecting module 35. When the second address signal rs _ addb <1:0> =11 and the third address signal rs _ add <3:0> =0111, the

rows

4, 5, 6, and 7 may be selected based on the first selecting module 34 or the

rows

3, 4, and 5 may be selected based on the second selecting module 35. For convenience of illustration, in fig. 5, each of the first selecting module 14 and the second selecting module 15 only displays 2 groups of multi-row selected row selecting units, and in actual use, the number of the multi-row selected row selecting units may be set as needed.

Example eight

As shown in fig. 6, the present embodiment provides a pixel readout circuit including:

pixel array 2, readout module 3 and selection module 4.

As shown in fig. 6, the selected block 4 provides a row selection signal rowsel < n:0> to the pixel array 2, and the selected block 4 is any one of the first to sixth embodiments. As an example, the selection module 4 also provides reset signals rst < n:0> and transmission signals tx < n:0>.

As shown in fig. 6, the readout module 3 receives column readout signals of the pixel array 2; in this embodiment, the readout module 3 is a column ADC, and outputs a digital signal; in practical use, the readout module can be set as required, and the readout function can be implemented, which is not limited to this embodiment.

Example nine

As shown in fig. 7, this embodiment provides a pixel readout circuit, which is different from the eighth embodiment in that a pixel row selection module 5 is used to replace the selection module 4; the pixel row selection module 5 is the pixel row selection module in the seventh embodiment, which is not described herein in detail.

The utility model discloses realize the addressing method that the multirow was selected simultaneously on the basis of selecting the pixel single file to can read out simultaneously realizing multirow pixel signal under the specific case, and then promote image sensor's frame rate, improve pixel array signal's reading speed.

To sum up, the utility model provides a select module, pixel row and select module and pixel readout circuit, include: the pixel array comprises a group of multi-row selected row selection units, wherein each multi-row selected row selection unit comprises a plurality of AND gates, the input end of each AND gate is connected with a corresponding address signal, and the output end of each AND gate outputs each row selection signal in the pixel array; of AND gates in said multiple selected row selection unit<n:m+1>The bit addresses respectively receive the corresponding first address signals/rs _ add<n:m+1>Of AND gates<m:0>The bit addresses respectively receive the corresponding second address signals rs _ addb<m:0>And each AND gate in the same group of multi-row selected row selection units sequentially uses a second address signal rs _ addb from low order to high order according to a binary system<m:0>Is replaced with the third address signal rs _ add<m:0>The corresponding bit of (a); wherein the first address signal/rs _ add<n:m+1>Is the third address signal rs _ add<n:m+1>M and n are both natural numbers, and m is smaller than n. The utility model discloses a select module, pixel row and select module and pixel readout circuit can realize that the multirow is selected simultaneously, improve pixel array's reading speed greatly, and then promote image sensor's frame rate; can realize 2*2 ^M Row or 3*2 ^m The lines are simultaneously selected, the purpose of simultaneously selecting the lines with different numbers is achieved by setting different address signals, and the method is high in flexibility and universality. Therefore, the utility modelEffectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the claims of the present invention.

Claims

1. A selected block based on a pixel array signal single row readout architecture, the selected block comprising at least:

2. The selection module of claim 1, wherein:

the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, a second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … …, in orderImplementation 2*2 ^m The rows are simultaneously selected.

3. The selection module of claim 1, wherein:

the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for realizing even row selection every two rows.

4. The selection module of claim 1, wherein:

the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for even row selection.

5. The selection module of claim 1, wherein:

the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>And =11 … … for realizing every two odd row selection.

6. The selection module of claim 1, wherein:

the multi-row selected row selection unit comprises 2*2 ^m An AND gate, in the multiple row selected row selection unit, the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … … for odd row selection.

7. The selection module according to claim 1, characterized in that theThe multi-row selected row selection unit comprises 3*2 ^m An AND gate with the last two bits removed connected to rs _ add<1>And rs _ add<0>The address combination of (1); and sets the second address signal rs _ addb<m:0>=11 … …, rs _ add in third address signal<n:m+1>＝00……00、rs_add<m:0>=11 … … to achieve 3*2 ^m The rows are selected simultaneously.

8. The selection module according to any one of claims 1 to 7, characterized in that: the selection module comprises n-m groups of multi-row selection line selection units, each multi-row selection line selection unit comprises the same number of AND gates, the input end of each AND gate is connected with a corresponding address signal, and the output end of each AND gate outputs each row selection signal in the pixel array;

9. The selection module according to any one of claims 1 to 7, characterized in that: the selection module comprises 2*2 ^n-m -1 group of multi-row selected row selection units, each of which comprises an equal number of and gates, and the input end of each and gate is connected with a corresponding address signal and the output end outputs each row selection signal in the pixel array;

and each group of multi-row selected row selection units sequentially replace the second address signal/rs _ add < n: m +1> with the corresponding bit of the third address signal rs _ add < n: m +1> from the low bit to the high bit according to the binary system.

10. A pixel row selection module, comprising:

the first AND logic unit, the second AND logic unit, the OR gate, the first selection module and the second selection module; the first selection module is a selection module for simultaneously selecting even number of rows and is formed by the selection module according to any one of claims 2-6, 8 and 9; the second selected module is 3*2 ^m-1 Line selectionThe selection module of claim 7-9;

the input end of the second AND logic unit receives an address signal and a second enabling signal respectively, the output end of the second AND logic unit is connected with the input end of the second selected module, and when the second enabling signal is effective, the second AND logic unit provides the address signal for the second selected module;

11. A pixel readout circuit, comprising at least:

a pixel array, a readout module and a selection module according to any one of claims 1-9; the selection module provides row selection signals for the pixel array; the readout module receives column readout signals of the pixel array.

12. A pixel readout circuit, comprising at least:

a pixel array, a readout module, and the pixel row selection module of claim 10; the pixel row selection module provides row selection signals for the pixel array; the readout module receives column readout signals of the pixel array.