CN217544606U

CN217544606U - Embedded chip packaging structure

Info

Publication number: CN217544606U
Application number: CN202220461485.4U
Authority: CN
Inventors: 李家铭
Original assignee: Guangdong Zecheng Technology Co ltd
Current assignee: Guangdong Zecheng Technology Co ltd
Priority date: 2022-01-20
Filing date: 2022-03-03
Publication date: 2022-10-04
Anticipated expiration: 2032-03-03
Also published as: TWM627448U

Abstract

The application provides an embedded chip packaging structure, including a circuit substrate, an at least IC chip, a complete solidified insulating glue layer, a copper foil layer, at least one through-hole, a chemical copper plating layer and an electroplating copper layer that are formed at insulating glue layer and this copper foil layer, this IC chip subsides are adorned in a surface of this circuit substrate, this IC chip has an at least naked pin, do not have glass fiber in this insulating glue layer, this pin contact this insulating glue layer but not contact this copper foil layer, this IC chip of this insulating glue layer cover and cladding, this insulating glue layer is covered to this copper foil layer, this through-hole corresponds to the pin, this chemical copper plating layer electricity is connected between this pin and this copper foil layer, this electroplating copper layer is formed on this chemical copper plating layer.

Description

Embedded chip packaging structure

Technical Field

The application relates to an embedded chip packaging technology.

Background

Unlike many IC chips mounted on the surface of a circuit board, embedded chip packaging embeds an IC chip in an inner layer of a circuit board. In order to form electrical connection with the pins of the embedded IC chip, it is necessary to form through holes at positions corresponding to the pins and plate copper in the through holes. In the prior art, the through holes are formed by laser engraving, and a part of the IC chip is easily damaged by laser irradiation during the process, so that improvement is needed.

SUMMERY OF THE UTILITY MODEL

The present application is directed to provide an embedded chip package technique capable of preventing an IC chip from being irradiated by laser.

In order to achieve the above and other objects, the present application provides an embedded chip package structure, including a circuit substrate, at least one IC chip, a completely cured insulating adhesive layer, a copper foil layer, at least one through hole formed in the insulating adhesive layer and the copper foil layer, a copper plated layer and a copper plated layer, wherein the IC chip is attached to a surface of the circuit substrate, the IC chip has at least one exposed pin, the insulating adhesive layer does not have glass fiber therein, the pin contacts the insulating adhesive layer but does not contact the copper foil layer, the insulating adhesive layer covers and wraps the IC chip, the copper foil layer covers the insulating adhesive layer, the through hole corresponds to the pin, the copper plated layer is electrically connected between the pin and the copper foil layer, and the copper plated layer is formed on the copper plated layer.

Because the insulating glue layer used in the application does not have glass fiber and is still in the B stage when just attached to the circuit substrate, the hole site insulating glue region can be removed through the etching solution without using laser engraving, and the problem that the IC chip is easy to damage due to laser irradiation is further avoided.

Other features and embodiments of the present application will be described in detail below with reference to the drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 to 9 are schematic views illustrating a manufacturing process according to an embodiment of the present application.

Description of the symbols

1: embedded chip packaging structure

10: circuit board 11: dielectric layer 20: IC chip

21: pin 30: adhesive-backed copper foil 31: copper foil layer

311: hole site copper foil area 32: insulating adhesive layer 321: hole site insulating glue area

33: through-hole 40: copper layer 50: electroplated copper layer

Detailed Description

The positional relationship described in the following embodiments includes: the top, bottom, left and right, unless otherwise indicated, are based on the orientation of the elements in the drawings.

The present application discloses a packaging process for an embedded chip to fabricate an embedded chip package structure, and the following describes the process of one embodiment of the present application with reference to fig. 1 to 9, wherein the circuit design is simplified for illustrative purposes, but the actual circuit design is not limited thereto.

The embedded chip packaging structure of the embodiment is manufactured by a manufacturing process comprising the following steps of:

step (1):

referring to fig. 1 and fig. 2, at least one IC chip 20 is mounted on a surface of a circuit substrate 10, the IC chip 20 has at least one exposed pin 21, the exposed pin 21 does not directly contact the surface of the circuit substrate 10, and the IC chip 20 is mounted on a dielectric layer 11 on the surface of the circuit substrate 10, but not limited thereto. The power substrate 10 can be fabricated by any suitable method as required, and the IC chip 20 can be, for example, an active device, a passive device, a MEMS or other chip.

Step (2):

referring to fig. 3 and 4, a back-adhesive copper foil 30 is further attached to the surface of the circuit substrate 10, wherein the back-adhesive copper foil 30 has a copper foil layer 31 and a B-Stage (B-Stage) insulation adhesive layer 32, the insulation adhesive layer 32 is coated on the copper foil layer 31, the insulation adhesive layer 32 does not have glass fibers, the pins 21 contact the insulation adhesive layer 32 but do not contact the copper foil layer 31, and the insulation adhesive layer 32 covers and wraps the IC chip 20; the insulating adhesive layer 32 may be, for example, an epoxy-based, acrylic-based, polyimide-based, photo-and/or thermal-curable resin, and the B-stage refers to a state where the curable resin is not completely cured but is dried to have a finger-touch drying property; according to the characteristics of photocuring and/or thermocuring, the resin in the B stage can be completely cured to the C stage under the irradiation of specific light waves and/or at a specific curing temperature; in the present application, the insulating glue layer 32 is maintained in the B-stage before step (5). The copper foil layer 31 has at least one hole site copper foil area 311 corresponding to the pin 21, the insulation adhesive layer 32 has at least one hole site insulation adhesive area 321 corresponding to the pin 21, and the hole site insulation adhesive area 321 is covered by the hole site copper foil area 311.

And (3):

referring to fig. 5, the hole copper foil region 311 is removed, thereby exposing the hole insulating glue region 321. In a possible embodiment, the hole-site copper foil region 311 is removed by conventional methods such as attaching a photoresist, exposing, developing, etching, etc., but not limited thereto, for example, it can be removed by laser engraving.

And (4):

referring to fig. 6, the hole site insulating adhesive region 321 is removed by using an etching solution, so as to form at least one through hole 33 corresponding to the pin 21 on the adhesive-backed copper foil 30; the etching solution is an agent capable of removing the B-stage insulating glue layer contacted with the etching solution. After the hole site insulating glue area 321 is removed, the pins 21 may be exposed. It should be noted that in steps (3) and (4), the leads 21 and other parts of the IC chip 20 are not exposed to laser, so as to avoid damage.

And (5):

depending on the photo-curing and/or thermal curing properties of the insulation paste layer 32, the insulation paste layer 32 in the B-stage can be completely cured under the irradiation of a specific light wave and/or at a specific curing temperature, and the appearance thereof can still maintain the appearance shown in fig. 6.

And (6):

as shown in fig. 7, a electroless copper plating layer 40 is formed on the copper foil layer 31 and in the through hole 33 by electroless plating.

And (7):

as shown in fig. 8, a copper electroplating layer 50 is formed on the electroless copper plating layer 40 by electroplating.

And (8):

the copper foil layer 31, the electroless copper plated layer 40 and the electrolytic copper plated layer 50 are subjected to patterning treatment to obtain a state shown in fig. 9. The circuit substrate may be formed with other blind holes or through holes, and the fabrication of these blind holes and through holes may be performed in steps (3) and (4), but the fabrication flow of these blind holes and through holes is not specifically shown in the drawings.

An embedded chip package 1 is completed after the above steps, and comprises a circuit substrate 10, at least one IC chip 20, a fully cured insulation adhesive layer 32, a copper foil layer 31, at least one through hole 33 formed in the insulation adhesive layer 32 and the copper foil layer 31, a copper plated layer 40 and a copper plated layer 50, wherein the IC chip 20 is attached to the surface of the circuit substrate 10, the IC chip 20 has at least one exposed pin 21, the insulation adhesive layer 32 does not contain glass fiber, the pin 21 contacts the insulation adhesive layer 32 but does not contact the copper foil layer 31, the insulation adhesive layer 32 covers and wraps the IC chip 20, the copper foil layer 31 covers the insulation adhesive layer 32, the through holes 33 respectively correspond to the pins 21, the copper plated layer 40 is electrically connected between the pins 21 and the copper foil layer 31, and the copper plated layer 50 is formed on the copper plated layer 40. The embedded chip package structure 1 may be further processed according to design requirements.

The above-described embodiments and/or implementations are only for illustrating the preferred embodiments and/or implementations of the technology of the present application, and are not intended to limit the implementations of the technology of the present application in any way, and those skilled in the art can make modifications or changes to other equivalent embodiments without departing from the scope of the technology disclosed in the present application, but should be construed as technology or implementations substantially the same as the present application.

Claims

1. An embedded chip packaging structure is characterized by comprising a circuit substrate, at least one IC chip, a completely cured insulating glue layer, a copper foil layer, at least one through hole formed in the insulating glue layer and the copper foil layer, a chemical copper plating layer and an electroplated copper layer, wherein the IC chip is attached to one surface of the circuit substrate and is provided with at least one exposed pin, the insulating glue layer does not contain glass fibers, the pin is in contact with the insulating glue layer but not in contact with the copper foil layer, the insulating glue layer covers and wraps the IC chip, the copper foil layer covers the insulating glue layer, the through hole corresponds to the pin, the chemical copper plating layer is electrically connected between the pin and the copper foil layer, and the electroplated copper layer is formed on the chemical copper plating layer.