CN217544164U

CN217544164U - DDR dilatation layout structure and electronic terminal

Info

Publication number: CN217544164U
Application number: CN202221344875.XU
Authority: CN
Inventors: 方志刚; 张璇; 谢烈枚
Original assignee: Nanchang Yiqin Technology Co ltd
Current assignee: Nanchang Yiqin Technology Co ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-10-04
Anticipated expiration: 2032-05-31

Abstract

The embodiment of the utility model discloses DDR dilatation layout structure and electronic terminal for solve the technical problem that current system level chip SOC can't realize the dilatation of double data rate synchronous dynamic random access memory DDR. The embodiment of the utility model provides a system level chip SOC and DDR switching circuit board; the DDR switching circuit board is electrically connected to the system-on-chip SOC, and at least two DDR SDRAMs are electrically connected to the DDR switching circuit board. In this embodiment, the DDR adapter circuit board is electrically connected to the SOC and the DDR adapter circuit board is electrically connected to at least two DDR sdram devices, so that the DDR sdram devices on the SOC are expanded, and the demands of different electronic terminals for the DDR capacity are met.

Description

DDR dilatation layout structure and electronic terminal

Technical Field

The utility model relates to a chip relates to technical field, especially relates to a DDR dilatation layout structure and electronic terminal.

Background

In the existing electronic terminal, a system on chip SOC, also called a system on chip, is generally provided, and the academic circles at home and abroad generally tend to define the SOC as a system integrating a microprocessor, an analog IP core, a digital IP core and a memory (or an off-chip memory control interface).

Because the size of the conventional system-on-chip SOC is limited to be small, as shown in fig. 2, the system-on-chip SOC generally only has a single connection terminal for connection with a DDR (double data rate synchronous dynamic random access memory), so that the DDR expansion cannot be realized in the conventional system-on-chip SOC.

Therefore, it is an important issue to be studied by those skilled in the art to find a DDR expansion layout structure and an electronic terminal that can solve the above technical problems.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model discloses DDR dilatation layout structure and electronic terminal for solve the technical problem that current system level chip SOC can't realize the dilatation of double data rate synchronous dynamic random access memory DDR.

The embodiment of the utility model provides a DDR dilatation layout structure, including system level chip SOC and DDR switching circuit board;

the DDR switching circuit board is electrically connected to the system-on-chip SOC, and at least two DDR SDRAMs are electrically connected to the DDR switching circuit board.

Optionally, the system on chip SOC has a first connection end for electrically connecting to a DDR transfer circuit board, and the DDR transfer circuit board is electrically connected to the first connection end.

Optionally, the DDR adapter circuit board has at least two second connection terminals for electrically connecting to a DDR sdram.

Optionally, each of the second connection terminals is electrically connected to the double data rate synchronous dynamic random access memory DDR.

Optionally, at least two of the second connection ends are distributed on the DDR adapter circuit board at a preset distance.

Optionally, a control circuit board for carrying the system on chip SOC is included;

the system level chip SOC is electrically connected to the control circuit board.

Optionally, a plurality of resistance-capacitance sensing elements are electrically connected to the control circuit board.

Optionally, the resistance-capacitance sensing element includes a resistor, a capacitor and an inductor.

The embodiment of the utility model provides an electronic terminal, including foretell DDR dilatation layout structure.

According to the technical solution provided by the utility model, the embodiment of the utility model has the following advantage:

in this embodiment, the DDR adapter circuit board is electrically connected to the SOC and the DDR adapter circuit board is electrically connected to at least two DDR sdram devices, so that the DDR sdram devices on the SOC are expanded, and the demands of different electronic terminals for the DDR capacity are met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic diagram of a DDR expansion layout structure provided in an embodiment of the present invention;

FIG. 2 is a schematic diagram of a layout structure of a system on chip SOC and a DDR in the related art;

illustration of the drawings: a control circuit board 1; a system level chip SOC2 and a double-rate synchronous dynamic random access memory DDR3; a capacitance resistance element 4; the DDR relay circuit board 5.

Detailed Description

The embodiment of the utility model discloses DDR dilatation layout structure and electronic terminal for solve the technical problem that current system level chip SOC can't realize the dilatation of the synchronous dynamic random access memory DDR of double rate.

In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. It is to be understood that the disclosed embodiments are merely exemplary of the invention, and are not intended to limit the invention to the precise embodiments disclosed. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Example one

Referring to fig. 1, a DDR expansion layout structure provided in this embodiment includes:

a system on chip SOC2 and a DDR transfer circuit board 5;

the DDR switching circuit board 5 is electrically connected to the system-on-chip SOC2, and at least two double-rate synchronous dynamic random access memories DDR3 are electrically connected to the DDR switching circuit board 5.

In this embodiment, the DDR adapter circuit board 5 is electrically connected to the system on chip SOC2, and the DDR adapter circuit board 5 is electrically connected to at least two double-rate synchronous dynamic random access memories DDR3, so that the double-rate synchronous dynamic random access memories DDR3 on the system on chip SOC2 are expanded, and the requirements of different electronic terminals on the DDR capacity are met.

Specifically, when the electronic terminal needs a DDR with a larger capacity, the designer can directly add a larger number of DDR sdram DDR3 on the DDR adapter circuit board 5 to meet the requirement.

Further, the system on chip SOC2 in this embodiment has a first connection end for electrically connecting with the adapter circuit board 5, and the DDR adapter circuit board 5 is electrically connected to the first connection end.

It should be noted that, in the prior art, the system on chip SOC2 has a first connection end, and is connected to the DDR3 through the first connection end, and in this embodiment, the DDR transfer circuit board 5 is connected to the first connection end of the system on chip SOC2, so that a greater number of DDR3 are electrically connected to the system on chip SOC2 through the DDR transfer circuit board 5.

Further, the DDR adapter circuit board 5 in this embodiment has at least two second connection terminals for electrically connecting to the DDR3;

and each second connecting end is electrically connected with the double-rate synchronous dynamic random access memory DDR3.

It should be noted that, a designer may determine how many second connection terminals are designed on the DDR transfer circuit board 5 according to the design requirements of the electronic terminal, and each second connection terminal is electrically connected to a double data rate synchronous dynamic random access memory DDR3.

Specifically, at least two of the second connection ends are distributed on the DDR transfer circuit board 5 at a predetermined distance.

Further, the present example also includes a control circuit board 1 for carrying the system on chip SOC 2;

the system on chip SOC2 is electrically connected to the control circuit board 1.

Further, the control circuit board 1 in this embodiment is electrically connected to a plurality of capacitance and resistance sensing devices 4.

Specifically, the resistance-capacitance sensing element 4 in this embodiment includes a resistor, a capacitor, and an inductor.

Example two

Referring to fig. 1, an electronic terminal provided in this embodiment includes a DDR expansion layout structure in the first embodiment;

specifically, the electronic terminal may be a notebook computer, a smart phone, a smart watch, and the like, and taking the smart phone as an example, the smart phone includes a housing, a screen assembly assembled on the housing, and a DDR expansion layout structure fixed inside the housing.

In this embodiment, the DDR expansion layout structure is arranged on the electronic terminal, and the DDR adapter circuit board 5 is electrically connected to the system on chip SOC2, and the DDR adapter circuit board 5 is electrically connected to at least two DDR3, so that the DDR3 on the system on chip SOC2 is expanded, and the demands of different electronic terminals for DDR capacity are met.

It is right above the utility model provides a DDR dilatation overall arrangement and electronic terminal introduces in detail, to the general technical personnel in this field, the foundation the utility model discloses the thought of embodiment all has the change part on concrete implementation and application scope, to sum up, this specification content should not be understood as right the utility model discloses a restriction.

Claims

1. A DDR expands and arranges the structure, wherein include SOC of the system level chip and DDR switching circuit board;

2. The DDR expansion layout structure of claim 1, wherein the system on a chip SOC has a first connection end for electrically connecting to a DDR patch circuit board, and the DDR patch circuit board is electrically connected to the first connection end.

3. The DDR expansion layout structure of claim 2, wherein the DDR patch circuit board has at least two second connection terminals for electrically connecting to a DDR SDRAM;

and each second connecting end is electrically connected with the double-rate synchronous dynamic random access memory DDR.

4. The DDR expansion layout structure of claim 3, wherein at least two of the second connection terminals are distributed on the DDR patch circuit board at a predetermined distance.

5. The DDR capacity expansion layout structure of claim 1, comprising a control circuit board for carrying the system on chip SOC;

6. The DDR capacity expansion layout structure of claim 5, wherein a plurality of resistance-capacitance sensing components are further electrically connected to the control circuit board.

7. The DDR capacity expansion layout structure of claim 6, wherein the RC sensing components comprise a resistor, a capacitor and an inductor.

8. An electronic terminal, comprising the DDR expansion layout of any one of claims 1 to 7.