CN217520622U - Capacitive sensitive chip structure with vertically arranged polar plates - Google Patents
Capacitive sensitive chip structure with vertically arranged polar plates Download PDFInfo
- Publication number
- CN217520622U CN217520622U CN202220947205.0U CN202220947205U CN217520622U CN 217520622 U CN217520622 U CN 217520622U CN 202220947205 U CN202220947205 U CN 202220947205U CN 217520622 U CN217520622 U CN 217520622U
- Authority
- CN
- China
- Prior art keywords
- polar plate
- plate
- cavity
- polar
- pressure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Measuring Fluid Pressure (AREA)
Abstract
A vertical polar plate capacitance type sensitive chip structure belongs to the technical field of Micro Electro Mechanical Systems (MEMS), and particularly relates to a capacitance type sensitive chip structure. The utility model discloses be exactly to above-mentioned problem, provide a erect and put polar plate capacitanc sensitive chip structure. The utility model discloses a erect and put first polar plate (1) and put second polar plate (2) with the perpendicular relative of first polar plate (1), be first cavity (3) between its characterized in that first polar plate (1) and second polar plate (2).
Description
Technical Field
The utility model belongs to the technical field of micro-electro-mechanical systems (MEMS), especially, relate to a capacitanc pressure sensitive chip structure.
Background
MEMS, i.e., micro-electro-mechanical systems, belongs to the leading-edge field of multidisciplinary crossing and is listed as one of five subversive technologies affecting future manufacturing industries. With the development of the micro-electro-mechanical system technology, the MEMS pressure sensor has become an indispensable key device in various industries, and is widely applied to the fields of consumer electronics, automotive electronics, aerospace, petrochemical industry, biomedicine, national defense war industry, and the like. The key core in the MEMS pressure sensor is a pressure sensitive chip, most of the current mainstream technologies are piezoresistive type and capacitive type, and compared with the piezoresistive type, the capacitive type pressure sensitive chip has the advantages of high sensitivity, low power consumption, good temperature characteristic and the like, is more suitable for developing a high-precision pressure sensor, and is in a research hotspot position in the MEMS field for a long time.
At present, the existing capacitive MEMS pressure sensitive chip generally adopts a parallel plate capacitor structure, and mainly comprises a movable plate and a fixed plate, wherein the two plates are distributed vertically, when pressure acts on the movable plate, the pressure sensing plate senses pressure from the vertical direction, and the distance between the two plates is changed, so that the capacitance value is changed, and the pressure is measured by detecting the capacitance value. The parallel plate capacitance calculation formula is: c = (ε) 0 ε r A）/dIn the formula, epsilon 0 Is a fixed value for the vacuum dielectric constant;ε r the relative dielectric constant of the dielectric between the electrode plates;Ais the opposite area between the electrode plates;dthe pitch of the electrode plates. The output capacitance can be known from the capacitance calculation formulaCThe positive electrode plates are in direct proportion to the positive area between the electrode plates, the initial capacitance value of the sensitive chip is obtained, the areas of the two electrode plates cannot be too small, the electrode plates are distributed up and down, the upper electrode plate and the lower electrode plate are divided, and the reduction degree of the area size of the chip is limited.
SUMMERY OF THE UTILITY MODEL
The utility model discloses be exactly to above-mentioned problem, provide a erect and put polar plate capacitanc pressure sensitive chip structure.
In order to achieve the above object, the present invention adopts the following technical solution, the present invention includes a vertical first polar plate (1) and a vertical second polar plate (2) opposite to the first polar plate (1), wherein a first cavity (3) is disposed between the first polar plate (1) and the second polar plate (2). (as shown in FIG. 1)
As a preferred scheme, first cavity (3) top sets up apron (4), and first cavity (3) are seal chamber. The first cavity (3) is not sealed, and can be used for manufacturing silicon microphones and accelerometers.
As another preferred scheme, the periphery of the side wall of the electrodeless board of the first cavity (3) and the bottom of the first cavity (3) are substrates (5). (as shown in FIG. 2)
As another preferred scheme, the first polar plate (1) and/or the second polar plate (2) of the utility model are/is provided with a medium layer (6).
As another preferred scheme, first polar plate (1) keeps away from second polar plate (2) side and links to each other with substrate (5) (namely first polar plate (1) is the unmovable polar plate, and second polar plate (2) direct pressure sensing is movable), and electric capacity C that forms between first polar plate (1) and second polar plate (2) works between second polar plate (2) and first polar plate (1) non-contact region (as shown in fig. 3).
As another preferred scheme, first polar plate (1) is kept away from second polar plate (2) side and is linked to each other with substrate (5) (namely first polar plate (1) is the unmovable polar plate, and second polar plate (2) direct pressure sensing is movable), produces deformation and first polar plate (1) contact after second polar plate (2) pressure sensing, along with the area of contact increase of pressure increase first polar plate (1) and second polar plate (2). (as shown in fig. 4).
As another preferred scheme, two polar plates all are that the pressure sensing is movable, produce deformation behind second polar plate (2) pressure sensing and do not contact with first polar plate (1). The second polar plate (2) is deformed after being sensed and is contacted with the first polar plate (1), and the contact area between the first polar plate (1) and the second polar plate (2) is increased along with the increase of the pressure. (as shown in fig. 5).
As another preferred scheme, the utility model discloses set up support (8) or fill gas (7) in first cavity (3) on first polar plate (1). (as shown in fig. 6). If the first polar plate (1) is provided with the dielectric layer (6), the support (8) is arranged on the dielectric layer (6).
As another preferred scheme, the side of the first polar plate (1) far away from the second polar plate (2) is provided with a second cavity (9);
a capacitor C formed between the first polar plate (1) and the second polar plate (2) works between the second polar plate (2) and the non-contact area of the first polar plate (1); or the second polar plate (2) is deformed to be in contact with the first polar plate (1) after sensing pressure, the contact area between the second polar plate (2) and the first polar plate (1) is increased along with the increase of the pressure, and meanwhile, the first polar plate (1) is deformed towards the inside of the second cavity (9). (as shown in FIG. 7)
As another preferable scheme, a third polar plate (10) is arranged on the side, away from the first polar plate (1), of the second cavity (9);
the second polar plate (2) is deformed after being sensed and is not contacted with the first polar plate (1); or the second polar plate (2) is deformed to contact with the first polar plate (1) after being subjected to pressure sensing, the contact area between the second polar plate (2) and the first polar plate (1) is increased along with the increase of the pressure, and meanwhile, the first polar plate (1) is deformed towards the direction of the third polar plate (10); or the second cavity (9) is communicated with the outside (a through hole (11) can be formed in the cover plate (4)), the first polar plate (1) and the second polar plate (2) form a variable capacitor, and the first polar plate (1) and the third polar plate (10) form a non-variable capacitor or a variable capacitor (when the first polar plate (1) is deformed under pressure). (as shown in FIG. 8 and FIG. 9)
As another preferred scheme, the utility model discloses first polar plate (1) leads to the first polarity signal of telecommunication, and second polar plate (2) and third polar plate (10) lead to the signal of telecommunication opposite with first polarity signal.
As another preferred scheme, the utility model discloses second cavity (9) periphery is substrate (5), and second cavity (9) top is apron (4), and second cavity (9) are sealed cavity.
As another preferable scheme, a third cavity (13) is arranged on the side of the third polar plate (10) far away from the first polar plate (1), and a fourth polar plate (12) is arranged on the side of the third cavity (13) far away from the third polar plate (10);
the second polar plate (2) and the first polar plate (1) are deformed simultaneously after sensing pressure, and work in a non-contact area to form a variable capacitor; or the second polar plate (2) and the first polar plate (1) are deformed and contacted simultaneously after pressure sensing, the contact area of the second polar plate (2) and the first polar plate (1) is increased along with the increase of the pressure, and the third polar plate (10) can directly sense the pressure and move; or the third polar plate (10) is not subjected to pressure sensing (the third polar plate (10) with a thick film is arranged to realize the pressure sensing, the third polar plate (10) and the fourth polar plate (12) form an invariable capacitor, the second polar plate (2) is directly subjected to pressure sensing and can move, the first polar plate (1) is directly subjected to pressure sensing and can move, and the first polar plate (1) and the second polar plate (2) form a variable capacitor; or the third cavity (13) and the second cavity (9) are communicated with the outside (a through hole (14) and a through hole (11) can be formed in the cover plate (4)), the second polar plate (2) is directly pressure-sensitive and movable, the first polar plate (1) and the second polar plate (2) form a variable capacitor, the third polar plate (10) and the fourth polar plate (12) are immovable, and the third polar plate (10) and the fourth polar plate (12) form an invariable capacitor. (as shown in FIGS. 10 and 11)
As another preferred scheme, the utility model third cavity (13) periphery is substrate (5), and third cavity (13) top is apron (4), and third cavity (13) are sealed cavity.
As another preferred scheme, the third polar plate (10) and/or the fourth polar plate (12) of the invention are/is provided with a medium layer (6).
In addition, first polar plate (1), second polar plate (2), third polar plate (10), fourth polar plate (12) are connected with external circuit through pressure welding point and metal lead or pressure welding point respectively, and the place that polar plate and substrate and apron link to each other all has insulating medium layer (this is current conventional structure, prevents the short circuit between each part). Each structure of the present invention can be used as a basic unit to form a capacitor array on the same substrate by repeated manufacturing.
The utility model has the advantages of simple structure and convenient operation.
The utility model discloses the setting is put vertically to the plate electrode, when pressure acts on movable polar plate, direction pressure sensing about the pressure sensing polar plate follow cavity side, and the area of chip can reach extremely optimization, reduces substantially the area size of chip.
Drawings
The present invention will be further described with reference to the accompanying drawings and the following detailed description. The scope of protection of the present invention is not limited to the following description.
Fig. 1 is a schematic structural diagram of the present invention. In fig. 1, the surface enclosed by AEHD is a first polar plate 1, the surface enclosed by ABCD is a cover plate 4, and the surface enclosed by BFGC is a second polar plate 2.
Fig. 2 is a schematic structural section of the present invention.
Fig. 3 is a schematic structural sectional view of embodiment 1 of the present invention.
Fig. 4 is a schematic structural sectional view of embodiment 2 of the present invention.
Fig. 5 is a schematic structural sectional view of embodiment 3 of the present invention.
Fig. 6 is a schematic structural sectional view of embodiment 4 of the present invention.
Fig. 7 is a schematic structural sectional view of embodiment 5 of the present invention.
Fig. 8 is a schematic structural sectional view of embodiment 6 of the present invention.
Fig. 9 is a schematic structural sectional view of embodiment 7 of the present invention.
Fig. 10 is a schematic structural sectional view of embodiment 8 of the present invention.
Fig. 11 is a schematic structural sectional view of embodiment 9 of the present invention.
Fig. 12 is a schematic cross-sectional view of a capacitor array structure according to embodiment 3 of the present invention.
Fig. 13 is a graph of simulation output characteristics according to embodiment 3 of the present invention.
Description of the reference numerals:
1. the plasma display device comprises a first polar plate, 2 a second polar plate, 3 a first cavity, 4 a cover plate, 5 a substrate, 6 a dielectric layer, 7 gas, 8 a support, 9 a second cavity, 10 a third polar plate, 11 a through hole, 12 a fourth polar plate, 13 a third cavity and 14 a through hole.
Detailed Description
As shown in the figure, the utility model discloses a erect and put first polar plate (1) and with first polar plate (1) relative perpendicular second polar plate (2) of putting, be first cavity (3) between first polar plate (1) and second polar plate (2).
As shown in fig. 1, a first cavity (3) is disposed on a substrate (5), a cover plate (4) is disposed on the top of the first cavity (3), a first polar plate (1) and a second polar plate (2) are disposed on two opposite sidewalls of the first cavity (3), and the movable polar plate is deformed under pressure to change a capacitance between the first polar plate (1) and the second polar plate (2), so as to measure a pressure value.
As shown in fig. 2, the structural section schematic diagram of the present invention sets up a first cavity (3) on the substrate (5), sets up the cover plate (4) at the top of the first cavity (3), sets up the first polar plate (1) and the second polar plate (2) respectively at two opposite side walls of the first cavity (3), and the movable polar plate is deformed under pressure to change the capacitance between the first polar plate (1) and the second polar plate (2), thereby measuring the pressure value.
As shown in fig. 3, the immovable polar plate is set as a first polar plate (1), the first polar plate (1) is connected with the substrate (5), a second polar plate (2) is arranged on a side wall of the first cavity (3) in the direction opposite to the first polar plate (1) of the first cavity (3), the second polar plate (2) is directly pressure-sensitive and movable, a cover plate (4) is arranged on the top of the first cavity (3), the first cavity (3) is sealed, the first polar plate (1) and the second polar plate (2) form a capacitor C, the capacitor C works between the second polar plate (2) and the first polar plate (1) in a non-contact area, when the second polar plate (2) senses pressure, the second polar plate (2) is deformed under pressure, the distance between the first polar plate (1) and the second polar plate (2) changes, the capacitor C changes accordingly, and the capacitor C changes along with the pressure-sensitive change of the second polar plate (2), so as to measure the pressure value. The utility model discloses an electric capacity output characteristic curve is good, and the precision is high moreover, and sensitivity is high, and temperature drift is little, more is fit for the pressure measurement of high accuracy small-scale range, and the area of chip can reach extremely optimization moreover, under the condition of equal electric capacity variation, chip area more than 90% can be saved to the top.
As shown in fig. 4, the first electrode plate (1) is set to be an immovable electrode plate, the first electrode plate (1) is connected with the substrate (5), a dielectric layer (6) is arranged on one side wall of the first cavity (3) on the first electrode plate (1), the side wall of the first cavity (3) opposite to the first electrode plate (1) is provided with the second electrode plate (2), the second electrode plate (2) is directly pressure-sensitive and movable, the top of the first cavity (3) is provided with the cover plate (4), and the first cavity (3) is sealed. Produce deformation and dielectric layer (6) contact on the first polar plate (1) after second polar plate (2) pressure sensing, along with pressure increase second polar plate (2) and dielectric layer (6) area of contact increase, at this moment output capacitance value can present similar linear relation with pressure variation to measure the pressure value, the utility model discloses a capacitance output characteristic curve is good, and the precision is high moreover, and sensitivity is high, and the temperature drift is little, more is fit for the pressure measurement of high accuracy small-scale range, and the area of chip can reach extremely optimization moreover, under the condition of equal capacitance variation, can save chip area more than 90% at most.
As shown in fig. 5, the first electrode plate (1) is disposed on one side wall of the first cavity (3), the first electrode plate (1) is connected to the substrate (5), the first electrode plate (1) is directly pressure-sensitive and movable, the side wall of the first cavity (3) opposite to the first electrode plate (1) is disposed with the second electrode plate (2), the top of the first cavity (3) is disposed with the cover plate (4), the first cavity (3) is sealed, the second electrode plate (2) is directly pressure-sensitive and movable, the first electrode plate (1) and the second electrode plate (2) deform after pressure-sensitive, the capacitance C formed by the first electrode plate (1) and the second electrode plate (2) changes along with the deformation of the first electrode plate (1) and the second electrode plate (2), thereby measuring the pressure value, and the variation of the capacitance C is larger. The sizes of the first polar plate (1) and the second polar plate (2) can be set to be 116um high, 650um long and 3um thick, a capacitance pressure curve graph is obtained through software simulation, as shown in fig. 13, the pressure range is 0-130kp, the corresponding capacitance variation is 2.1pf, and the high sensitivity is achieved. The utility model discloses an electric capacity output characteristic is good, has that sensitivity is high, the linearity is good, linear range scope is big, temperature drift is little, more be fit for the pressure measurement of high accuracy small-scale range, and the overload capacity is strong, and the area of chip can reach extremely optimization moreover, under the condition of equal electric capacity variation, chip area more than 90% can be saved to the top.
As shown in fig. 6, the first electrode plate (1) is an immovable electrode plate, the first electrode plate (1) is connected with the substrate (5), a dielectric layer (6) is arranged on one side wall of the first cavity (3) on the first electrode plate (1), the second electrode plate (2) is arranged on the side wall of the first cavity (3) opposite to the first electrode plate (1), the second electrode plate (2) is directly pressure-sensitive and movable, the cover plate (4) is arranged on the top of the first cavity (3), and the first cavity (3) is sealed. A support (8) is arranged on the dielectric layer, the first cavity (3) is filled with gas (7), the second polar plate (2) is deformed after being sensed by pressure and is contacted with the dielectric layer (6) on the first polar plate (1), the contact area of the second polar plate (2) and the dielectric layer (6) is increased along with the increase of the pressure, the gas (7) in the first cavity (3) is sealed to jointly act on the outward tension of the second polar plate (2) and the support (8) on the first polar plate (1) at the moment, so that the second polar plate (2) is not tightly attached to the first polar plate (1), the adhesive force between the two polar plates is reduced, when the second polar plate (2) is pressed and reduced, the pressure of the gas (7) in the sealed first cavity (3) forces the second polar plate (2) to rapidly reduce deformation, thereby reducing hysteresis characteristics, and the output capacitance value and pressure change show a similar linear relation, thereby measuring the pressure value. The utility model discloses an electric capacity output characteristic is good, and the precision is high moreover, and sensitivity is high, and temperature drift is little, and the area of chip can reach extremely optimization moreover, under the condition of equal electric capacity variation, chip area more than 90% can be saved to the highest.
As shown in figure 7, the two polar plates of the utility model are both pressure-sensitive and movable, the first polar plate (1) is arranged on one side wall of the first cavity (3), the second cavity (9) is arranged on the other side opposite to the first polar plate (1) and opposite to the first cavity (3), the first polar plate (1) is connected with the substrate (5), the second polar plate (2) is arranged on the side wall of the first cavity (3) opposite to the first polar plate (1), the cover plate (4) is arranged on the top of the second cavity (9) and the first cavity (3), the first cavity (3) is sealed, the second cavity (9) is sealed, the second polar plate (2) is directly pressure-sensitive and movable, the dielectric layer (6) is arranged on the first polar plate (1), the second polar plate (2) is deformed to contact with the first polar plate (1) after pressure sensing, the contact area between the second polar plate (2) and the first polar plate (1) is increased along with the increase of pressure, meanwhile, the first pole plate (1) deforms towards the inside of the second cavity (9). The utility model discloses a capacitance output characteristic curve is good, and the precision is high moreover, and sensitivity is high, and temperature drift is little, and it is stronger to overload, and the area of chip can reach utmost optimization moreover, and the area is littleer.
As shown in fig. 8, the first plate (1) is disposed on one side wall of the first cavity (3), the second cavity (9) is disposed on the other side of the first plate (1) opposite to the first cavity (3) and opposite to the first cavity (3), the first plate (1) is connected to the substrate (5), the second plate (2) is disposed on the side wall of the first cavity (3) opposite to the first plate (1), the cover plate (4) is disposed on the top of the second cavity (9) and the first cavity (3), the third plate (10) is disposed on the side wall of the second cavity (9) opposite to the first plate (1), the first cavity (3) is sealed, the second cavity (9) is sealed, the second plate (2) is directly pressure-sensitive and movable, and the capacitor C1 formed between the first plate (1) and the second plate (2) works in a non-contact region between the second plate (2) and the first plate (1). First polar plate (1) leads to first polarity signal of telecommunication, second polar plate (2) and third polar plate (10) lead to the signal of telecommunication opposite with first polarity signal, first polar plate (1) forms variable capacitance C1 with second polar plate (2), first polar plate (1) forms invariable capacitance C2 with third polar plate (10), electric capacity C1 and C2 combination form differential capacitance, shield common mode signal interference, the interference killing feature is stronger, the capacitance output characteristic curve is good, and the precision is high, sensitivity is high, the temperature drift is little, overload intensity, and the area of chip can reach extremely optimization, the area is littleer.
As shown in fig. 9, the first plate (1) is disposed on one side wall of the first cavity (3), the second cavity (9) is disposed on the other side opposite to the first plate (1) and opposite to the first cavity (3), the first plate (1) is connected to the substrate (5), the second plate (2) is disposed on the side wall of the first cavity (3) opposite to the first plate (1), the cover plate (4) is disposed on the top of the second cavity (9) and the first cavity (3), the third plate (10) is disposed on the side wall of the second cavity (9) opposite to the first plate (1), the through hole (11) is disposed on the top of the second cavity (9) of the cover plate (4), the first cavity (3) is sealed, the first plate (1) and the second plate (2) sense pressure and move simultaneously, the first plate (1) is connected to the first polarity electrical signal, the second plate (2) and the third plate (10) are connected to the second polarity electrical signal opposite to the first polarity signal, the pressure sensing of the first polar plate (1) and the second polar plate (2) simultaneously generates polar plate deformation, the first polar plate (1) and the second polar plate (2) form a variable capacitor C1, the first polar plate (1) and the third polar plate (10) form a variable capacitor C2, when the pressure is increased, the capacitor C1 is increased, the capacitor C2 is reduced, the capacitors C1 and C2 are combined to form a differential capacitor C3, the variable quantity of the capacitor C3 is equal to the sum of the variable quantity of the capacitor C1 and the variable quantity of the capacitor C2, the variable quantity of the output capacitor C3 is larger, the precision is higher, the sensitivity is higher, common-mode signal interference is shielded, the anti-interference capability is stronger, the capacitance output characteristic curve is good, the temperature drift is small, the overload is strong, and the area of a chip can be optimized extremely and the area is smaller.
As shown in FIG. 10, a first plate (1) is arranged on one side wall of a first cavity (3), a second cavity (9) is arranged on the other side opposite to the first plate (1) and opposite to the first cavity (3), a second plate (2) is arranged on the side wall of the first cavity (3) opposite to the first plate (1), a third plate (10) is arranged on the side wall of the second cavity (9) opposite to the first plate (1), a third cavity (13) is arranged on the other side opposite to the third plate (10) and opposite to the second cavity (9), a fourth plate (12) is arranged on the side wall of the third cavity (13) opposite to the third plate (10), a cover plate (4) is arranged on the top of the first cavity (3), the top of the second cavity (9) and the top of the third cavity (13), a through hole (11) is arranged on the top of the second cavity (9) of the cover plate (4), and a dielectric layer (6) is arranged on the first plate (1) and the fourth plate (12), the first polar plate (1), the second polar plate (2), the third polar plate (10) and the fourth polar plate (12) are all connected with the substrate (5), the first cavity (3) is sealed, the third cavity (13) is sealed, the first polar plate (1), the second polar plate (2) and the third polar plate (10) sense pressure and move simultaneously, the first polar plate (1) and the fourth polar plate (12) are communicated with a first polarity electric signal, the second polar plate (2) and the third polar plate (10) are communicated with a second polarity electric signal opposite to the first polarity signal, the first polar plate (1), the second polar plate (2) and the third polar plate (10) sense pressure and deform simultaneously, the first polar plate (1) and the second polar plate (2) form a variable capacitor C1, the first polar plate (1) and the third polar plate (10) form a variable capacitor C2, the third polar plate (10) and the fourth polar plate (12) form a variable capacitor C3, when the pressure is increased, the first polar plate (1) and the second polar plate (2) are deformed in an increasing mode towards the inner direction of the first cavity (3), the distance between the first polar plate (1) and the second polar plate (2) is reduced, the capacitance C1 is increased, the third polar plate (10) is deformed in an increasing mode towards the direction of the fourth polar plate (12) in the third cavity (13) along with the increase of pressure, the distance between the first polar plate (1) and the third polar plate (10) is increased, the capacitance C2 is reduced, at the moment, the distance between the third polar plate (10) and the fourth polar plate (12) is reduced, and the capacitance C3 is increased; when the pressure is reduced, the first pole plate (1) and the second pole plate (2) are deformed in an increasing way towards the outside of the first cavity (3), the distance between the first pole plate (1) and the second pole plate (2) is increased, the capacitor C1 is reduced, the third pole plate (10) is deformed in an increasing way towards the outside of the third cavity (13) and the opposite direction of the fourth pole plate (12) along with the reduction of the pressure, the distance between the first pole plate (1) and the third pole plate (10) is increased, the capacitor C2 is increased, at the moment, the distance between the third pole plate (10) and the fourth pole plate (12) is increased, the capacitor C3 is reduced, the capacitors C1 and C2 are combined to form a differential capacitor C4, the capacitors C3 and C2 are combined to form a differential capacitor C5, the variation of the output capacitor C6 is equal to the sum of the capacitors C4 and C5, the output capacitor is larger, the accuracy is higher, the sensitivity is higher, the common-mode signal interference can be shielded, and the capacity is stronger in interference resistance, the capacitance output characteristic curve is good, the temperature drift is small, the overload is strong, the area of the chip can be optimized extremely, and the area is smaller.
As shown in fig. 11, the first polar plate (1) is disposed on one side wall of the first cavity (3), the second cavity (9) is disposed on the other side opposite to the first polar plate (1) and opposite to the first cavity (3), the second polar plate (2) is disposed on the side wall of the first cavity (3) opposite to the first polar plate (1), the third polar plate (10) is disposed on the side wall of the second cavity (9) opposite to the first polar plate (1), the third cavity (13) is disposed on the other side opposite to the third polar plate (10) and opposite to the second cavity (9), the fourth polar plate (12) is disposed on the side wall of the third cavity (13) opposite to the third polar plate (10), the cover plate (4) is disposed on the top of the first cavity (3), the second cavity (9) and the third cavity (13), the through hole (11) is disposed on the top of the second cavity (9) of the cover plate (4), the through hole (14) is disposed on the top of the second cavity (9) of the cover plate (4), the first polar plate (1), the second polar plate (2), the third polar plate (10) and the fourth polar plate (12) are all connected with the substrate (5), the first cavity (3) is sealed, the first polar plate (1), the second polar plate (2) and the pressure sensing can move simultaneously, the third polar plate (10) is a fixed polar plate, the first polar plate (1) and the fourth polar plate (12) are communicated with a first polarity electric signal, the second polar plate (2) and the third polar plate (10) are communicated with a second polarity electric signal opposite to the first polarity signal, the first polar plate (1) and the second polar plate (2) and the pressure sensing can deform simultaneously, the first polar plate (1) and the second polar plate (2) form a variable capacitor C1, the first polar plate (1) and the third polar plate (10) form a variable capacitor C2, the third polar plate (10) and the fourth polar plate (12) form a constant capacitor C3, when the pressure increases, the first polar plate (1) and the second polar plate (2) deform towards the inner part of the first cavity (3), the distance between the first polar plate (1) and the second polar plate (2) is reduced, the capacitor C1 is increased, the distance between the first polar plate (1) and the third polar plate (10) is increased, the capacitor C2 is reduced, the pressure of the second cavity (9) is the same as that of the third cavity (13), the third polar plate (10) cannot deform along with the change of pressure, the capacitor C3 is unchanged, the capacitor C1 and the capacitor C3 are combined to form a differential capacitor C4, the capacitor C2 and the capacitor C3 are combined to form a differential capacitor C5, the variation of the output capacitor C6 is equal to the sum of the capacitor C4 and the capacitor C5, the variation of the output capacitor is larger, the precision is higher, the sensitivity is higher, the common-mode signal interference can be shielded, the anti-interference capability is higher, the output characteristic curve of the capacitor is good, the temperature drift is small, the overload is strong, the area of the chip can be optimized, and the area is smaller.
As shown in fig. 12, 5 basic capacitors of example 3 were repeatedly fabricated on the substrate (5).
The manufacturing method based on SOI silicon and bonding process comprises the following steps:
cleaning an SOI silicon wafer;
thinning an SOI silicon chip, and thinning the upper layer silicon to the thickness required by the polar plate;
c. etching a first polar plate (1) and a second polar plate (2);
d. oxidizing to generate silicon dioxide, and connecting the polar plate and the substrate through the silicon dioxide;
e. bonding another silicon wafer (namely a cover plate (4)) on the tops of the polar plate and the substrate;
f. thinning the silicon slice bonded to the uppermost layer to the thickness required by the cover plate (4);
g. depositing silicon dioxide;
h. etching a lead hole;
i. depositing an aluminum lead;
j. a passivation layer (which may be silicon dioxide, silicon nitride, etc.) is deposited.
The utility model provides a erect and put polar plate capacitanc pressure sensitive chip can be used to consumer electronics, automotive electronics, industry observing and controlling, medical electronics, aerospace and national defense military project etc. in a plurality of fields absolute pressure and the measurement of differential pressure. The utility model discloses pressure sensitive chip has that sensitivity is high, the linearity is good, linear range is big, the temperature drift is little, the overload capacity is strong, manufacturing process and integrated circuit technology advantage such as compatible, is particularly suitable for developing high accuracy pressure sensor.
The utility model discloses can be applied to pressure sensor, silicon microphone, accelerometer, flowmeter etc..
It should be understood that the above detailed description of the present invention is only for illustrating the present invention and is not limited by the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention can still be modified or equivalently replaced to achieve the same technical effects; as long as satisfy the operation needs, all be in the protection scope of the utility model.
Claims (4)
1. The vertical polar plate capacitive sensitive chip structure comprises a vertical first polar plate (1) and a vertical second polar plate (2) opposite to the first polar plate (1), and is characterized in that a first cavity (3) is arranged between the first polar plate (1) and the second polar plate (2);
the periphery of the side wall of the electrodeless board of the first cavity (3) and the bottom of the first cavity (3) are substrates (5);
or the side of the first polar plate (1) far away from the second polar plate (2) is connected with the substrate (5);
or the first polar plate (1) is provided with a support (8) or the first cavity (3) is filled with gas (7);
or a second cavity (9) is arranged on the side, far away from the second polar plate (2), of the first polar plate (1);
or a third polar plate (10) is arranged on the side, far away from the first polar plate (1), of the second cavity (9);
or a third cavity (13) is arranged on the side, far away from the first polar plate (1), of the third polar plate (10), and a fourth polar plate (12) is arranged on the side, far away from the third polar plate (10), of the third cavity (13).
2. The vertical plate capacitive sensor chip structure according to claim 1, wherein a cover plate (4) is disposed on the top of the first cavity (3), and the first cavity (3) is a sealed cavity.
3. The vertical plate capacitive sensor chip structure according to claim 1, wherein the periphery of the second cavity (9) is provided with the substrate (5), and the top of the second cavity (9) is provided with the cover plate (4);
the periphery of the third cavity (13) is provided with a substrate (5), and the top of the third cavity (13) is provided with a cover plate (4).
4. The vertically-arranged-plate capacitive sensor chip structure according to claim 1, wherein a dielectric layer (6) is arranged on the first plate (1) and/or the second plate (2);
and a dielectric layer (6) is arranged on the third polar plate (10) and/or the fourth polar plate (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220947205.0U CN217520622U (en) | 2022-04-23 | 2022-04-23 | Capacitive sensitive chip structure with vertically arranged polar plates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220947205.0U CN217520622U (en) | 2022-04-23 | 2022-04-23 | Capacitive sensitive chip structure with vertically arranged polar plates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217520622U true CN217520622U (en) | 2022-09-30 |
Family
ID=83372625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220947205.0U Active CN217520622U (en) | 2022-04-23 | 2022-04-23 | Capacitive sensitive chip structure with vertically arranged polar plates |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217520622U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115655534A (en) * | 2022-10-31 | 2023-01-31 | 歌尔微电子股份有限公司 | Pressure sensor and method for manufacturing pressure sensor |
-
2022
- 2022-04-23 CN CN202220947205.0U patent/CN217520622U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115655534A (en) * | 2022-10-31 | 2023-01-31 | 歌尔微电子股份有限公司 | Pressure sensor and method for manufacturing pressure sensor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3114570B2 (en) | Capacitive pressure sensor | |
| US7296476B2 (en) | Microelectromechanical system pressure sensor and method for making and using | |
| KR100404904B1 (en) | A capacitive differential pressure sensor and method for manufacturing thereof | |
| CN111982383B (en) | Differential pressure contact type MEMS capacitance film vacuum gauge | |
| EP0720731A1 (en) | Suspended diaphragm pressure sensor | |
| CN103983395B (en) | A kind of micropressure sensor and preparation thereof and detection method | |
| CN112964417B (en) | Capacitive pressure sensitive chip with double movable polar plates | |
| CN217520622U (en) | Capacitive sensitive chip structure with vertically arranged polar plates | |
| CN112763129A (en) | Absolute pressure contact type MEMS capacitance film vacuum gauge | |
| CN117268600A (en) | MEMS pressure sensor chip and preparation method thereof | |
| WO2024041638A1 (en) | Differential-capacitance-type mems pressure sensor and manufacturing method therefor | |
| CN112857628B (en) | MEMS capacitive pressure sensor chip and manufacturing process thereof | |
| CN213364087U (en) | Capacitive MEMS pressure sensor applied to electronic terminal product | |
| CN116973010A (en) | Vertical polar plate capacitance type sensitive chip structure | |
| JP4540775B2 (en) | Servo capacitive vacuum sensor | |
| CN216246919U (en) | Capacitive chip structure | |
| CN113353883A (en) | MEMS pressure sensor based on phase detection principle and preparation method | |
| CN217738499U (en) | Embedded capacitive sensitive chip | |
| CN218297446U (en) | Dielectric layer embedded type capacitive pressure sensitive chip | |
| CN221198728U (en) | Capacitive chip structure | |
| CN217110956U (en) | Suspension type capacitance sensitive chip | |
| CN221571714U (en) | Groove type capacitor chip structure | |
| CN114061823B (en) | Temperature self-compensating high-sensitivity pressure sensor array and preparation method thereof | |
| CN112284606B (en) | T-shaped cross beam cross island membrane pressure sensor chip and preparation method thereof | |
| CN110568220B (en) | Anti-interference overload-resistant MEMS accelerometer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |