CN217443444U - Voltage test board circuit - Google Patents
Voltage test board circuit Download PDFInfo
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- CN217443444U CN217443444U CN202220643900.8U CN202220643900U CN217443444U CN 217443444 U CN217443444 U CN 217443444U CN 202220643900 U CN202220643900 U CN 202220643900U CN 217443444 U CN217443444 U CN 217443444U
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Abstract
The utility model relates to a voltage testing board circuit, including resistance R1, R2, R3, R4, R5, R6, R7, R8, electric capacity C1, C2, diode D1, D2, triode Q1, Q2, chip U, zener diode D3, field effect transistor NMOS1, NMOS2, triode Q1, Q2 can change self conduction or cut-off state according to the state of voltage, thereby draw down or compensate to the signal of telecommunication of chip U output, thereby play the effect of protection to chip U, and simultaneously, field effect transistor NMOS1, NMOS2 can improve protection circuit's withstand voltage value, can protect on the basis that voltage testing board circuit can not destroy, reduce input impedance, can reduce the influence to voltage testing board circuit like this.
Description
Technical Field
The utility model relates to a voltage test's technical field, concretely relates to voltage testing board circuit.
Background
The voltage testing board has the opportunity of generating overvoltage or undervoltage in the process of testing the voltage of the components, and the components on the testing board are easily damaged.
Therefore, further improvements are needed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the not enough of above-mentioned prior art existence, and provide a voltage testing board circuit, aim at solving one of the above-mentioned technical problem among the prior art to a certain extent at least.
The purpose of the utility model is realized like this:
a voltage test board circuit comprises resistors R1, R2, R3, R4, R5, R6, R7 and R8, capacitors C1 and C2, diodes D1 and D2, triodes Q1 and Q2, a chip U, a zener diode D3, field effect transistors NMOS1 and NMOS 2.
The left end of the resistor R1 is electrically connected with the signal input end, the right end of the resistor R1 is respectively electrically connected with the upper end of the capacitor C1, the upper end of the resistor R2, the cathodes of the diodes D1 and D2, the anode of the diode D1 is electrically connected with the left end of the resistor R3, the right end of the resistor R3 is respectively electrically connected with the upper end of the resistor R4, the base of the triode Q1 and the collector of the triode Q2, the collector of the triode Q1 is electrically connected with the left end of the resistor R7, and the right end of the resistor R7 is respectively electrically connected with the upper end of the capacitor C2 and the pin 2 of the chip U.
The positive electrode of the diode D2 is electrically connected with the left end of the resistor R5, and the right end of the resistor R5 is electrically connected with the upper end of the resistor R6 and the base of the triode Q2 respectively.
The lower ends of the capacitors C1 and C2, the lower ends of the resistors R2, R4 and R6 and the emitters of the triodes Q1 and Q2 are grounded respectively.
The power supply circuit is characterized in that a pin 1 of the chip U is electrically connected with a driving power supply through a resistor R8, a pin 6 of the chip U is electrically connected with gates of field effect transistors NMOS1 and NMOS2 respectively, sources of 4-pin field effect transistors NMOS1 and NMOS2 of the chip U are electrically connected, drains of the field effect transistors NMOS1 and NMOS2 are electrically connected with a signal output end respectively, a cathode of a voltage stabilizing diode D3 is electrically connected with the pin 6 of the chip U, and an anode of the voltage stabilizing diode D3 is electrically connected with the pin 4 of the chip U.
The utility model has the advantages that:
triode Q1, Q2 can change the state of switching on or cutting off of self according to the state of voltage to drawing low or the compensation to the signal of telecommunication of chip U output, thereby play the effect of protection to chip U, and simultaneously, field effect transistor NMOS1, NMOS2 can improve protection circuit's withstand voltage value, can protect on the basis that the voltage testing board circuit can not destroy, reduce input impedance, can reduce the influence to the voltage testing board circuit like this.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, or may be learned by practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
Detailed Description
The present invention will be further described with reference to the accompanying drawings and examples.
Referring to fig. 1, the voltage testing board circuit comprises resistors R1, R2, R3, R4, R5, R6, R7 and R8, capacitors C1 and C2, diodes D1 and D2, triodes Q1 and Q2, a chip U, a zener diode D3, field effect transistors NMOS1 and NMOS 2.
The chip U in this embodiment may preferably be a MAX1452 signal linear conversion chip.
The left end of the resistor R1 is electrically connected with the signal input end, the right end of the resistor R1 is respectively electrically connected with the upper end of the capacitor C1, the upper end of the resistor R2, the diode D1 and the negative electrode of the D2 are electrically connected, the positive electrode of the diode D1 is electrically connected with the left end of the resistor R3, the right end of the resistor R3 is respectively electrically connected with the upper end of the resistor R4, the base electrode of the triode Q1 and the collecting electrode of the triode Q2 are electrically connected, the collecting electrode of the triode Q1 is electrically connected with the left end of the resistor R7, the right end of the resistor R7 is respectively electrically connected with the upper end of the capacitor C2 and the pin 2 of the chip U.
The positive pole of diode D2 and resistance R5's left end electric connection, resistance R5's right-hand member respectively with resistance R6's upper end, triode Q2's base electric connection.
The lower ends of the capacitors C1 and C2, the lower ends of the resistors R2, R4 and R6 and the emitters of the triodes Q1 and Q2 are grounded respectively.
The pin 1 of the chip U is electrically connected with a driving power supply through a resistor R8, the pin 6 of the chip U is electrically connected with the grids of field effect transistors NMOS1 and NMOS2 respectively, the sources of the field effect transistors NMOS1 and NMOS2 of the pin 4 of the chip U are electrically connected, the drains of the field effect transistors NMOS1 and NMOS2 are electrically connected with a signal output end respectively, the cathode of a voltage stabilizing diode D3 is electrically connected with the pin 6 of the chip U, and the anode of the voltage stabilizing diode D3 is electrically connected with the pin 4 of the chip U.
When the voltage input by the signal input end is normal, the triode Q1 is conducted and outputs low level to the pin 2 of the chip U; when the voltage input by the signal input end is undervoltage, the triode Q1 is in a cut-off state and outputs a high level to the pin 2 of the chip U; when the voltage input by the signal input end is overvoltage, although the base electrode of the triode Q1 is electrified, the triode Q2 is conducted at the moment, the base electrode of the triode Q1 is pulled down, the triode Q2 is turned off, and high level is output to the pin 2 of the chip U, so that the effect of protecting the chip U can be achieved after overvoltage and undervoltage appear in the power voltage.
When the current passing through the chip U is relatively small, the regulated voltage on the regulator diode D3 is relatively small, so that the current limiting capability of the field effect transistor NMOS1 and NMOS2 is improved, and when the current passing through the chip U is relatively large, the regulated voltage of the regulator diode D3 is relatively large, so that the current conducting capability of the field effect transistor NMOS1 and NMOS2 is improved.
The above embodiments are merely preferred embodiments of the present invention, and other embodiments are also possible. Those skilled in the art can make equivalent variations or substitutions without departing from the spirit of the invention, and such equivalent variations or substitutions are included in the scope of the claims of the present application.
Claims (1)
1. A voltage test board circuit is characterized by comprising resistors R1, R2, R3, R4, R5, R6, R7 and R8, capacitors C1 and C2, diodes D1 and D2, triodes Q1 and Q2, a chip U, a voltage stabilizing diode D3, field effect transistors NMOS1 and NMOS 2;
the left end of the resistor R1 is electrically connected with the signal input end, the right end of the resistor R1 is electrically connected with the upper end of the capacitor C1, the upper end of the resistor R2 and the cathodes of the diodes D1 and D2 respectively, the anode of the diode D1 is electrically connected with the left end of the resistor R3, the right end of the resistor R3 is electrically connected with the upper end of the resistor R4, the base of the triode Q1 and the collector of the triode Q2 respectively, the collector of the triode Q1 is electrically connected with the left end of the resistor R7, and the right end of the resistor R7 is electrically connected with the upper end of the capacitor C2 and the pin 2 of the chip U respectively;
the anode of the diode D2 is electrically connected with the left end of the resistor R5, and the right end of the resistor R5 is electrically connected with the upper end of the resistor R6 and the base of the triode Q2 respectively;
the lower ends of the capacitors C1 and C2, the lower ends of the resistors R2, R4 and R6 and the emitters of the triodes Q1 and Q2 are grounded respectively;
the power supply comprises a chip U, a pin 1 of the chip U is electrically connected with a driving power supply through a resistor R8, a pin 6 of the chip U is electrically connected with grids of field effect transistors NMOS1 and NMOS2 respectively, sources of 4-pin field effect transistors NMOS1 and NMOS2 of the chip U are electrically connected, drains of the field effect transistors NMOS1 and NMOS2 are electrically connected with a signal output end respectively, a cathode of a voltage stabilizing diode D3 is electrically connected with the pin 6 of the chip U, and an anode of the voltage stabilizing diode D3 is electrically connected with the pin 4 of the chip U.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220643900.8U CN217443444U (en) | 2022-03-22 | 2022-03-22 | Voltage test board circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220643900.8U CN217443444U (en) | 2022-03-22 | 2022-03-22 | Voltage test board circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217443444U true CN217443444U (en) | 2022-09-16 |
Family
ID=83214854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220643900.8U Active CN217443444U (en) | 2022-03-22 | 2022-03-22 | Voltage test board circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217443444U (en) |
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2022
- 2022-03-22 CN CN202220643900.8U patent/CN217443444U/en active Active
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