CN217406507U

CN217406507U - LC filter

Info

Publication number: CN217406507U
Application number: CN202220559931.5U
Authority: CN
Inventors: 杜江; 矣峻岭
Original assignee: Chengdu Meishu Technology Co ltd
Current assignee: Chengdu Meishu Technology Co ltd
Priority date: 2022-03-15
Filing date: 2022-03-15
Publication date: 2022-09-09
Anticipated expiration: 2032-03-15

Abstract

The utility model discloses a LC filter, include: the device comprises a filter circuit and an equalizing circuit used for leveling time delay; the filter circuit is connected between a terminal P1 and a terminal P2 after being cascaded with the equalization circuit; the filter circuit includes: a plurality of cascaded filter units, an inductor L4 and a capacitor C6; one end of the cascaded filter units is connected with the inductor L4 and then connected with the endpoint P1, and the other end of the cascaded filter units is connected with the capacitor C6 and then connected with the equalizing circuit. The LC filter adopts a zero placement technology and a cascade hybrid network to carry out topology on a traditional LC filter circuit, solves the contradiction between out-of-band rejection and in-pass-band phase fluctuation of the filter, and simultaneously enables the filter to have higher rectangular coefficient and smaller phase fluctuation.

Description

LC filter

Technical Field

The utility model relates to a digital signal processing technology field particularly, relates to a LC wave filter.

Background

The LC filter is a filter circuit formed by utilizing the combined design of an inductor, a capacitor and a resistor, and can filter certain harmonic wave or multiple harmonic waves; the single-tuned filter, the double-tuned filter and the high-pass filter belong to passive filters.

The topological structure of the LC filter circuit is flexible, and the packaging modes are various. The traditional LC filter is mostly realized by an elliptic function type, the out-of-band attenuation of the near end is high, but the group delay fluctuation is large; the use of a Bessel or Gaussian filter with a linear phase function has the problem of slow out-of-band attenuation. The filter group delay is a main factor of signal delay and distortion caused by a receiving link, and the filter out-of-band rejection and the linear delay are a pair of contradictory indexes.

In view of this, the present application is specifically proposed.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that: how to solve the contradiction between the out-of-band rejection and the phase fluctuation in the pass band of the filter, and the purpose is to provide an LC filter, improve the traditional LC filter circuit by introducing a zero placement technology and a cascade mixed network, flexibly set the position of a resonance point of a series LC resonance circuit, thereby generating an out-of-band rejection point, improving the contradiction between the out-of-band rejection and a linear phase, and simultaneously realizing the flat phase characteristic in the band.

The utility model discloses a following technical scheme realizes:

an LC filter comprising: the device comprises a filter circuit and an equalizing circuit used for leveling time delay; the filter circuit is connected with the equalization circuit in cascade and then is connected between a point P1 and a point P2; the filter circuit includes: a plurality of cascaded filter units, an inductor L4 and a capacitor C6; one end of each of the cascaded filter units is connected with the inductor L4 and then connected with the endpoint P1, and the other end of each of the cascaded filter units is connected with the capacitor C6 and then connected with the equalizing circuit; the filtering unit includes: capacitors C1, C2, C3, C4 and C5, inductors L1, L2 and L3; the capacitor C1, the inductor L3 and the capacitor C2 are sequentially connected in series and then are connected in parallel with the capacitor C5; one end of the capacitor C3 connected with the inductor L1 in parallel is connected between the capacitor C1 and the inductor L3, and the other end is grounded; one end of the capacitor C4, which is connected in parallel with the inductor L2, is connected between the inductor L3 and the capacitor C2, and the other end is grounded.

As a further description of the present invention, the equalization circuit is an external equalization circuit, which includes a plurality of external equalization circuit units in cascade; the equalization circuit is connected between the filter circuit and the terminal P2.

As a further description of the present invention, the equalizing circuit unit includes: capacitors C7, C8 and C9, inductors L5 and L6; the capacitor C7 is connected in series with the capacitor C8 and then connected in parallel with the inductor L6; one end of the capacitor C9 connected in series with the inductor L5 is connected between the capacitors C7 and C8, and the other end is grounded.

As a further description of the present invention, the equalization circuit is an internal equalization circuit, which includes a plurality of internal equalization circuit units; the plurality of inner equalization circuit units are cascaded at two ends of the filter circuit.

As a further description of the present invention, the internal equalizing circuit unit includes: capacitors C10, C11 and C12, inductors L7 and L8; the capacitor C10 is connected in series with the inductor L8, and the inductor L7, the capacitor C11 and the capacitor C12 are connected in parallel; one end of the inductor L7 is connected with the capacitor C10, and the other end of the inductor L7 is grounded; one end of the capacitor C11 is connected between the capacitor C10 and the inductor L8, the other end is grounded, one end of the capacitor C12 is connected to the inductor L8, and the other end is grounded.

As a further description of the present invention, the LC filter further includes: metal layers D1, D2, D3, D4, and D5; a dielectric layer is arranged between two adjacent metal layers; the metal layers D1 and D5 are metal ground layers; the capacitors C1 and C2 are all included on the metal layers D2, D3 and D4; the capacitors C3 and C4 include two parallel MIM capacitors, one of which is located on the metal layers D1 and D2, and the other is located on the metal layers D4 and D5; the capacitor C5 is formed by a seam formed by two pieces of metal conductors extending towards the center on the metal layer D3; inductors L1 and L2 are arranged on the metal layers D2 and D4; the inductor L1 is connected in parallel with the capacitor C3 through a via hole, and the inductor L2 is connected in parallel with the capacitor C4 through a via hole; the inductors L1 and L2 are connected with the metal layer D5 through via holes; the inductors L1 and L2 are close to each other along the y-axis direction to form the inductor L3; the port P1 and the port P2 are located on the metal layer D3; one end of the terminal P1 and one end of the terminal P2 are connected to a metal conductor, and the other end of the terminal P1 and the other end of the terminal P2 are connected to the outside.

As a further description of the present invention, the inductors L1, L2, L3, L4 and L5 are all three-dimensional spiral inductors; the capacitors C1 and C2 are VIC capacitors.

As a further description of the present invention, the three-dimensional spiral inductor includes: a plurality of bottom metal strips, a plurality of top metal strips, and a plurality of metal connection posts; the bottom layer metal strip is of an L-shaped structure; the top layer metal strip is obtained by turning the bottom layer metal strip 180 degrees on the plane of the bottom layer metal strip and then rotating the bottom layer metal strip 180 degrees clockwise; the bottom metal strips and the top metal strips are arranged in parallel along the long edge; the end part of the short side of the bottom layer metal strip is connected with the end part of the long side of the top layer metal strip through the metal connecting column.

As a further description of the present invention, both the lower surface of the metal layer D1 and the upper surface of the metal layer D5 are covered with a protective layer.

As a further description of the present invention, intermediate composite layers for providing relaxed interfacial stress are included between the dielectric layers and the metal layers D1, D2, D3, D4, and D5.

Compared with the prior art, the utility model, following advantage and beneficial effect have:

1. the embodiment of the utility model provides a LC filter adopts zero place technique and cascade hybrid network to carry out topology to traditional LC filter circuit, has solved the contradiction between the phase fluctuation in the out-of-band suppression of filter and the passband, makes the filter have higher rectangular coefficient and less phase fluctuation simultaneously;

2. the embodiment of the utility model provides an LC filter, introduced the cross coupling between source and the load, obtained two transmission zero points that the position can be adjusted to make the filter have stronger practicality;

3. the embodiment of the utility model provides an LC filter provides two kinds of balanced structures of outer equalizer circuit and interior equalizer circuit, can compensate the time delay fluctuation of filter, plays the effect of leveling time delay;

4. the embodiment of the utility model provides an LC filter, based on low temperature burns ceramic technology altogether, introduced the layering technique, arrange the circuit component of filter on different layers, utilize the coupling relation of circuit component on different layers to reduce circuit size, realize the miniaturization of filter;

5. the embodiment of the utility model provides an LC filter, adopt three-dimensional spiral inductance, reduce the size of filter circuit; by adopting the VIC capacitor, the advantages of a multilayer structure are fully utilized, and a larger capacitor can be realized on a smaller volume;

6. in the LC filter provided by the embodiment of the utility model, the protective layers cover the upper surface and the lower surface of the filter, so as to protect the filter well;

7. the embodiment of the utility model provides a pair of LC filter has added the composite bed between dielectric layer and metal level, introduces relaxation interfacial stress, avoids dielectric layer and metal level warpage and fracture appear when burning altogether.

Drawings

In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and that for those skilled in the art, other related drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of a circuit structure of an LC filter cascaded with an external equalization circuit according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a circuit structure of an LC filter in which an internal equalization circuit is cascaded according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an LC filter having multiple metal layers according to an embodiment of the present invention;

fig. 4 is a partial enlarged view of an LC filter structure with multiple metal layers according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a three-dimensional spiral inductor structure according to an embodiment of the present invention.

Reference numbers and corresponding part names in the drawings:

1-filter circuit, 2-equalization circuit, 11-filter unit, 21-outer equalization circuit unit, 22-inner equalization circuit unit, 31-metal layer D1, 32-metal layer D2, 33-metal layer D3, 34-metal layer D4, 35-metal layer D5, 36-protective layer, 41-bottom metal strip, 42-top metal strip and 43-metal connecting column.

Detailed Description

To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those of ordinary skill in the art that: it is not necessary to employ these specific details to practice the invention. In other instances, well-known structures, circuits, materials, or methods have not been described in detail so as not to obscure the present invention.

Throughout the specification, reference to "one embodiment," "an embodiment," "one example" or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the present invention. Thus, the appearances of the phrases "one embodiment," "an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and are not necessarily drawn to scale. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the present invention, the terms "front", "rear", "left", "right", "upper", "lower", "vertical", "horizontal", "high", "low", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the scope of the present invention.

Examples

The near-end out-of-band attenuation of the traditional LC filter is high, but the group delay fluctuation is large; however, the use of a linear phase function bessel-type or gaussian-type filter has a problem of slow out-of-band attenuation. In order to solve the contradiction between the out-of-band rejection and the phase fluctuation in the pass band of the filter, the implementation provides an LC filter, introduces a zero point placing technology, introduces a transmission zero point through cross coupling and an LC resonance circuit, and flexibly sets the position of a resonance point of a series LC resonance circuit, thereby generating an out-of-band rejection point and improving the contradiction between the out-of-band rejection and a linear phase; a cascade hybrid network is introduced, and time delay fluctuation is compensated through an equalizing circuit, so that the function of leveling time delay is achieved.

Specifically, as shown in fig. 1, the LC filter provided in this embodiment includes: the device comprises a filter circuit 1 and an equalizing circuit 2 for leveling time delay; the filter circuit 1 is connected in cascade with the equalization circuit 2 between a terminal P1 and a terminal P2. Wherein, filter circuit 1 is based on the improvement that 1 structure of nine sections ellipse filter circuit carried out, includes: a plurality of cascaded filter units 11, an inductor L4 and a capacitor C6; one end of the cascaded filter units 11 is connected to the inductor L4 and then connected to the terminal P1, and the other end is connected to the capacitor C6 and then connected to the equalizing circuit 2. The filtering unit 11 includes: capacitors C1, C2, C3, C4 and C5, inductors L1, L2 and L3; the capacitor C1, the inductor L3 and the capacitor C2 are sequentially connected in series and then are connected in parallel with the capacitor C5; one end of the capacitor C3 connected in parallel with the inductor L1 is connected between the capacitor C1 and the inductor L3, and the other end is grounded; one end of the capacitor C4 connected in parallel with the inductor L2 is connected between the inductor L3 and the capacitor C2, and the other end is grounded.

The circuit structure introduces cross coupling between the source and the load, and obtains two transmission zero points with adjustable positions, so that the filter has stronger practicability. Due to the addition of the resonant tank, the impedance characteristics of the circuit are changed, requiring readjustment of the component values.

Furthermore, the group delay of the filter is generally in a concave parabolic shape, and an equalizing circuit with a convex parabolic group delay characteristic can be adopted to compensate delay fluctuation, so that the function of leveling the delay is achieved.

The present embodiment provides two ways of external equalizer circuit compensation and internal equalizer circuit compensation, as follows:

on one hand, the external equalization method is to design a delay equalizer opposite to the delay characteristic of the filter to be cascaded with the filter, so as to realize the in-band relatively flat phase characteristic. The inner equalization method is to place transmission zeros on the real axis of the transmission function to achieve linear phase within the pass band. In this embodiment, the second-order external equalizer circuit 2 is cascaded with the filter circuit 1. In fig. 1, a second-order external equalization circuit 2 is cascaded with two external equalization circuit units 21; the equalization circuit 2 is connected between the filter circuit 1 and the terminal P2. The external equalization circuit unit 21 includes: capacitors C7, C8 and C9, inductors L5 and L6; the capacitor C7 is connected in series with the capacitor C8 and then connected in parallel with the inductor L6; one end of the capacitor C9 connected in series with the inductor L5 is connected between the capacitors C7 and C8, and the other end is grounded.

On the other hand, as shown in fig. 2, the internal equalization circuit unit 22 includes: capacitors C10, C11 and C12, inductors L7 and L8; the capacitor C10 is connected in series with the inductor L8, and the inductor L7, the capacitor C11 and the capacitor C12 are connected in parallel; one end of the inductor L7 is connected with the capacitor C10, and the other end of the inductor L7 is grounded; one end of the capacitor C11 is connected between the capacitor C10 and the inductor L8, the other end is grounded, one end of the capacitor C12 is connected to the inductor L8, and the other end is grounded. In fig. 2, two inner equalization circuit units 22 are cascaded across the filter circuit 1.

Further, in the above-mentioned case,

with the rapid development of wireless communication technology, more and more mobile devices have wireless communication functions such as bluetooth and WiFi. The conventional filter circuit 1 is usually designed on a plane, so that the designed circuit has a large size and cannot meet the requirements of mobile devices. In this embodiment, a layered structure is introduced based on the low-temperature co-fired ceramic technology, the LC filter circuits are arranged on different layers, and the coupling relationship between circuit elements on different layers is utilized to reduce the circuit size and achieve miniaturization of the filter. As shown in fig. 3 and 4, the present embodiment employs a layered structure including: metal layers D131, D232, D333, D434, and D535; a dielectric layer is arranged between two adjacent metal layers; the metal layers D131 and D535 are metal layers; the capacitors C1 and C2 are included on the metal layers D232, D33 and D434; the capacitors C3 and C4 include two parallel MIM capacitors, one located on the metal layers D131 and D232 and the other located on the metal layers D434 and D535; a gap formed by two metal conductors extending towards the center on the metal layer D333 forms the capacitor C5; inductors L1 and L2 are included on the metal layers D232 and D434; the inductor L1 is connected in parallel with the capacitor C3 through a via hole, and the inductor L2 is connected in parallel with the capacitor C4 through a via hole; the inductors L1 and L2 are connected with the metal layer D535 through via holes; the inductors L1 and L2 are close to each other along the y-axis direction to form the inductor L3; the port P1 and the port P2 are located on the metal layer D333; one end of the terminal P1 and one end of the terminal P2 are connected to a metal conductor, and the other end of the terminal P1 and the other end of the terminal P2 are connected to the outside.

To further reduce the size of the filter circuit, a three-dimensional spiral inductor is used as shown in fig. 5. The three-dimensional spiral inductor comprises: a plurality of bottom metal strips 41, a plurality of top metal strips 42 and a plurality of metal connection posts 43; the bottom layer metal strip 41 is of an L-shaped structure; the top layer metal strip 42 is obtained by turning the bottom layer metal strip 41 on the plane by 180 degrees and then rotating the bottom layer metal strip by 180 degrees clockwise; the plurality of bottom metal strips 41 and the plurality of top metal strips 42 are arranged in parallel along the long sides; the ends of the short sides of the bottom metal strip 41 and the ends of the long sides of the top metal strip 42 are connected by the metal connecting posts 43. In addition, the capacitors C1 and C2 are VIC capacitors, the advantages of a multilayer structure are fully utilized, and large capacitors can be realized on the small size.

In addition, the lower surface of the metal layer D131 and the upper surface of the metal layer D535 are both covered with the protective layer 36, which plays a good role in protecting the filter; an intermediate composite layer for providing a relaxed interface stress is arranged between the dielectric layer and the metal layers D131, D232, D333, D434 and D535, and the sintering property and the components of the intermediate composite layer are similar to those of the dielectric layer and the metal layers, so that the dielectric layer and the metal layers are prevented from warping and cracking during co-firing.

The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An LC filter, comprising: the device comprises a filter circuit (1) and an equalizing circuit (2) for leveling time delay; the filter circuit (1) is connected between a terminal P1 and a terminal P2 after being cascaded with the equalization circuit (2); the filter circuit (1) comprises: a plurality of cascaded filter units (11), an inductor L4 and a capacitor C6; one end of each of the cascaded filter units (11) is connected with the inductor L4 and then connected with the endpoint P1, and the other end of each of the cascaded filter units is connected with the capacitor C6 and then connected with the equalizing circuit (2); the filtering unit includes: capacitors C1, C2, C3, C4 and C5, inductors L1, L2 and L3; the capacitor C1, the inductor L3 and the capacitor C2 are sequentially connected in series and then are connected in parallel with the capacitor C5; one end of the capacitor C3 connected in parallel with the inductor L1 is connected between the capacitor C1 and the inductor L3, and the other end is grounded; one end of the capacitor C4 connected in parallel with the inductor L2 is connected between the inductor L3 and the capacitor C2, and the other end is grounded.

2. An LC filter according to claim 1, characterized in that the equalization circuit (2) is an outer equalization circuit comprising a cascade of a plurality of outer equalization circuit units (21); the equalization circuit (2) is connected between the filter circuit (1) and the terminal point P2.

3. An LC filter according to claim 2, characterized in that the equalization circuit unit (21) comprises: capacitors C7, C8 and C9, inductors L5 and L6; the capacitor C7 is connected in series with the capacitor C8 and then connected in parallel with the inductor L6; one end of the capacitor C9 connected in series with the inductor L5 is connected between the capacitors C7 and C8, and the other end is grounded.

4. An LC filter according to claim 1, characterized in that said equalization circuit (2) is an internal equalization circuit comprising a plurality of internal equalization circuit cells (22); the plurality of inner equalization circuit units (22) are cascaded at two ends of the filter circuit (1).

5. An LC filter according to claim 4, characterized in that said internal equalization circuit unit (22) comprises: capacitors C10, C11 and C12, inductors L7 and L8; the capacitor C10 is connected in series with the inductor L8, and the inductor L7, the capacitor C11 and the capacitor C12 are connected in parallel; one end of the inductor L7 is connected with the capacitor C10, and the other end of the inductor L7 is grounded; one end of the capacitor C11 is connected between the capacitor C10 and the inductor L8, the other end is grounded, one end of the capacitor C12 is connected to the inductor L8, and the other end is grounded.

6. An LC filter according to claim 1, comprising: metal layers D1(31), D2(32), D3(33), D4(34), and D5 (35); a dielectric layer is arranged between two adjacent metal layers; the metal layers D1(31) and D5(35) are metal ground layers; the metal layers D2(32), D3(33) and D4(34) all include the capacitors C1 and C2 thereon; the capacitors C3 and C4 include two parallel MIM capacitors, one located on the metal layers D1(31) and D2(32) and the other located on the metal layers D4(34) and D5 (35); the capacitor C5 is formed by a seam formed by two pieces of metal conductors extending towards the center on the metal layer D3 (33); inductors L1 and L2 are included on each of the metal layers D2(32) and D4 (34); the inductor L1 is connected in parallel with the capacitor C3 through a via hole, and the inductor L2 is connected in parallel with the capacitor C4 through a via hole; the inductors L1 and L2 are connected with the metal layer D5(35) through via holes; the inductors L1 and L2 are close to each other along the y-axis direction to form the inductor L3; the endpoint P1 and the endpoint P2 are located on the metal layer D3 (33); one end of the terminal P1 and one end of the terminal P2 are connected to a metal conductor, and the other end of the terminal P1 and the other end of the terminal P2 are connected to the outside.

7. The LC filter of claim 6, wherein the inductors L1, L2, L3, L4 and L5 are all three-dimensional spiral inductors; the capacitors C1 and C2 are VIC capacitors.

8. An LC filter according to claim 7, wherein said three-dimensional spiral inductor comprises: a plurality of bottom metal strips (41), a plurality of top metal strips (42) and a plurality of metal connection posts (43); the bottom layer metal strip (41) is of an L-shaped structure; the top layer metal strip (42) is obtained by turning the bottom layer metal strip (41) on the plane by 180 degrees and then rotating the bottom layer metal strip by 180 degrees clockwise; the bottom metal strips (41) and the top metal strips (42) are arranged in parallel along the long sides; the end part of the short side of the bottom layer metal strip (41) is connected with the end part of the long side of the top layer metal strip (42) through the metal connecting column (43).

9. An LC filter according to claim 6, comprising: the lower surface of the metal layer D1(31) and the upper surface of the metal layer D5(35) are both covered with a protective layer (36).

10. An LC filter according to claim 6, characterised in that intermediate composite layers for providing relaxed interfacial stress are included between the dielectric layers and the metal layers D1(31), D2(32), D3(33), D4(34) and D5 (35).