CN217404353U - Semiconductor detection tool - Google Patents
Semiconductor detection tool Download PDFInfo
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- CN217404353U CN217404353U CN202220911373.4U CN202220911373U CN217404353U CN 217404353 U CN217404353 U CN 217404353U CN 202220911373 U CN202220911373 U CN 202220911373U CN 217404353 U CN217404353 U CN 217404353U
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- chip
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Abstract
A semiconductor detection jig comprises: the chip placing cavity is used for placing a chip to be detected, the bottom of the chip placing cavity is provided with a plurality of probes, and one ends of the probes are connected with the chip to be detected placed in the chip placing cavity; the circuit board is provided with a plurality of second through holes, and the side wall surfaces of the second through holes are provided with metal layers connected with the metal circuits; the other ends of a plurality of probes at the bottom of the chip placing cavity penetrate through the first through hole and extend into the second through hole, and the part of the probe extending into the second through hole is welded with the metal layer on the surface of the side wall of the second through hole. The semiconductor detection tool can prevent short circuit between metal lines caused by water vapor invasion.
Description
Technical Field
The utility model relates to a semiconductor testing field especially relates to a semiconductor detection tool.
Background
A chip, also called an integrated circuit (integrated circuit), is a micro electronic device or component, and is manufactured by a certain semiconductor manufacturing process (such as photolithography, etching, deposition, ion implantation), and interconnecting the required elements of transistors, diodes, resistors, capacitors, inductors, and the like and wiring in a circuit together on one or more small semiconductor wafers or dielectric substrates, and then packaged in a package to form a micro structure with the required circuit function, so that the electronic element is greatly advanced toward miniaturization, low power consumption, and high reliability.
In the manufacturing process of the chip, a detection procedure is needed before the chip is processed, manufactured and put into the market, and the conventional general detection procedure is to mount and fix the processed chip and the PCB mainboard and then detect the related electrical properties.
A plurality of circuits and pads connected with the circuits are formed on the existing PCB main board, the pads on the PCB main board are electrically connected with a chip to be detected through probes, and the PCB main board is connected with a detection host machine to form a test loop. However, in the detection process, the problem that data cannot be collected due to the fact that short circuits exist in the circuit on the PCB main board exists.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a semiconductor detection tool, include:
the chip placing cavity is used for placing a chip to be detected, a plurality of protruding probes are arranged at the bottom of the chip placing cavity, and one ends of the probes are connected with the chip to be detected placed in the chip placing cavity;
the supporting plate is positioned between the circuit board and the bottom of the chip placing cavity and is attached to the circuit board, a plurality of first through holes penetrating through the thickness of the supporting plate are formed in the supporting plate, a plurality of metal circuits are arranged inside the circuit board, a plurality of second through holes penetrating through the thickness of the circuit board are formed in the circuit board, partial surfaces of the metal circuits are exposed out of the side walls of the second through holes, and metal layers connected with the metal circuits are arranged on the surfaces of the side walls of the second through holes;
the other ends of the probes at the bottom of the chip placing cavity penetrate through the first through hole and extend into the second through hole, and the part of the probe extending into the second through hole is welded with the metal layer on the surface of the side wall of the second through hole.
Optionally, the hardness and rigidity of the supporting plate are greater than those of the circuit board, and the temperature resistance of the circuit board is higher than that of the supporting plate.
Optionally, the support plate is a rigid PCB substrate.
Optionally, the support plate surface and the support plate do not have any wiring therein.
Optionally, the sidewall surface of the first via hole has a second metal layer.
Optionally, the circuit board is a flexible circuit substrate.
Optionally, the metal lines are located inside the flexible circuit substrate.
Optionally, the chip placing cavity has a closed cavity, the chip to be detected is located in the cavity, and the surface of one end of the probes is exposed in the cavity.
Optionally, the semiconductor detection device is suitable for being placed in the heat insulation box when the chip to be detected is subjected to electrical performance detection.
Optionally, the heat preservation box is suitable for introducing an inert gas with a specific pressure and maintaining a specific temperature when detecting the electrical property.
The utility model discloses in aforementioned semiconductor test fixture, include: the chip placing cavity is used for placing a chip to be detected, a plurality of protruding probes are arranged at the bottom of the chip placing cavity, and one ends of the probes are connected with the chip to be detected placed in the chip placing cavity; the supporting plate is positioned between the circuit board and the bottom of the chip placing cavity and is attached to the circuit board, a plurality of first through holes penetrating through the thickness of the supporting plate are formed in the supporting plate, a plurality of metal circuits are arranged inside the circuit board, a plurality of second through holes penetrating through the thickness of the circuit board are formed in the circuit board, partial surfaces of the metal circuits are exposed out of the side walls of the second through holes, and metal layers connected with the metal circuits are arranged on the surfaces of the side walls of the second through holes; the other ends of the probes at the bottom of the chip placing cavity penetrate through the first through hole and extend into the second through hole, and the part of the probe extending into the second through hole is welded with the metal layer on the surface of the side wall of the second through hole. Through setting up backup pad and circuit board in this application, the backup pad is used for supporting on the one hand the circuit board prevents that the circuit board from warping the metal circuit who brings and exposing, on the other hand, the backup pad can also be used to the circuit board with the isolation between the chamber is placed to the chip. And, a plurality of metal circuit are located inside the circuit board, promptly the metal circuit is by the material of circuit board the cover can not expose in the air, therefore when high temperature test, the metal circuit in the circuit board can not be exposed to prevent the short circuit between the metal circuit that the steam invasion brought.
Drawings
Fig. 1-2 are schematic structural views of a semiconductor inspection jig according to some embodiments of the present invention.
Detailed Description
As background art says, a plurality of circuits and pads connected with the circuits are formed on the existing PCB main board, the pads on the PCB main board are electrically connected with the chip to be detected through probes, and the PCB main board is connected with a detection host to form a test loop. However, in the detection process, the problem that data cannot be collected due to the fact that short circuits exist in the circuit on the PCB main board exists.
Research discovers that the circuit on the existing PCB main board is isolated from the outside by welding the solder ink coverage, but when some specific pressure and temperature are tested, the chip and the PCB main board need to be arranged in the heat preservation box, the PCB main board has water vapor to corrode the PCB after passing through a period of high and low temperature in the heat preservation box, so that the solder ink on the surface of the PCB main board falls off, and the water vapor contacts the exposed circuit to cause short circuit, so that the test host can not normally collect data.
Therefore, the utility model provides a semiconductor detection tool can avoid testing tool to do not seal completely in high temperature environment and hinder that reason such as completely isolated caused and weld the printing ink and drop to prevent that steam from contacting the problem that naked circuit caused the short circuit.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. In describing the embodiments of the present invention in detail, the drawings are not necessarily to scale, and the drawings are merely exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
An embodiment of the present invention provides a semiconductor testing jig, please refer to fig. 1 and fig. 2, fig. 2 is a schematic structural diagram of fig. 1 when each part is not welded, including:
the chip detection device comprises a chip placing cavity 101, wherein a chip to be detected is placed in the chip placing cavity 101, a plurality of protruding probes 104 are arranged at the bottom of the chip placing cavity 101, and one ends of the probes 104 are connected with the chip to be detected placed in the chip placing cavity 101;
a supporting plate 102 and a circuit board 103, wherein the supporting plate 102 is located between the circuit board 103 and the bottom of the chip placement cavity 101, and the supporting plate 102 is attached to the circuit board 103, the supporting plate 102 has a plurality of first through holes 105 (refer to fig. 2) penetrating through the thickness of the supporting plate 102, the circuit board 103 has a plurality of metal circuits (not shown in the figure), the circuit board 103 has a plurality of second through holes 106 penetrating through the thickness of the circuit board 103, the side walls of the second through holes 106 expose partial surfaces of the metal circuits, and the side wall surfaces of the second through holes have metal layers (not shown in the figure) connected with the metal circuits;
the other ends (the ends not connected with the chip to be detected) of the probes 104 at the bottom of the chip placing cavity 101 penetrate through the first through holes 105 and extend into the second through holes 106, and the parts of the probes 104 extending into the second through holes 106 are welded with the metal layer on the side wall surface of the second through holes 106.
Specifically, the chip placing cavity 101 is used for placing a chip to be detected, the chip placing cavity 101 is provided with a cavity or a groove, and the chip with detection is placed in the cavity and the groove. In some embodiments, the chip placing cavity 101 may be a sealed or non-sealed chip placing cavity, and when the chip placing cavity 101 is sealed, the chip to be detected placed in the chip placing cavity 101 does not contact with the outside air.
In some embodiments, the chip placing cavity 101 has a holding device therein, the holding device is used for fixing the chip to be detected, and the output pad or pin of the chip to be detected is electrically contacted with one end of the probe.
In some embodiments, the chip to be tested is a chip that needs to be tested after packaging, and the relevant tests include electrical performance tests (such as short circuit, open circuit and resistance tests), and special environment tests (such as high temperature tests or pressure tests). The chip to be tested comprises an integrated circuit with a specific function formed through a semiconductor integrated manufacturing process and an output bonding pad or pin connected with the integrated circuit, and part of the surface of the output bonding pad or pin is not covered by packaging materials when the chip to be tested is packaged. In some embodiments, the chips to be tested include, but are not limited to, sensor chips, power supply chips, signal processing chips, logic control chips, memory chips, and the like.
The probes 104 are disposed at the bottom of the chip placing cavity 101, in a specific embodiment, the probes 104 may be partially embedded in the bottom material of the chip placing cavity 101, a surface of one end of the probes is exposed in the cavity or the groove of the chip placing cavity 101, and the other end of the probes protrudes from the top surface of the chip placing cavity 101.
In some embodiments, the probes 104 are arranged in an array, and the probes 104 are used to connect pads (or pins) of the chip to be tested with corresponding metal lines in the circuit board 103 to form a detection loop.
The supporting plate 102 is used to support the circuit board 103 and prevent the metal circuit from being exposed due to the deformation of the circuit board 103, and on the other hand, the supporting plate 102 can also be used to isolate the circuit board 103 from the chip placing cavity 101. The circuit board 103 has a plurality of metal circuits therein (not shown in the figure)
In some embodiments, the hardness and rigidity of the supporting plate 102 are greater than those of the circuit board 103, and the temperature resistance of the circuit board 103 is greater than that of the supporting plate 102, so that the supporting plate 102 can provide good support, and on the other hand, the circuit board is not easily deformed during high-temperature testing, thereby better protecting the metal circuit in the circuit board 103.
In some embodiments, the support plate 102 has only a number of first through holes 105 extending through the thickness of the support plate 102, the support plate 102 is a rigid PCB substrate, the surface of the support plate 102 and the support plate 102 do not have any wires therein, and all metal wires are within the wiring board 103.
In some embodiments, the material of the rigid PCB substrate may be a material that is light in weight, and meets a certain hardness (the stiffener needs a certain hardness). In some embodiments, the material of the rigid PCB substrate may include an organic insulating material. In a specific embodiment, the material of the rigid PCB substrate may include FR4(FR4 is a code number of a fire-resistant material grade) specification material. The FR4 specification material may be a composite material including epoxy resin and glass fiber, etc. The FR4 specification material is light in weight, can be made to a certain thickness and does not weigh much.
In some embodiments, the sidewall surface of the first through hole 105 has a second metal layer, and the probe 104 may be welded together with the second metal layer in a subsequent welding process.
In some embodiments, the circuit board 103 is a flexible circuit substrate, and the material of the flexible circuit substrate is a flexible material, and the flexible material includes polyimide or polyethylene terephthalate. A plurality of metal lines are located inside the flexible circuit substrate, promptly the metal line is by the material of flexible substrate the cover can not expose in the air, and because the flexible circuit substrate heat resistance is better, therefore when high temperature test, the flexible circuit substrate can not damage, and the metal line in the circuit board 103 can not be exposed to prevent the short circuit between the metal line that the steam invasion brought.
When the semiconductor detection jig is used for detection, the metal circuit in the circuit board 103 is also connected with a detection host, so that a chip to be detected, the metal circuit and the detection host form a test loop, and the detection host is used for sending a detection signal, receiving a feedback signal generated during detection, processing the feedback signal and outputting a detection structure.
In some embodiments, the semiconductor detection jig is adapted to be placed in the heat insulation box when the chip to be detected is subjected to electrical performance detection. The heat preservation box is suitable for introducing inert gas with specific pressure and keeping specific temperature when detecting electrical properties. Specifically, when carrying out high temperature and high-pressure test, with this application semiconductor test tool arranges the incubator in, when detecting, lets in the inert gas of specific pressure and heats to specific temperature and keeps this specific temperature in the incubator.
To sum up, this application foretell semiconductor inspection tool, include: the chip placing cavity is provided with a supporting plate and a circuit board, the supporting plate is positioned between the circuit board and the bottom of the chip placing cavity and is attached to the circuit board, a plurality of first through holes penetrating through the thickness of the supporting plate are formed in the supporting plate, a plurality of metal circuits are arranged in the circuit board, a plurality of second through holes penetrating through the thickness of the circuit board are formed in the circuit board, partial surfaces of the metal circuits are exposed out of the side walls of the second through holes, and metal layers connected with the metal circuits are arranged on the side wall surfaces of the second through holes; the other ends of the probes at the bottom of the chip placing cavity penetrate through the first through hole and extend into the second through hole, and the part of the probe extending into the second through hole is welded with the metal layer on the surface of the side wall of the second through hole. Through setting up backup pad and circuit board in this application, the backup pad is used for supporting on the one hand the circuit board prevents that the circuit board from warping the metal circuit who brings and exposing, on the other hand, the backup pad can also be used to the circuit board with the isolation between the chamber is placed to the chip. And, a plurality of metal circuit are located inside the circuit board, promptly the metal circuit is by the material of circuit board the cover can not expose in the air, therefore when high temperature test, the metal circuit in the circuit board can not be exposed to prevent the short circuit between the metal circuit that the steam invasion brought.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can use the method and technical contents disclosed above to make possible changes and modifications to the technical solution of the present invention without departing from the spirit and scope of the present invention, therefore, any simple modifications, equivalent changes and modifications made to the above embodiments by the technical substance of the present invention are all within the protection scope of the technical solution of the present invention.
Claims (10)
1. A semiconductor detection tool is characterized by comprising:
the chip placing cavity is used for placing a chip to be detected, a plurality of protruding probes are arranged at the bottom of the chip placing cavity, and one ends of the probes are connected with the chip to be detected placed in the chip placing cavity;
the supporting plate is positioned between the circuit board and the bottom of the chip placing cavity, the supporting plate is attached to the circuit board, a plurality of first through holes penetrating through the thickness of the supporting plate are formed in the supporting plate, a plurality of metal circuits are arranged inside the circuit board, a plurality of second through holes penetrating through the thickness of the circuit board are formed in the circuit board, the side walls of the second through holes are exposed out of partial surfaces of the plurality of metal circuits, and metal layers connected with the metal circuits are arranged on the side wall surfaces of the second through holes;
the other ends of the probes at the bottom of the chip placing cavity penetrate through the first through hole and extend into the second through hole, and the part of the probe extending into the second through hole is welded with the metal layer on the surface of the side wall of the second through hole.
2. The semiconductor test fixture of claim 1, wherein the supporting board has a hardness and a rigidity greater than those of the circuit board, and the circuit board has a temperature resistance greater than that of the supporting board.
3. The semiconductor inspection tool of claim 1 or 2, wherein the support plate is a rigid PCB substrate.
4. The semiconductor inspection tool of claim 3 wherein the support plate surface and the support plate do not have any wiring therein.
5. The semiconductor inspection jig according to claim 3, wherein the sidewall surface of the first through hole has a second metal layer.
6. The semiconductor inspection jig according to claim 1 or 2, wherein the circuit board is a flexible circuit board.
7. The semiconductor inspection tool of claim 6 wherein the metal traces are located within the flexible circuit substrate.
8. The semiconductor test fixture of claim 1, wherein the chip placement cavity has a closed cavity, the chip to be tested is located in the cavity, and a surface of one end of the plurality of probes is exposed in the cavity.
9. The semiconductor inspection tool of claim 1, wherein the semiconductor inspection tool is adapted to be placed in an incubator when inspecting electrical properties of a chip to be inspected.
10. The semiconductor inspection tool of claim 9 wherein the thermal container is adapted to introduce an inert gas at a specific pressure and maintain a specific temperature during the inspection of the electrical properties.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220911373.4U CN217404353U (en) | 2022-04-14 | 2022-04-14 | Semiconductor detection tool |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220911373.4U CN217404353U (en) | 2022-04-14 | 2022-04-14 | Semiconductor detection tool |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217404353U true CN217404353U (en) | 2022-09-09 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220911373.4U Active CN217404353U (en) | 2022-04-14 | 2022-04-14 | Semiconductor detection tool |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217404353U (en) |
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2022
- 2022-04-14 CN CN202220911373.4U patent/CN217404353U/en active Active
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