CN2173968Y - Universal Chinese card for computer - Google Patents

Abstract

The utility model relates to a universal external connecting type Chinese card for a computer inserted on a parallel interface, belonging to the technical field of an interface in the computer science. The universal external connecting type Chinese card comprises a character library array 1, a time sequence device 2, a latch device 3, a chip select device 4, an exchange device 5, a plug matched with the parallel interface 6 of a host machine and a down-lead which are installed on a circuit board, wherein, the data line of the interface 6 is connected with the input of the latch device 3 and the exchange device 5 and the address feet of the character library 1. A control line is connected with the input of the time sequence device 2, the exchange device 5 and the chip select device 4. A state line is connected with the output of the exchange device 5. The output of the latch device 3 is connected with the address end of the character library 1. The output of the chip select device 4 is connected with the chip select feet of the character library 1. The output of the character library 1 is connected with the input of the exchange device 5. The universal external connecting type Chinese card for the computer does not occupy the extending slot of the host machine, and itself also provides a parallel interface.

Description

Universal Chinese card for computer

The utility model relates to a kind of computer Chinese character card, belongs to the interfacing field in the computer science.

Since computer Chinese character card is released, because its strong functions makes market continue to increase its demand.But present Chinese Card also has following deficiency:

1. need take a host expansion slot, common microcomputer on the market, expansion slot has eight at most, and few has only three.And the expansion card that the user need insert is more and more, can't be exhaustive one by one as the encrypted card of the driver card of the interface card of network interface card, virus card, scanner, laser printer, software, display card, hard disk card, expanded memory card etc.Squeezing one and come out to insert Chinese Card in quite nervous expansion slot, is very difficult thing.The microcomputer that has, all do not have expansion slot as notebook machine, hand held machine, network non-disk workstation etc., may not use present Chinese Card, the manufacturer that has have to be cured to Chinese Card on the machine mainboard, like this, the machine that does not solidify Chinese Card still can't use Chinese Card.

2. need occupying system resources.Chinese Card needs committed memory address and port address, and PC has only the address space of 1M under real pattern, and about vacant address space 128K, port address has only 4K, and vacant is also few.So plugging Chinese Card is easy to conflict with other card.

3. present Chinese Card generally can only be used on the isa bus.PS/2 is a mca bus, so many Chinese Cards all can't be used on the PS/2, and bussing technique is also in development constantly, and whether Chinese Card can move on bus in the future, still a problem.

4. insert Chinese Card and need open cabinet, cumbersome.For the layman, also might burn out machine because of carelessness.Universal day by day along with computing machine, easily installation property has become an index of computer product evaluation and test.

The purpose of this utility model is that design does not a kind ofly take host expansion slot, do not take the external Hanzi board of other system resource yet.

Parallel interface is the external apparatus interface that present microcomputer extensively adopts, and can connect printer and draught machine etc.Because parallel interface is the interface of one-way transmission, promptly send the interface of data to peripheral hardware, so the function of data input is not provided in the interface by microcomputer.As with it as the Chinese Card interface, then not only need Chinese Card is sent in the address of font data in control signal and the character library, the more important thing is and font data will be read in internal memory, so that main frame is further handled.Find behind various by analysis parallel interface data and the control program that the output signal of in fact using is D0__D7, STROBE and INIT.Output data is placed on the D0__D7, and STROBE offers peripheral hardware and latchs control, and INIT is used to make peripheral hardware to reset.Whenever microcomputer when peripheral hardware transmits data, at first detect the busy-idle condition of peripheral hardware, it is the BUSY signal, when peripheral hardware such as is at the idle condition of pending data input, program just is placed on the eight bit data of a byte on the D0__D7, on the STROBE line, send out a positive pulse then, make peripheral hardware latch data on the D0__D7.The key that this shows data transmission is controlled at the STROBE signal, and this signal does not change, and peripheral hardware can not shown interest in data-signal, and INIT should remain on high level in course of normal operation simultaneously.And SLCTIN is always low level in the operating process of various peripheral hardwares, and AUTOFD is always high level.Further analyze the printout program of DOS and Windows, what find to adopt all is same method, and the analysis of some typical application (as: AUTOCAD, TANGO, WordStar, WordPerfect etc.) has also been drawn same conclusion.

So, whether can be when not influencing the parallel interface normal running, utilize SLCTIN and AUTOFD to be used as the operation control of Chinese Card? process is to several widely used external units that receive data by parallel interface, interface control circuit as printer and draught machine, the analysis of interface control signal and control program is found, distinct device is not quite similar to the processing of SLCTIN and AUTOFD, but as can be seen these two signals belong to functional deterioration signal, most of peripheral hardware is not all handled this two signals, and minority is listed it in optional signal and fully need not in the practical operation.In addition, though be not sent to the data signal line of microcomputer from peripheral hardware, but there are 2 handshake and 3 status signals to read for microcomputer, if do the data input to obtain font data with these 5 signals, then can consider to use parallel interface as the Chinese Card interface now, and make the control signal of Chinese Card with SLCTIN and AUTOFD signal.

The purpose of this utility model be achieved in that the computer general-purpose external Hanzi board by guard shield, power supply, be contained in that MASKROM display, timing control unit, address latch unit, ROM array chip on the printed-wiring board (PWB) selects logical block, switching logic unit, the plug and the lead-in wire that match with host parallel interface are formed.Wherein: the data line ground connection location latch units of parallel interface and the input of switching logic unit and the address pin of MASKROM array; One among the control line SLCTIN of parallel interface and the AUTOFD connects the output permission pin of timing control unit and switching logic unit and the input control end of chip selection logic unit, another root connects the input of timing control unit as clock signal, and the condition line of parallel interface connects the output of switching logic unit; Latching control pin and exporting of the output ground connection location latch units of timing control unit allows pin; The output of address latch unit connects the address input end of MASKROM array and the signal input part of chip selection logic unit; The output of chip selection logic unit connects the chip select pin of MASKROM array; The data output of MASKROM array connects the input of switching logic unit.

The data line of main frame by parallel interface sent the address signal of the MASKROM array of middle and high, low three bytes successively to this Chinese Card, and the address signal of middle and high byte is latched in the address latch unit; This aft engine sends control command through the control line of parallel interface, by sequential control and chip selection logic unit, address signal is beated among the MASKROM array of choosing, therefrom select font data and deliver to switching logic unit, last main frame is fetched the font data of switching logic unit output from the condition line of parallel interface.By means of parallel interface, main frame just can send address and the action of fetching data, thereby has realized the visit to external Chinese Card.

Below in conjunction with drawings and Examples the utility model is described in detail.

Fig. 1 is a circuit composition frame chart of the present utility model;

Fig. 2 is the circuit diagram of an embodiment of the utility model;

Fig. 3 is the address latch sequential chart in the utility model.

Universal Chinese card for computer shown in Figure 1 by guard shield, power supply (all not drawing among the figure), be contained in MASKROM array 1 on the printed substrate, SECO 2, address latch 3, array chip selection logic 4, switch logic 5, the plug and the lead-in wire that match with host parallel interface 6 form. Wherein: the data wire ground connection location of parallel interface 6 latchs 3 and the input of switch logic 5 and the address pin of MASKROM array 1; One of the control line SLCTIN of parallel interface 6 and AUTOFD connect the output permission pin of SECO 2 and switch logic 5 and the input control end of chip selection logic 4, another root connects the input of SECO 2 as clock signal, and the condition line of parallel interface 6 connects the output of switch logic 5; The output ground connection location of SECO 2 latch 3 latch control pin and output allows pin; The output of address latch 3 connects the MASKROM array The signal input part of address input end and chip selection logic 4; The output of chip selection logic 4 connects the chip select pin of MASKROM array; The data output of MASKROM array connects the input of switch logic 5.

Fig. 2 is the circuit diagram of an embodiment of the utility model, wherein:

Sequential control 2, address latch 3, chip selection logic 4 and switch logic 5 all constitute with GAL16V8; Address latch 3 by in eight bit address latchs 9 and high eight-bit address latch 10 form; Parallel interface 6 is standard parallel interface CENTRONIX;

The MASKROM array adopts four word-base chips 8 that model is AKN624017P, its address pin A0～A5 and D/A pin connect the data line of parallel interface 6, output pin F7～the F0 of eight bit address latchs 9 during its address pin A6～A13 connects, its address pin A14～A19 meets the output pin F7～F2 of high eight-bit address latch 10, its output allow pin and chip select pin and connect after be connected to the CS output pin of chip selection logic 4, its data pin meets the input pin I0～I7 of switch logic 5;

The control line AUTOFD of parallel interface 6 connects the I0 pin of sequential control 2 as clock signal, control line SLCTIN meets the OE pin of sequential control 2 and switch logic 5 and the input pin I3 of chip selection logic 4, the control signal that D0 line in the data line is imported according to selection as high and low four figures meets the input pin I8 of switch logic 5, and its condition line ACK, PE, BUSY and SLCT meet the output pin F5～F2 of switch logic 5 respectively;

The chip select pin OE of eight bit address latchs 9 and high eight-bit address latch 10 during the F5 pin of sequential control 2 connects, eight bit address latchs 9 and high eight-bit address latch 10 latched control pin I8 during F3 and F2 pin connect respectively;

The output pin F0 of high eight-bit address latch 10 and F1 select the input pin I6 and the I7 of logic 4 as the sheet selected control system signal contact pin of MASKROM array 1.

In addition, still have the function of parallel interface for making external Hanzi board, the standard parallel interface 11 of expansion also is housed on printed-wiring board (PWB), the state pin ACK of this interface, PE, BUSY, SLCT meet input pin F7, F1, F6 and the F0 of switch logic 5 respectively.All the other pin are corresponding one by one continuous with the plug of host parallel interface 6.

Following its principle of work of surface analysis:

Parallel interface data when output SLCTIN is always low, thereby the gating Chinese Card carries out data transmission and suits somebody to a T when being high with SLCTIN.Data transmission finishes and is returned to low level, and condition line is returned system.The Chinese character base data reach 8MB, total address space needs 23 address wires with byte addressing, in the data input of reality, do the data input for unit with nibble (4Bit), therefore the address must address with nibble, so also must increase an address wire, so actual address wire needs 24, these addresses must cutting be high, medium and low respectively 8 latch respectively in order, this just need send time clock with program and be controlled.AUTOFD is a signal of having degenerated, therefore available it make clock cable.When SLCTIN is sent to the signal of state mouth from external unit during for low level; The signal that is sent to the state mouth as SLCTIN during for high level is the font data of reading from Mask ROM array, transmits low four or high four with the D0 line decision of data port.

Behind the computing machine gating Chinese Card, at first be ready to the address date of Chinese character base font, the state of latch control signal is set by control line SLCTIN and AUTOFD, simultaneously condition line is switched on the Chinese character base data line, export the address date of Chinese character base font from the data line of parallel interface 6 by order middle and high, low byte then.

With reference to Fig. 3, the initial SLCTIN of order is low, and after main frame sent first clock, the output F2 of sequential control 2 and F3 pin were that LH and LM are low, and main frame makes that SLCTIN is high then, the gating external Hanzi board; Send out byte address middle, it is high that second clock makes F3, during middle byte address is latched in the eight bit address latchs 9; Then send out high byte address and the 3rd clock, with the high byte address latch in high eight-bit address latch 10; After this send out the low byte address again.The highest two translate the chip selection signal of MASKROM array 1 through chip selection logic 4 in the high address, choose certain sheet word-base chip 8, and the font data of so just taking out a byte from word-base chip is sent to the input end pin of switch logic 5.This font data needs at twice from switch logic 5 outputs, and when the D0 position in the low byte address was 0, low four of output word graphic data were to export high four at 1 o'clock.The font data of output is read by main frame through the condition line of parallel interface 6.The operation of main frame by sending the address and fetching data so just realized the visit to external Hanzi board.

When SLCTIN is high, one of four states line ACK, PE, BUSY, SLCT that switch logic 5 will be expanded parallel interface 11 export as input, the corresponding state line that is about to these condition lines and parallel interface 6 is connected, and makes external Hanzi board recover the function of parallel interface.

Because external Hanzi board uses existing parallel interface, an expansion parallel interface is provided simultaneously, therefore external Hanzi board can both be worked simultaneously with the equipment that is inserted in its expansion parallel interface, external Hanzi board neither takies expansion slot, do not take other system resource yet, needn't consider the compatibility of bus; Because external Hanzi board is external, therefore needn't open cabinet, general people does not need special training to install and use.

The utility model operation result on 386 machines of 33MHz shows: transfer rate can reach more than the 120KB/S.

Claims (3)

1, the computer general-purpose external Hanzi board has shell, power supply, is contained in the MASKROM array (1) on the printed-wiring board (PWB), it is characterized in that on the printed-wiring board (PWB) also having sequential control (2), address latch (3), array chip selection logic (4), switch logic (5), with plug and lead-in wire that host parallel interface (6) matches, wherein: the input of (3) and switch logic (5) and the address pin of MASKROM array (1) are latched in the data line ground connection location of parallel interface (6); One of the control line SLCTIN of parallel interface (6) and AUTOFD connect the output permission pin of sequential control (2) and switch logic (5) and the input control end of chip selection logic (4), another root connects the input of sequential control (2) as clock signal, and the condition line of parallel interface (6) connects the output of switch logic (5); Latching control pin and exporting the permission pin of (3) latched in the output ground connection location of sequential control (2); The output of address latch (3) connects the address input end of MASKROM array (1) and the signal input part of chip selection logic (4); The output of chip selection logic (4) connects the chip select pin of MASKROM array (1); The data output of MASKROM array (1) connects the input of switch logic (5).

2, according to right 1 described computer general-purpose external Hanzi board, it is characterized in that: said parallel interface (6) is standard parallel interface CENTRONIX; Extension standards parallel interface (11) also is housed on the said printed-wiring board (PWB), and the state pin ACK of this interface, PE, BUSY, SLCT connect the input of said switch logic (5), and all the other pin are corresponding one by one continuous with the plug of host parallel interface (6).

3, according to right 2 described computer general-purpose external Hanzi boards, it is characterized in that:

Said sequential control (2), address latch (3), chip selection logic (4) and switch logic (5) all constitute with GAL16V8; Said address latch (3) by in eight bit address latchs (9) and high eight-bit address latch (10) form;

Said MASKROM array (1) adopts four AKN624017P(8), its address pin A0～A5 and D/A pin connect the data line of said parallel interface (6), output pin F7～the F0 of eight bit address latchs (9) during its address pin A6～A13 connects, its address pin A14～A19 meets the output pin F7～F2 of high eight-bit address latch (10), its output allows pin and chip select pin and connects back CS output pin with chip selection logic (4) to join, and its data pin meets the input pin I0～I7 of switch logic (5);

The control line AUTOFD of said parallel interface (6) connects the I0 pin of sequential control (2) as clock signal, control line SLCTIN meets the OE pin of sequential control (2) and switch logic (5) and the input pin I3 of chip selection logic (4), a control signal of importing according to selection as high and low four figures in its data line meets the input pin I8 of switch logic (5), and its condition line ACK, PE, BUSY and SLCT meet the output pin F5～F2 of switch logic (5) respectively;

The chip select pin OE of eight bit address latchs (9) and high eight-bit address latch (10) during the F5 pin of said sequential control (2) connects, eight bit address latchs (9) and high eight-bit address latch (10) latched control pin I8 during F3 and F2 pin connect respectively;

The output pin F1 of said high eight-bit address latch (10) and F0 as the sheet selected control system signal of MASKROM array (1) respectively contact pin select the input pin I6 and the I7 of logic (4);

State pin ACK, PE, BUSY and the SLCT of said expansion parallel interface (11) meets input pin F7, F1, F6 and the F0 of switch logic (5) respectively.

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