CN217386635U - Drive circuit and display panel - Google Patents
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- CN217386635U CN217386635U CN202220908593.1U CN202220908593U CN217386635U CN 217386635 U CN217386635 U CN 217386635U CN 202220908593 U CN202220908593 U CN 202220908593U CN 217386635 U CN217386635 U CN 217386635U
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Abstract
The application provides a driving circuit and a display panel. The driving circuit comprises a plurality of pixel circuit arrays, wherein each pixel circuit array comprises a row of pixel circuits, the pixel circuit arrays comprise a second pixel circuit array and a third pixel circuit array adjacent to the second pixel circuit array, and the pixel circuits in the second pixel circuit array are connected to a second data voltage line; the pixel circuits in the third pixel circuit array are connected to a third data voltage line; the second data voltage line and the third data voltage line extend in a first direction; and the third data voltage line and the second data voltage line are at least partially overlapped along a second direction, wherein an included angle between the second direction and the first direction is 70-110 degrees. Therefore, the second data voltage line and the third data voltage line are at least partially overlapped in the second direction, so that the phase gap between the two pixel circuit arrays can be reduced, and the PPI of the display panel can be improved.
Description
Technical Field
The application relates to the technical field of display, in particular to a driving circuit and a display panel.
Background
With the continuous development of scientific technology, display devices such as mobile phones, computers, televisions and the like are widely applied in the life of people. A display device is usually provided with a display panel, and the current display panel has a low pixel density (PPI) due to the unreasonable layout of the driving circuit.
SUMMERY OF THE UTILITY MODEL
An object of the embodiments of the present application is to provide a driving circuit and a display panel, which are used to solve the problem of low pixel density of the display panel in the prior art.
A first aspect of the embodiments of the present application provides a driving circuit, where the driving circuit includes a plurality of pixel circuit arrays, where each pixel circuit array includes a row of pixel circuits;
the plurality of pixel circuit arrays includes a second pixel circuit array and a third pixel circuit array adjacent to the second pixel circuit array, wherein,
the pixel circuits in the second pixel circuit array are connected to a second data voltage line;
the pixel circuits in the third pixel circuit array are connected to a third data voltage line;
the second data voltage line and the third data voltage line extend in a first direction; and the number of the first and second groups,
the third data voltage line and the second data voltage line are at least partially overlapped along a second direction, wherein an included angle between the second direction and the first direction is 70-110 degrees.
In an embodiment, an isolation layer is disposed between the third data voltage line and the second data voltage line along a thickness direction of the driving circuit.
In one embodiment, the thickness of the isolation layer is 0 to 4 μm.
In an embodiment, the driving circuit further includes a first pixel circuit array, wherein the first pixel circuit array is adjacent to the second pixel circuit array.
In an embodiment, the pixel circuits in the first pixel circuit array and the pixel circuits in the second pixel circuit array are connected to a same anode voltage line.
In one embodiment, the pixel circuits in the first pixel circuit array and the pixel circuits in the second pixel circuit array are spaced apart by 0-8 μm.
In one embodiment, the pixel circuits in the first pixel circuit array are connected to a first anode voltage line;
the pixel circuits in the second pixel circuit array are connected to a second anode voltage line, wherein the first anode voltage line and the second anode voltage line are different anode voltage lines;
the first anode voltage line and the second anode voltage line extend in a first direction;
the first anode voltage line and the second anode voltage line at least partially overlap along a second direction.
In an embodiment, a second isolation layer is disposed between the first anode voltage line and the second anode voltage line along a thickness direction of the driving circuit.
In one embodiment, the thickness of the second isolation layer is 0 to 4 μm.
In a second aspect of the embodiments of the present application, a display panel is provided, which includes the driving circuit provided in the embodiments of the present application.
By adopting the driving circuit provided by the embodiment of the application, the driving circuit comprises a plurality of pixel circuit arrays, wherein each pixel circuit array comprises a row of pixel circuits, the plurality of pixel circuit arrays comprise a second pixel circuit array and a third pixel circuit array adjacent to the second pixel circuit array, and the pixel circuits in the second pixel circuit array are connected to a second data voltage line; the pixel circuits in the third pixel circuit array are connected to a third data voltage line; the second data voltage line and the third data voltage line extend in a first direction; and the third data voltage line and the second data voltage line are at least partially overlapped along a second direction, wherein an included angle between the second direction and the first direction is 70-110 degrees. Therefore, the second data voltage line and the third data voltage line are at least partially overlapped in the second direction, so that the phase gap between the two pixel circuit arrays can be reduced, and the PPI of the display panel can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a driving circuit in the prior art;
fig. 2 is a top view of a driving circuit according to an embodiment of the present disclosure;
fig. 3 is a front view of a driving circuit provided in an embodiment of the present application;
fig. 4 is a top view of a driving circuit according to another embodiment of the present application;
FIG. 5 is a front view of a driver circuit provided in another embodiment of the present application;
FIG. 6 is a top view of a driving circuit according to another embodiment of the present application;
FIG. 7 is a front view of a driver circuit provided in another embodiment of the present application;
FIG. 8 is a top view of a driving circuit according to another embodiment of the present application;
fig. 9 is a front view of a driving circuit according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the present application, terms such as "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying a relative importance or order.
As described above, with the continuous development of scientific technology, display devices such as mobile phones, computers, televisions, and the like are widely used in the lives of people. The display device is usually provided with a display panel, and the current display panel has a low PPI due to the unreasonable layout of the driving circuit.
For example, as shown in fig. 1, a layout of signal lines in a driving circuit of a conventional display panel is shown, the driving circuit 10 includes a plurality of rows of pixel circuits 11, and each row of pixel circuits 11 is connected to a different signal line 12, at this time, in order to ensure that an aperture ratio meets a requirement, a relatively large gap needs to be maintained between each row of pixel circuits 11, which results in an unreasonable layout of the driving circuit and a low PPI of the display panel. The signal line 12 may be an anode voltage line (ELVDD) or a data voltage line.
Based on this, embodiments of the present application provide a driving circuit and a display panel, which can be used to solve the problems in the prior art. In combination with the top view of the driving circuit 20 in fig. 2 and the front view of the driving circuit 20 in fig. 3, the driving circuit 20 includes a plurality of pixel circuit arrays 21, and each pixel circuit array 21 includes a row of pixel circuits. For example, the driving circuit 20 may include 3, 4, 5 or other numbers of pixel circuit arrays 21, each of which includes a row of pixel circuits, wherein the row may refer to a row or a column.
In practical applications, there may be a plurality of pixel circuits 211 in each row of pixel circuits, for example, a plurality of pixel circuits 211 may be grouped into a row, so as to obtain the pixel circuit.
It should be noted that the plurality of pixel circuit arrays 21 of the driving circuit 20 includes a first pixel circuit array and a second pixel circuit array, where the second pixel circuit array 21B is adjacent to the first pixel circuit array 21A. For convenience of explanation, the first pixel circuit array will be referred to as a first pixel circuit array 21A, and the second pixel circuit array will be referred to as a second pixel circuit array 21B.
In addition, the pixel circuits 211 in the first pixel circuit array 21A and the pixel circuits 211 in the second pixel circuit array 21B are connected to the same anode voltage line 22. For example, as shown in fig. 2, the plurality of pixel circuit arrays 21 of the driving circuit 20 includes two adjacent pixel circuit arrays 21, which are respectively referred to as a first pixel circuit array 21A and a second pixel circuit array 21B, the pixel circuits 211 in the two pixel circuit arrays 21 are connected to the same anode voltage line 22, therefore, when the two pixel circuit arrays 21 are laid out, compared with the prior art in which anode voltage lines are respectively laid out for the two pixel circuit arrays, the layout manner of the embodiment of the present application reduces the laying out of one anode voltage line, therefore, under the condition of the same aperture ratio requirement, the phase gap between the two pixel circuit arrays (i.e. the first pixel circuit array 21A and the second pixel circuit array 21B) can be reduced, therefore, the layout of the anode voltage lines 22 in the driving circuit 20 is more reasonable, and the PPI of the display panel can be improved.
As shown in fig. 3, in general, the distance d between the pixel circuit 211 in the first pixel circuit array 21A and the pixel circuit 211 in the second pixel circuit array 21B may be greater than 0 and less than or equal to 8 μm. For example, the spacing d may be 2 μm, 3 μm, 5 μm, 8 μm, or other values.
In practical applications, the driving circuit 20 may further include a substrate, and the pixel circuit arrays 21 in the driving circuit 20 may be arranged in an array on the substrate.
In one embodiment, another driving circuit may also be provided. Fig. 4 is a top view of the driving circuit 20, and fig. 5 is a front view of the driving circuit 20. In this driving circuit 20, the pixel circuits 211 in the first pixel circuit array 21A may also be connected to the first data voltage line 23, thereby supplying the data voltage (Vdata) to the pixel circuits 211 in the first pixel circuit array 21A through the first data voltage line 23; and the pixel circuits 211 in the second pixel circuit array 21B may also be connected to the second data voltage line 24 so that the data voltage is supplied to the pixel circuits 211 in the second pixel circuit array 21B through the second data voltage line 24.
In one embodiment, another driving circuit may also be provided. Fig. 6 is a top view of the driving circuit 20, and fig. 7 is a front view of the driving circuit 20. The pixel circuit array 21 in the driving circuit 20 further includes a third pixel circuit array 21C, the third pixel circuit array 21C is adjacent to the second pixel circuit array 21B, and the pixel circuits 211 in the third pixel circuit array 21C are connected to the third data voltage line 25.
It should be noted that the second data voltage line 24 and the third data voltage line 25 extend along a first direction (i.e., Y direction shown in fig. 6), and the first direction is also a direction in which the pixel circuits 211 in each pixel circuit array 21 are generally laid out and extended according to the requirements of the display panel layout. In addition, the third data voltage line 25 and the second data voltage line 24 at least partially overlap in the second direction (i.e., the X direction shown in fig. 6), for example, may partially overlap or may completely overlap. Wherein, the included angle between the second direction and the first direction is 70 degrees to 110 degrees, such as 70 degrees, 80 degrees, 90 degrees, 100 degrees, 110 degrees or other values; of course, the second direction and the first direction may also be perpendicular or substantially perpendicular to each other, i.e. the included angle between the two directions is about 90 degrees, such as 85-95 degrees.
In this way, by at least partially overlapping the third data voltage line 25 and the second data voltage line 24 along the second direction, the gap between the second pixel circuit array 21B and the third pixel circuit array 21C can be further reduced under the condition that the aperture ratio meets the requirement, the layout of the driving circuit 20 is further optimized, and the PPI of the display panel is further improved.
In practical applications, in order to reduce mutual interference of the data voltages between the third data voltage line 25 and the second data voltage line 24, an isolation layer 26 may be further disposed between the third data voltage line 25 and the second data voltage line 24 along the thickness direction of the driving circuit 20, so that the third data voltage line 25 and the second data voltage line 24 are isolated by the isolation layer 26. For example, the third data voltage line 25 and the second data voltage line 24 may be disposed at different heights (e.g., disposed at different layers) in a thickness direction of the driving circuit 20, and separated by the disposed isolation layer 26.
The isolation layer 26 may be made of an insulating material in general, and in order to avoid an excessive thickness of the driving circuit 20, the thickness of the isolation layer 26 may be greater than 0 and less than or equal to 4 μm, for example, 2 μm, 3 μm, 4 μm, or the like.
In the embodiment of the present application, the same anode voltage line 22 is shared by the pixel circuits between the first pixel circuit array 21A and the second pixel circuit array 21B, so that one anode voltage line is reduced compared to the prior art, thereby reducing a gap between the first pixel circuit array 21A and the second pixel circuit array 21B, and further improving the PPI of the display panel. Between the second pixel circuit array 21B and the third pixel circuit array 21C, the gap between the second pixel circuit array 21B and the third pixel circuit array 21C can be reduced by at least partially overlapping the third data voltage line 25 and the second data voltage line 24 along the second direction, so as to improve the PPI of the display panel. In practical applications, one of the two ways may be adopted, or the two ways may be combined, so as to improve the PPI of the display panel.
For example, in a practical driving circuit, a certain pixel circuit array may be used as the first pixel circuit array 21A, and a pixel circuit array adjacent to the certain pixel circuit array may be used as the second pixel circuit array 21B, so that the pixel circuits of the two pixel circuit arrays share the same anode voltage line, and the pixel circuit array adjacent to the other side of the second pixel circuit array 21B is used as the third pixel circuit array 21C, so that the third data voltage line 25 and the second data voltage line 24 at least partially overlap along the second direction; and, the third pixel circuit array 21C is further used as a new first pixel circuit array 21A, the pixel circuit array adjacent to the other side of the third pixel circuit array 21C is used as a new second pixel circuit array 21B, and the new first pixel circuit array 21A and the new second pixel circuit array 21B share the same anode voltage line, and so on, thereby realizing optimization of the driving circuit layout and improving the PPI of the display panel.
Two ways for optimizing the layout of the driving circuit are mentioned above, which are respectively a way one: pixel circuits in the first pixel circuit array 21A sharing the same anode voltage line with pixel circuits in the second pixel circuit array 21B; in the second mode, the third data voltage line 25 and the second data voltage line 24 are at least partially overlapped in the second direction between the second pixel circuit array 21B and the third pixel circuit array 21C. It should be further noted that, in this embodiment of the application, the following manner three may be further adopted to optimize the layout of the driving circuit in the display panel, so as to improve the PPI of the display panel. In addition, as for the contents of the third mode, if there is no ambiguity, the contents of the first mode and the second mode can be referred to.
For convenience of description, the first pixel circuit array, the second pixel circuit array, the third pixel circuit array, and the like are used continuously, but terms such as "first", "second", "third", and the like are only used for distinguishing the three, and cannot be understood as indicating or implying relative importance or order.
It is possible to combine the top view of the driving circuit 30 shown in fig. 8 with the front view of the driving circuit 30 shown in fig. 9. The driving circuit 30 may include a plurality of pixel circuit arrays, and each of the pixel circuit arrays includes a row of pixel circuits.
The plurality of pixel circuit arrays in the driving circuit 30 includes a first pixel circuit array 31A and a second pixel circuit array 31B, and the second pixel circuit array 31B is adjacent to the first pixel circuit array 31A. The pixel circuits in the first pixel circuit array 31A are connected to a first anode voltage line 32A, the pixel circuits in the second pixel circuit array 31B are connected to a second anode voltage line 32B, the first anode voltage line 32A and the second anode voltage line 32B extend along a first direction (Y direction in fig. 8), and the first anode voltage line 32A and the second anode voltage line 32B at least partially overlap along a second direction (X direction in fig. 8), wherein an included angle between the second direction and the first direction is 70 degrees to 110 degrees, such as 70 degrees, 80 degrees, 90 degrees, 100 degrees, 110 degrees, or other values. The first anode voltage line and the second anode voltage line are different anode voltage lines.
Of course, the second direction and the first direction may also be perpendicular or substantially perpendicular to each other, i.e. the included angle between the two directions is about 90 degrees, such as 85-95 degrees.
The first and second anode voltage lines 32A and 32B may overlap partially or completely.
Of course, in order to reduce the mutual interference of the anode voltages between the first anode voltage line 32A and the second anode voltage line 32B, an isolation layer (referred to as a second isolation layer) may be provided between the first anode voltage line 32A and the second anode voltage line 32B along the thickness direction of the driving circuit 30. For example, the first anode voltage line 32A and the second anode voltage line 32B are disposed at different heights in the thickness direction of the driving circuit 30, and a second isolation layer is disposed therebetween for isolation. It is also possible for the second isolation layer to be made of an insulating material, and to avoid an excessive thickness of the driving circuit, it is also possible for the thickness of the second isolation layer to be greater than 0 and less than or equal to 4 μm, for example, 2 μm, 3 μm, 4 μm, or the like.
The difference from the first embodiment is that in the third embodiment, the pixel circuits in the first pixel circuit array 31A and the pixel circuits in the second pixel circuit array 31B do not share the same anode voltage line, but are respectively connected to the first anode voltage line 32A and the second anode voltage line 32B, and the gap between the first pixel circuit array 31A and the second pixel circuit array 31B is reduced by at least partially overlapping the first anode voltage line 32A and the second anode voltage line 32B along the second direction, thereby increasing the PPI of the display panel.
And the third mode and the first mode or the second mode may also be combined, for example, the third mode and the second mode are combined, in this case, the plurality of pixel circuit arrays in the driving circuit 30 further includes a third pixel circuit array, and the third pixel circuit array is adjacent to the second pixel circuit array 31B.
The pixel circuits in the first pixel circuit array 31A are connected to a first data voltage line, the pixel circuits in the second pixel circuit array 31B are connected to a second data voltage line, and the pixel circuits in the third pixel circuit array are connected to a third data voltage line. The second and third data voltage lines also extend in the first direction Y, and the third and second data voltage lines also at least partially overlap in the second direction.
Of course, in order to reduce the mutual interference of the data voltages between the third data voltage line and the second data voltage line, an isolation layer may be disposed between the third data voltage line and the second data voltage line along the thickness direction of the driving circuit 30, so that the third data voltage line and the second data voltage line are isolated by the isolation layer. For example, the third data voltage line and the second data voltage line may be disposed at different heights (e.g., disposed on different layers) along the thickness direction of the driving circuit 30, and the third data voltage line and the second data voltage line may be isolated from each other by the disposed isolation layer.
In practical applications, in order to optimize the overall structure of the driving circuit, a certain pixel circuit array may be used as the first pixel circuit array 31A, and a pixel circuit array adjacent to the pixel circuit array may be used as the second pixel circuit array 31B, wherein the pixel circuits in the first pixel circuit array 31A are connected to the first anode voltage line 32A, the pixel circuits in the second pixel circuit array 31B are connected to the second anode voltage line 32B, the first anode voltage line 32A and the second anode voltage line 32B extend along the first direction, and the first anode voltage line 32A and the second anode voltage line 32B at least partially overlap along the second direction.
Further, the pixel circuit array adjacent to the other side of the second pixel circuit array 31B may be used as a third pixel circuit array, and the third data voltage line and the second data voltage line may also at least partially overlap along the second direction; and then, taking the third pixel circuit array as a new first pixel circuit array, taking the pixel circuit array adjacent to the other side of the third pixel circuit array as a new second pixel circuit array, further enabling anode voltage lines respectively connected with the new first pixel circuit array and the new second pixel circuit array to at least partially overlap along a second direction, and so on, thereby realizing the optimization of the whole layout of the driving circuit and improving the PPI of the display panel.
Based on the driving circuit provided in the embodiment of the present application, an embodiment of the present application can also provide a display panel, where the display panel includes any one of the pixel circuits provided in the embodiment of the present application, so that the problems in the prior art can also be solved, and details thereof are not repeated here. In practical applications, the display panel may further include a protective case, an external power source, and the like, which are not described one by one.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. A driving circuit is characterized by comprising a plurality of pixel circuit arrays, wherein each pixel circuit array comprises a row of pixel circuits;
the plurality of pixel circuit arrays includes a second pixel circuit array and a third pixel circuit array adjacent to the second pixel circuit array, wherein,
the pixel circuits in the second pixel circuit array are connected to a second data voltage line;
the pixel circuits in the third pixel circuit array are connected to a third data voltage line;
the second data voltage line and the third data voltage line extend in a first direction; and the number of the first and second groups,
the third data voltage line and the second data voltage line are at least partially overlapped along a second direction, wherein an included angle between the second direction and the first direction is 70-110 degrees.
2. The driving circuit according to claim 1, wherein an isolation layer is provided between the third data voltage line and the second data voltage line in a thickness direction of the driving circuit.
3. The driving circuit according to claim 2, wherein the thickness of the isolation layer is 0 to 4 μm.
4. The driver circuit of claim 1, wherein the driver circuit comprises a first pixel circuit array, wherein the first pixel circuit array is adjacent to the second pixel circuit array.
5. The driving circuit according to claim 4, wherein the pixel circuits in the first pixel circuit array and the pixel circuits in the second pixel circuit array are connected to the same anode voltage line.
6. The driving circuit according to claim 5, wherein a pitch between the pixel circuits in the first pixel circuit array and the pixel circuits in the second pixel circuit array is 0 to 8 μm.
7. The drive circuit of claim 4,
the pixel circuits in the first pixel circuit array are connected to a first anode voltage line;
the pixel circuits in the second pixel circuit array are connected to a second anode voltage line, wherein the first anode voltage line and the second anode voltage line are different anode voltage lines;
the first anode voltage line and the second anode voltage line extend in a first direction;
the first anode voltage line and the second anode voltage line at least partially overlap along a second direction.
8. The drive circuit according to claim 7, wherein a second spacer is provided between the first anode voltage line and the second anode voltage line in a thickness direction of the drive circuit.
9. The driving circuit according to claim 8, wherein the second isolation layer has a thickness of 0 to 4 μm.
10. A display panel comprising a driver circuit as claimed in any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220908593.1U CN217386635U (en) | 2022-04-19 | 2022-04-19 | Drive circuit and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220908593.1U CN217386635U (en) | 2022-04-19 | 2022-04-19 | Drive circuit and display panel |
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| Publication Number | Publication Date |
|---|---|
| CN217386635U true CN217386635U (en) | 2022-09-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220908593.1U Active CN217386635U (en) | 2022-04-19 | 2022-04-19 | Drive circuit and display panel |
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| CN (1) | CN217386635U (en) |
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- 2022-04-19 CN CN202220908593.1U patent/CN217386635U/en active Active
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