CN217360174U - Chip testing device - Google Patents
Chip testing device Download PDFInfo
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- CN217360174U CN217360174U CN202220191637.3U CN202220191637U CN217360174U CN 217360174 U CN217360174 U CN 217360174U CN 202220191637 U CN202220191637 U CN 202220191637U CN 217360174 U CN217360174 U CN 217360174U
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Abstract
The utility model discloses a chip testing device, include the mainboard and be used for installing the chip mounting panel by the test chip, be equipped with mount pad, treater unit and display element on the mainboard, the connection can be dismantled to chip mounting panel and mount pad, treater unit loops through mount pad and chip mounting panel and is connected with the chip under test, treater unit still with the display element is connected. The utility model discloses a connection can be dismantled to chip mounting panel and mainboard, only need design the chip mounting panel that corresponds to different chips, and can follow the display element and read the test result to the realization is tested the chip of different models, and does not come the direct display test result through the host computer.
Description
Technical Field
The utility model relates to a chip test field especially relates to a chip testing device.
Background
In order to avoid the problem that the integrated circuit has problems because a fault chip is welded on the integrated circuit, manpower and material resources are consumed for repairing. Chips are generally tested before being mounted on an integrated circuit, and current chip testing equipment can only test a specific chip, but the integrated circuit often comprises a plurality of chips, so that the chips can be tested by the plurality of chip testing equipment. In addition, the current chip testing equipment needs to read the testing result through an upper computer.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem who solves: the chip testing device can test chips of different models and can directly display a testing result.
In order to solve the technical problem, the utility model discloses a technical scheme be:
the utility model provides a chip testing device, includes mainboard and the chip mounting panel that is used for the installation to be tested the chip, be equipped with mount pad, treater unit and display element on the mainboard, the connection can be dismantled to chip mounting panel and mount pad, treater unit loops through mount pad and chip mounting panel and is connected with the chip under test, treater unit still with display element connects.
Furthermore, the display unit comprises LED lamps in one-to-one correspondence with pins of the tested chip, the chip mounting plate is provided with pins in one-to-one correspondence with the pins of the tested chip, the mounting base comprises jacks in one-to-one correspondence with the pins, and the pins are inserted into the corresponding jacks and sequentially pass through the corresponding jacks and the processor unit to be electrically connected with the corresponding LED lamps.
Furthermore, a voltage conversion unit and a first on-off control unit are further arranged on the mainboard, the input end of the voltage conversion unit is connected with an external power supply through the first on-off control unit, the output end of the voltage conversion unit is connected with the power supply end of the processor unit, and the output end of the voltage conversion unit is further connected with the power supply end of the tested chip through the chip mounting plate.
Furthermore, a driving unit is further arranged on the main board, and the processor unit is connected with the display unit through the driving unit to increase the driving capability of the processor unit.
Further, still be equipped with data conversion unit and TYPE C interface on the mainboard, the TYPE C interface passes through data conversion unit and processor unit to be connected.
Furthermore, a second on-off control unit is arranged between the data conversion unit and the processor unit.
Furthermore, still be equipped with first debugging interface and second debugging interface on the mainboard, first debugging interface is connected with the debugging end of processor unit, the second debugging interface passes through the chip mounting panel and is connected with the debugging end of being tested the chip.
Furthermore, the main board is further provided with a first clock unit, and the first clock unit is connected with a clock end of the processor unit.
Furthermore, a chip seat and a second clock unit are arranged on the chip mounting plate, and the second clock unit is connected with the clock end of the tested chip through the chip seat.
Furthermore, the display unit further comprises a chip power indicator lamp, and the chip power indicator lamp is connected with the power supply end of the tested chip through a chip seat.
Compared with the prior art, the utility model has the advantages of as follows:
1. the utility model discloses a connection can be dismantled to chip mounting panel and mainboard, consequently only need design the chip mounting panel that corresponds to different chips, and keep the mainboard unchangeable to the cost has been practiced thrift to the different types of chip test of integrated circuit, in addition the utility model discloses still set up the display element on the mainboard, thereby can the direct indication test result, and need not acquire at the host computer.
2. The utility model discloses a display element adopts and the LED lamp by the pin one-to-one of test chip to the cost has been practiced thrift, and can know the test condition of every pin directly perceived, and the pin of the chip existing problem that can pinpoint the trouble.
Drawings
Fig. 1 is a structural diagram of an embodiment of the present invention.
Fig. 2 is a circuit block diagram of an embodiment of the present invention.
Illustration of the drawings: 1-mainboard, 2-chip mounting board, 11-mounting seat, 12-processor unit, 13-display unit, 14-voltage conversion unit, 15-first on-off control unit, 16-driving unit, 17-data conversion unit, 18-second on-off control unit, 19-first clock unit, 21-chip seat, 22-second clock unit and 101-chip power indicator lamp.
Detailed Description
The invention will be further described with reference to the drawings and specific preferred embodiments without limiting the scope of the invention.
As shown in fig. 1 and fig. 2, the present embodiment provides a chip testing apparatus, which includes a motherboard 1 and a chip mounting board 2 for mounting a chip to be tested, where the motherboard 1 is provided with a mounting base 11, a processor unit 12 and a display unit 13, the chip mounting board 2 and the mounting base 11 are detachably connected, the processor unit 12 is connected to the chip to be tested sequentially through the mounting base 11 and the chip mounting board 2, and the processor unit 12 is further connected to the display unit 13, so that the display unit 13 is controlled to display.
Through the structure, the processor unit 12 interacts with the tested chip, and simultaneously controls the display unit 3 to display corresponding information according to the condition of the tested chip, so that the chip testing device of the embodiment can directly display the testing result without acquiring the results on an upper computer, and the testing operation of the chip is simplified.
In this embodiment, through above-mentioned structure, the connection can be dismantled to chip mounting panel 2 and mainboard 1, consequently only need design corresponding chip mounting panel 2 to different chips, and keep mainboard 1 unchangeable to practice thrift the cost to the different types of chip test of integrated circuit, improved the chip testing arrangement's of this embodiment suitability.
The processor unit 12 in this embodiment is an Altera EPM240T100I5 chip, which is a CPLD chip, packaged TQFP100, and basically meets the test of pin chips below 100.
As shown in fig. 1 and 2, in this embodiment, the display unit 13 includes LED lamps corresponding to pins of the chip to be tested, the chip mounting board 2 is provided with pins corresponding to the pins of the chip to be tested, the mounting base 11 includes jacks corresponding to the pins, the pins are inserted into the corresponding jacks, and the pins are electrically connected to the corresponding LED lamps sequentially through the corresponding jacks and the corresponding pins of the processor unit 12. Through the structure, the test result displayed by the chip testing device of the embodiment corresponds to the condition of each pin of the tested chip, the test condition of each pin can be visually known, the pin with the fault of the chip can be accurately positioned, the cost is saved by adopting the LED lamp, and the service life is prolonged.
As shown in fig. 2, the main board 1 of this embodiment is further provided with a voltage conversion unit 14 and a first on-off control unit 15, an input end of the voltage conversion unit 14 is connected to an external power supply through the first on-off control unit 15, an output end of the voltage conversion unit 14 is connected to a power supply end of the processor unit 12, and an output end of the voltage conversion unit 14 is further connected to a power supply end of the chip to be tested through the chip mounting board 2.
The voltage conversion unit 14 in this embodiment includes a MAX1951ESA + chip and an RT2515HGSP chip, where the MAX1951ESA + chip may convert an external 5V power supply into 3.3V respectively to supply power to the processor unit 12, and the RT2515HGSP chip is an adjustable level conversion chip and may convert the external 5V power supply into a corresponding operating voltage according to the operating voltage of the chip to be tested to supply power to the chip to be tested.
As shown in fig. 2, in order to increase the driving capability of the processor unit 12 in consideration of more chip pins to be tested, in this embodiment, a driving unit 16 is further disposed on the main board 1, and the processor unit 12 is connected to the display unit 13 through the driving unit 16.
In this embodiment, the driving unit 16 uses an SN74HC245PW chip, which is a commonly used driver, and can enable the pins of the processor unit 12 to simultaneously operate in the output state.
As shown in fig. 2, in this embodiment, the main board 1 is further provided with a data conversion unit 17 and a TYPE C interface, and the TYPE C interface is connected to the IIC/UART interface of the processor unit 12 through the data conversion unit 17.
The data conversion unit 17 in this embodiment adopts an MCP2221A-I/ST chip, can convert IIC/UART protocol data into USB2.0 data, and can be connected to GPIO, so that an external upper computer can communicate with the processor unit 12 through the TYPE C interface.
As shown in fig. 2, in the present embodiment, a second on-off control unit 18 is further disposed between the data conversion unit 17 and the processor unit 12. The second on-off control unit 18 can control the operating mode of the processor unit 12, when the second on-off control unit 18 is turned on, the corresponding pin of the processor unit 12 operates in a serial port (IIC) mode and can communicate with an external upper computer, otherwise, the pin operates in a GPIO mode and can only interact with the driving unit 16 for data.
As shown in fig. 2, in this embodiment, the main board 1 is further provided with a first debug interface and a second debug interface, the first debug interface is connected to the debug end of the processor unit 12, and the second debug interface is connected to the debug end of the chip to be tested through the chip mounting board 2. In this embodiment, the first debug interface and the second debug interface are both JTAG interfaces, and the test program can be written into the processor unit 12 through the first debug interface, and the test program can be written into the chip to be tested through the second debug interface.
As shown in fig. 2, in this embodiment, the main board 1 is further provided with a first clock unit 19, and the first clock unit 19 is connected to the clock terminal of the processor unit 12, so as to provide a clock signal for the processor unit 12.
As shown in fig. 1 and fig. 2, in the present embodiment, a chip holder 21 and a second clock unit 22 are disposed on the chip mounting board 2, and the second clock unit 22 is connected to a clock terminal of the chip under test through the chip holder 21, so as to provide a clock signal for the chip under test. In addition, the display unit 13 further includes a chip power indicator 101, the chip power indicator 101 is connected to the power supply terminal of the chip to be tested through the mounting base 11 and the chip base 21, the normal state of the chip can be determined through the chip power indicator 101, if the chip power indicator 101 is not on after power-on, the chip to be tested has a problem of power supply, and the pin detection does not need to be continued.
The following describes the procedure of using the chip testing apparatus of the present embodiment:
firstly, a first on-off control unit 15 is switched on, the mainboard 1 is powered on, a program to be tested is written into the processor unit 12 through a first debugging interface, and the first on-off control unit 15 is switched off after the writing is finished so that the mainboard 1 is powered off;
then, the tested chip is mounted on the corresponding chip mounting plate 2, after the chip mounting plate 2 is connected with the mainboard 1, the first on-off control unit 15 is switched on to electrify the mainboard 1, if the chip power indicator light 101 is not on at the moment, the tested chip is abnormal, the first on-off control unit 15 is switched off to electrify the mainboard 1, and the test is finished; if the power indicator 101 of the test chip is lighted, a test program is written into the tested chip through the second debugging interface, after the writing is finished, the second on-off control unit 18 is switched on, the test program information is read through the upper computer for verification, and the state of the display unit 3 is observed after the verification is passed (the second on-off control unit 18 can also not be switched on, namely the state of the display unit 3 is directly observed without verification);
if all the LED lamps in the display unit 3 are lighted, the tested chip is normal, the first on-off control unit 15 is disconnected to power off the mainboard 1, the test is finished, otherwise, the tested chip is abnormal, the pin corresponding to the LED lamp which is not lighted is recorded, and the first on-off control unit 15 is disconnected to power off the mainboard 1.
The foregoing is illustrative of the preferred embodiment of the present invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments by the technical entity of the present invention should fall within the protection scope of the technical solution of the present invention.
Claims (10)
1. The utility model provides a chip testing device, its characterized in that includes mainboard (1) and is used for installing chip mounting panel (2) by the test chip, be equipped with mount pad (11), treater unit (12) and display element (13) on mainboard (1), chip mounting panel (2) and mount pad (11) can be dismantled and be connected, treater unit (12) loop through mount pad (11) and chip mounting panel (2) and are connected with the chip under test, treater unit (12) still with display element (13) are connected.
2. The chip testing device according to claim 1, wherein the display unit (13) comprises LED lamps corresponding to pins of the tested chip one to one, the chip mounting plate (2) is provided with pins corresponding to the pins of the tested chip one to one, the mounting base (11) comprises jacks corresponding to the pins one to one, and the pins are inserted into the corresponding jacks and sequentially pass through the corresponding jacks and the processor unit (12) to be electrically connected with the corresponding LED lamps.
3. The chip testing device according to claim 1, wherein a voltage conversion unit (14) and a first on-off control unit (15) are further disposed on the main board (1), an input end of the voltage conversion unit (14) is connected to an external power supply through the first on-off control unit (15), an output end of the voltage conversion unit (14) is connected to a power supply end of the processor unit (12), and an output end of the voltage conversion unit (14) is further connected to a power supply end of a chip to be tested through the chip mounting board (2).
4. The chip testing device according to claim 1, wherein a driving unit (16) is further disposed on the main board (1), and the processor unit (12) is connected to the display unit (13) through the driving unit (16) to increase the driving capability of the processor unit (12).
5. The chip testing device according to claim 1, wherein a data conversion unit (17) and a TYPE C interface are further provided on the main board (1), and the TYPE C interface is connected to the processor unit (12) through the data conversion unit (17).
6. Chip test arrangement according to claim 5, characterized in that a second on-off control unit (18) is further provided between the data conversion unit (17) and the processor unit (12).
7. The chip testing device according to claim 1, wherein the main board (1) is further provided with a first debug interface and a second debug interface, the first debug interface is connected with the debug end of the processor unit (12), and the second debug interface is connected with the debug end of the chip to be tested through the chip mounting board (2).
8. The chip testing device according to claim 1, wherein a first clock unit (19) is further disposed on the motherboard (1), and the first clock unit (19) is connected to a clock terminal of the processor unit (12).
9. The chip testing device according to claim 1, wherein a chip holder (21) and a second clock unit (22) are arranged on the chip mounting board (2), and the second clock unit (22) is connected with the clock terminal of the chip to be tested through the chip holder (21).
10. The chip testing apparatus according to claim 4, wherein the display unit (13) further comprises a chip power indicator lamp (101), and the chip power indicator lamp (101) is connected to a power supply terminal of the chip under test through a chip holder (21).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220191637.3U CN217360174U (en) | 2022-01-24 | 2022-01-24 | Chip testing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220191637.3U CN217360174U (en) | 2022-01-24 | 2022-01-24 | Chip testing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217360174U true CN217360174U (en) | 2022-09-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220191637.3U Active CN217360174U (en) | 2022-01-24 | 2022-01-24 | Chip testing device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217360174U (en) |
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- 2022-01-24 CN CN202220191637.3U patent/CN217360174U/en active Active
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