CN217282909U

CN217282909U - Charge pump circuit and phase-locked loop circuit

Info

Publication number: CN217282909U
Application number: CN202123198083.4U
Authority: CN
Inventors: 郭锐
Original assignee: Hefei Datang Storage Technology Co ltd
Current assignee: Hefei Datang Storage Technology Co ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-08-23
Anticipated expiration: 2031-12-17

Abstract

The embodiment of the utility model discloses charge pump circuit and phase-locked loop circuit, this charge pump circuit includes: the charging and discharging module is respectively connected with the PFD and the post-stage filter capacitor; the input end of the sampling control circuit is connected with the PFD result output end; the first output end of the sampling control circuit is connected with the first controlled end of the voltage sampling and holding module; the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge-discharge module through the voltage sampling and holding module; the positive input end and the negative input end of the operational amplifier are connected with the charge-discharge connecting end of the charge-discharge module; the sampling input end of the voltage sampling and holding module is connected with the voltage output end of the operational amplifier, and the bias voltage output end of the voltage sampling and holding module is connected with the bias voltage input end of the charge-discharge module. Through the scheme of the embodiment, the current mismatch problem of the current charge pump circuit is solved.

Description

Charge pump circuit and phase-locked loop circuit

Technical Field

The utility model relates to a charge pump circuit design technique, more specifically relates to a charge pump circuit and phase-locked loop circuit.

Background

A Phase Locked Loop (PLL) is an important module in a digital-to-analog hybrid circuit, and can track the phase and frequency of an input signal and output a low-jitter clock signal. It has become an essential module in special chips such as communication system, digital circuit, hard disk drive circuit and CPU.

Charge pumps are widely used in phase-locked loop circuits, and the addition of charge pumps can provide infinite loop gain and capture range for loops. In a phase locked loop circuit, a charge pump is used to convert a digital signal output from a Phase Frequency Detector (PFD) into an analog signal that controls the frequency variation of a Voltage Controlled Oscillator (VCO). The performance of the charge pump directly affects the quality of the VCO output frequency. The selection and application of the high-performance charge pump circuit play a crucial role in improving the overall performance of the PLL. The charge pump has non-ideal factors such as charge sharing (charge sharing), channel charge injection, clock feed-through, current mismatch and the like, and the performance of a charge pump phase-locked loop (CPPLL) is restricted.

One charge pump structure widely used in current engineering is shown in fig. 1, in which when S1 and S2 are opened, S3 and S4 are closed, and an operational amplifier (OPAMP) makes voltages at the X point and the Y point consistent with a voltage of Vc through a feedback action, so that a charge sharing effect of parasitic capacitances at the X point and the Y point on the voltage of Vc when S1 and S2 are closed next time is avoided, and although the charge sharing is improved, current mismatch of I1 and I2 cannot be avoided.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a charge pump circuit and phase-locked loop circuit can solve the current mismatch problem that current charge pump circuit exists.

The embodiment of the utility model provides a charge pump circuit is still provided, can include: the device comprises a charge-discharge module, an operational amplifier, a sampling control circuit and a voltage sampling holding module;

the state control end of the charge-discharge module is connected with the control output end of a preset Phase Frequency Detector (PFD), the charge-discharge connection end of the charge-discharge module is connected with the charge-discharge input end of a post-stage filter capacitor, and the output end of the filter capacitor is connected with the input end of a Voltage Controlled Oscillator (VCO);

the input end of the sampling control circuit is connected with the result output end of the PFD; the first output end of the sampling control circuit is connected with the first controlled end of the voltage sampling and holding module;

the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge-discharge module through the voltage sampling and holding module; the positive input end and the negative input end of the operational amplifier are respectively connected with different charge-discharge connection ends of the charge-discharge module

The sampling input end of the voltage sampling and holding module is connected with the voltage output end of the operational amplifier, and the bias voltage output end of the voltage sampling and holding module is connected with the bias voltage input end of the charge-discharge module.

In an exemplary embodiment of the present invention, the charging/discharging connection terminal may include: the charging and discharging circuit comprises a first charging and discharging connection end Vc and a second charging and discharging connection end Vm;

the plurality of charge and discharge paths of the charge and discharge module may include: a first charging path, a second charging path, a first discharging path and a second discharging path;

the first charging path and the first discharging path are connected with a first charging and discharging connection end Vc, and the second charging path and the second discharging path are connected with a second charging and discharging connection end Vm;

the first charge-discharge connection end Vc is connected with the negative input end of the operational amplifier, and the second charge-discharge connection end Vm is connected with the positive input end of the operational amplifier.

In an exemplary embodiment of the present invention, the charge and discharge module may include: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

a source electrode of the first P-type MOS transistor MP1 is connected to a power supply, a gate electrode thereof is used as the bias voltage input terminal, and is connected to a voltage output terminal of the operational amplifier and a voltage output terminal of the voltage sample hold module, and a drain electrode thereof is connected to a first end of the second switch S2 and a first end of the fourth switch S4, respectively;

a second end of the second switch S2 is connected to a first charge-discharge connection end Vc; a second end of the fourth switch S4 is connected to a second charge-discharge connection terminal Vm;

the first P-type MOS transistor MP1 and the second switch S2 constitute the first charging path; the first P-type MOS transistor MP1 and the fourth switch S4 constitute the second charging path;

the source of the first N-type MOS transistor MN1 is grounded, the gate is connected to a preset bias voltage Vbn, and the drain is connected to the first end of the first switch S1 and the first end of the third switch S3, respectively;

the second end of the first switch S1 is connected to the first charge-discharge connection end Vc; the second end of the third switch S3 is connected with a second charge-discharge connection end Vm;

the first N-type MOS transistor MN1 and the first switch S1 constitute the first discharge path; the first N-type MOS transistor MN1 and the third switch S3 constitute the second discharge path.

In an exemplary embodiment of the present invention, the voltage sample-and-hold module may include: a fifth switch S5 and a first capacitor; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module;

the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge and discharge module through the fifth switch S5; the first end of the fifth switch is used as the sampling input end of the voltage sampling and holding module and is connected with the voltage output end of the operational amplifier; a second end of the fifth switch is connected with a gate of the first P-type MOS transistor MP 1;

a first end of the first capacitor is used as a bias voltage output end of the voltage sample-and-hold module and is connected with the gate of the first P-type MOS transistor MP1, and a second end of the first capacitor is connected with a power supply;

and the first end of the first capacitor is used as the voltage output end of the voltage sampling and holding module and used for outputting the held bias voltage.

In an exemplary embodiment of the present invention, the sampling control circuit may include: a logic operation circuit; the logical operation circuit includes: a second AND gate;

one input end of the second and gate is set to input a first voltage upb output by the PFD and used for controlling the on-off of the fourth switch S4; the first voltage upb is used for controlling the on-off state of the second charging path; (ii) a

The other input end of the second and gate is set to input a second voltage dnb output by the PFD and used for controlling the on-off of the third switch S4; the second voltage dnb is used for controlling the on-off state of the second discharge path; (ii) a

The output end of the second and gate is used as the first output end of the sampling control circuit, is connected with the fifth switch S5, and is configured to control the opening or closing of the fifth switch S5 through the output signal of the second and gate.

In an exemplary embodiment of the present invention, the charge pump circuit may further include: an initial bias voltage providing module;

the bias voltage output end of the initial bias voltage providing module is connected with the bias voltage input end of the charge-discharge module through the voltage sampling and holding module;

the voltage sampling and holding module is further configured to control the initial bias voltage providing module to disconnect from the charge-discharge module before sampling the bias voltage of the operational amplifier.

In an exemplary embodiment of the present invention, the initial bias voltage providing module may include: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN 2;

the source electrode of the second P-type MOS transistor MP2 is connected to the power supply, and the drain electrode of the second P-type MOS transistor MP2 is connected to the gate electrode of the second P-type MOS transistor MP2 and the drain electrode of the second N-type MOS transistor MN 2;

the grid electrode of the second P-type MOS tube MP2 is used as the bias voltage output end of the initial bias voltage providing module and is connected with the bias voltage input end of the charge-discharge module;

the source electrode of the second N-type MOS transistor MN2 is grounded; the grid electrode of the second N-type MOS tube MN2 is connected with a preset bias voltage Vbn.

In an exemplary embodiment of the present invention, the voltage sample-and-hold module may include: a fifth switch S5, a sixth switch S6, and a first capacitor; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module; the controlled end of the sixth switch S6 is used as the second controlled end of the voltage sample-and-hold module;

the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge and discharge module through the fifth switch S5;

the bias voltage output end of the initial bias voltage providing module is connected with the bias voltage input end of the charge-discharge module through the sixth switch S6;

the first end of the first capacitor is connected with the bias voltage input end of the charge-discharge module, and the second end of the first capacitor is connected with a power supply VDD;

a first end of the first capacitor is used as a voltage output end of the voltage sampling and holding module and used for outputting the held bias voltage;

the gate of the second P-type MOS transistor MP2 is connected to the bias voltage input terminal of the charge-discharge module through the sixth switch.

In an exemplary embodiment of the present invention, the sampling control circuit includes: a lock detection circuit and a logical operation circuit;

the lock detection circuit may include: the device comprises a first delay unit, a second delay unit, a first trigger and a second trigger; the logical operation circuit includes: the first AND gate, the second AND gate and the first NOT gate; the difference value between the second delay time length of the second delay unit and the first delay time length of the first delay unit is a preset phase difference threshold value;

the input end of the first delay unit is set as an input reference source phase phi _ref What is, what isThe output end of the first delay unit is respectively connected with the first input end of the first trigger and the first input end of the second trigger;

the input end of the second delay unit is set as a signal phase phi obtained by inputting the feedback signal of the VCO for frequency division _div An output end of the second delay unit is connected to a second input end of the first flip-flop and a second input end of the second flip-flop respectively;

the output end of the first trigger is connected with the first input end of the first AND gate;

the output end of the second trigger is connected with the second input end of the first AND gate;

the output end of the first AND gate is connected with the first input end of the second AND gate;

a second input end of the second and gate is connected with a first result output end of the PFD, and is set to input a first voltage upb output by the PFD and used for controlling the on-off of the fourth switch S4; the first voltage upb is used for controlling the on-off state of the second charging path;

a third input end of the second and gate is connected with a second result output end of the PFD, and is set to input a second voltage dnb output by the PFD and used for controlling the on-off of the third switch S4; the second voltage dnb is used for controlling the on-off state of the second discharge path;

the output end of the second and gate is used as the first output end of the sampling control circuit, is connected with the controlled end of the fifth switch S5, and is configured to control the opening or closing of the fifth switch S5 through the output signal of the second and gate;

the input end of the first not gate is connected to the output end of the first and gate, and the output end of the first not gate is used as the second output end of the sampling control circuit and is connected to the controlled end of the sixth switch S6.

The embodiment of the utility model provides a phase-locked loop circuit is still provided, can include: the charge pump circuit of any one of the above, filter capacitance and phase frequency detector PFD connected to the charge pump circuit, voltage controlled oscillator VCO connected to the filter capacitance, and frequency divider connecting the VCO and the PFD.

The utility model discloses charge pump circuit can include: the device comprises a charge-discharge module, an operational amplifier, a sampling control circuit and a voltage sampling holding module; the state control end of the charge-discharge module is connected with the control output end of a preset Phase Frequency Detector (PFD), and the charge-discharge connection end of the charge-discharge module is connected with the charge-discharge input end of a post-stage filter capacitor; the output end of the filter capacitor is connected with the input end of the VCO; the input end of the sampling control circuit is connected with the result output end of the PFD; the first output end of the sampling control circuit is connected with the first controlled end of the voltage sampling and holding module; the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge-discharge module through the voltage sampling and holding module; the positive input end and the negative input end of the operational amplifier are respectively connected with different charge-discharge connecting ends of the charge-discharge module; the sampling input end of the voltage sampling and holding module is connected with the voltage output end of the operational amplifier, and the bias voltage output end of the voltage sampling and holding module is connected with the bias voltage input end of the charge-discharge module. Through the scheme of the embodiment, the current mismatch problem of the current charge pump circuit is solved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the technical solutions of the present invention, and are incorporated in and constitute a part of this specification, together with the embodiments of the present invention for explaining the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

FIG. 1 is a schematic diagram of a charge pump circuit in the related art;

fig. 2 is a schematic diagram of a charge pump circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a charge pump circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a charge pump circuit including an initial bias voltage providing module according to an embodiment of the present invention;

fig. 5 is a schematic diagram of another sampling control circuit according to an embodiment of the present invention;

fig. 6 is a signal waveform diagram of a lock detector circuit according to an embodiment of the present invention in different states;

fig. 7 is a block diagram of a pll circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the present invention, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

The embodiment of the utility model provides a charge pump circuit 1 is still provided, as shown in fig. 2, can include: a charge-discharge module 11, an operational amplifier 12, a sampling control circuit 13 and a voltage sampling and holding module 14;

the state control end of the charge-discharge module 11 is connected with the control output end of a preset Phase Frequency Detector (PFD), and the charge-discharge connection end of the charge-discharge module 11 is connected with the input end of a post-stage filter capacitor; the output end of the filter capacitor of the later stage is connected with the input end of the VCO (voltage controlled oscillator);

the charge-discharge module 11 may be configured to enter a charge-discharge state of a filter capacitor at a subsequent stage of the charge pump circuit under the control of the PFD, or enter a sampled state for the operational amplifier to perform voltage sampling; the PFD controls the state (charge and discharge state or sampled state) of the charge and discharge module according to the feedback signal of the VCO; the voltage of the filter capacitor is used for controlling the frequency of the VCO;

the input end of the sampling control circuit 13 is connected with the result output end of the PFD; a first output end of the sampling control circuit 13 is connected to a first controlled end of the voltage sampling and holding module 14;

the sampling control circuit 13 may be configured to obtain an output result of the PFD, generate a corresponding control signal according to the output result of the PFD, and control the operational amplifier to be turned on to start voltage sampling or to be turned off to stop voltage sampling according to the control signal;

the voltage output end of the operational amplifier 12 is connected with the bias voltage input end of the charge-discharge module 11 through the voltage sampling and holding module 14; the positive input end and the negative input end of the operational amplifier 12 are respectively connected with different charging and discharging connecting ends of the charging and discharging module 11;

the operational amplifier 12 may be configured to sample voltages at a plurality of charge and discharge connection terminals on a charge and discharge path in the charge and discharge module 11 after being turned on under the control of the sampling control circuit 13, output corresponding bias voltages according to the obtained sampled voltages, and input the bias voltages to a bias voltage input terminal of the charge and discharge module 11, so as to implement negative feedback through the bias voltages and control the voltages at the plurality of charge and discharge connection terminals to be consistent;

a sampling input end of the voltage sampling and holding module 14 is connected with a voltage output end of the operational amplifier 12, and a bias voltage output end of the voltage sampling and holding module 14 is connected with a bias voltage input end of the charge and discharge module 11;

the voltage sampling and holding module 14 is configured to sample the bias voltage output by the operational amplifier 12 when the charge and discharge module 11 is in the sampled state, hold the sampled bias voltage when the charge and discharge module 11 enters the charge and discharge state, and input the held bias voltage to the bias voltage input end of the charge and discharge module 11 to maintain the current in the charge and discharge module 11 unchanged.

In an exemplary embodiment of the present invention, a specific embodiment of the charge pump circuit according to an embodiment of the present invention is given below, and as shown in fig. 3, the charge pump circuit may include an operational amplifier 12, a charging current branch (i.e., a charge-discharge module 11, i.e., OPAMP) and a plurality of switches, wherein the plurality of switches (e.g., S1_ S4) in the charge-discharge module 11 have the same function as the conventional charge pump circuit. The fifth switch S5 and the first capacitor Cs in the voltage sample-and-hold module 14 implement the function of sample-and-hold. The fifth switch S5 and the first capacitor Cs sample the output voltage of the operational amplifier 12 for a period of time in each reference clock cycle and hold the sampled output voltage on the first capacitor Cs, so that the current of the MP1 is maintained without change. The operational amplifier 12 functions to eliminate the charge sharing effect by generating an appropriate bias voltage Vbp through negative feedback to maintain Vm and Vc equal. In the charging and discharging module 11, during the sampling phase (i.e., in the sampled state), the current of the MP1 flows into the MN1 completely, so that the current of the two tubes (MP1 and MN1) can be perfectly matched, at this time, the bias voltage Vbp of the MP1 is recorded, and when the charge pump charges or discharges the filter capacitor of the subsequent stage and the first switch S1 and the second switch S2 are turned on simultaneously, the MP1 is biased by the voltage Vbp, so that the current mismatch can be eliminated well. The circuit recharges the first capacitor Cs every cycle, thereby constantly updating the magnitude of the current of the trim MP1 and avoiding the Vbp voltage drop caused by leakage current.

In an exemplary embodiment of the present invention, the following describes the structure of the charge pump circuit in fig. 3 in detail.

In an exemplary embodiment of the present invention, the charge and discharge module 11 may include: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

a source electrode of the first P-type MOS transistor MP1 is connected to a power supply, a gate electrode thereof is used as the bias voltage input terminal, and is connected to a voltage output terminal of the operational amplifier and a voltage output terminal of the voltage sample-and-hold module, and a drain electrode thereof is connected to a first end of the second switch S2 and a first end of the fourth switch S4, respectively;

a second end of the second switch S2 is connected to a first charge-discharge connection end Vc; a second end of the fourth switch S4 is connected with a second charging and discharging connection end Vm;

a second end of the first switch S1 is connected with a first charging and discharging connection end Vc; the second end of the third switch S3 is connected with a second charge-discharge connection end Vm;

In an exemplary embodiment of the present invention, the state control terminal of the charge and discharge module 11 may refer to the controlled terminal of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4, and the controlled terminal may control the opening or closing of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.

In an exemplary embodiment of the present invention, the voltage sample and hold module 14 may include: a fifth switch S5 and a first capacitor; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module;

the voltage output end of the operational amplifier 12 is connected to the bias voltage input end of the charge and discharge module 11 through the fifth switch S5; a first end of the fifth switch is used as a sampling input end of the voltage sampling and holding module 14, and is connected to a voltage output end of the operational amplifier 12; the second end of the fifth switch is connected with the gate of the first P-type MOS transistor MP 1;

a first end of the first capacitor is used as a voltage output end of the voltage sample-and-hold module 14, and is used for outputting the held bias voltage.

In the exemplary embodiment of the present invention, the operational amplifier 12 samples or stops sampling the charge and discharge module 11 by the control of the sampling control circuit 13; the sampling control circuit 13 controls the operational amplifier when it is determined by detecting the output result of the PFD. The output result of the PFD may be used to control the state of the charge-discharge module 11 (whether the charge-discharge module is in a charge-discharge state or in a sampled state), and it may be determined when to control the operational amplifier according to the state of the charge-discharge module 11. The operational amplifier 12 may be controlled to be turned on to start sampling when in the sampled state, and the operational amplifier 12 may be controlled to be turned off to stop sampling when in the charge-discharge state.

In an exemplary embodiment of the present invention, the sampling control circuit 13 includes: a logic operation circuit;

the logic operation circuit obtains the output result of the PFD, and comprises:

obtaining voltages which are output by the PFD and used for controlling the on-off states of different charging and discharging paths of the charging and discharging module; the on-off states of the different charging and discharging paths are used for indicating that the charging and discharging module is in the charging and discharging state or the sampled state;

the logic operation circuit generates a corresponding control signal according to the output result of the PFD, and controls the operational amplifier to be switched on to start voltage sampling or to be switched off to stop voltage sampling according to the control signal, and the method comprises the following steps:

and performing logic calculation on the collected voltages on different charging and discharging paths to obtain a control signal of the fifth switch S5, and controlling the fifth switch S5 to be closed through the control signal so as to control the operational amplifier to be switched on, or controlling the fifth switch S5 to be switched on through the control signal so as to control the operational amplifier to be switched on and off.

The utility model discloses an in the exemplary embodiment, based on the circuit embodiment of aforementioned charge-discharge module 11, the charge-discharge module gets into the charge-discharge state to the filter electric capacity of the back level of charge pump circuit under the control of predetermined phase frequency detector PFD, perhaps gets into by the sampling state for operational amplifier carries out voltage sampling, can include:

when the second switch S2 and the first switch S1 are controlled to be alternatively opened; when the third switch S3 and the fourth switch S4 are controlled to be opened alternatively, the charging and discharging module is controlled to enter the charging and discharging state;

when the second switch S2 and the first switch S1 are both controlled to be opened and the third switch S3 and the fourth switch S4 are both controlled to be closed, the charge and discharge module is controlled to enter the sampled state;

when the second switch S2 and the first switch S1 are both controlled to be closed and the third switch S3 and the fourth switch S4 are both controlled to be open, this state is short, and the short pulse of the state is used to eliminate the phase detection dead zone. At this time, the charging and discharging module does not perform charging and discharging operations on the rear-stage capacitor, and the original voltage of the rear-stage capacitor is maintained unchanged.

The exemplary embodiment of the present invention provides a circuit embodiment based on the aforementioned charge and discharge module 11, the voltage of PFD output for controlling the on-off state of different charge and discharge paths of the charge and discharge module 11 may include:

acquiring a first voltage upb output by the PFD and used for controlling the on-off of the fourth switch S4; the first voltage upb is used as a voltage for controlling the on-off state of the second charging path;

acquiring a second voltage dnb output by the PFD for controlling the first terminal of the third switch S3; the second voltage dnb is used as a voltage for controlling the on/off state of the second discharge path.

The exemplary embodiment of the present invention provides a charging and discharging module 11, which is capable of determining the state of the charging and discharging module 11 according to the output voltage of the PFD to the switches on different charging and discharging paths, because the charging and discharging module 11 is in different states (charging and discharging states or sampled states), and the switching states of the switches on different charging and discharging paths are different, and the voltage values output by the PFD to the switches on different charging and discharging paths are also different.

In the exemplary embodiment of the present invention, the sampling control circuit 13 may perform logical calculation on the output voltage of the obtained PFD, and finally obtain a control signal for controlling the operational amplifier.

In an exemplary embodiment of the present invention, as shown in fig. 3, the logic operation circuit may include: a second AND gate 136;

one input end of the second and gate 136 is set to input the first voltage upb outputted by the PFD for controlling the on/off of the fourth switch S4; the first voltage upb is used for controlling the on-off state of the second charging path;

the other input end of the second and gate 136 is configured to input a second voltage dnb output by the PFD for controlling the on/off of the third switch S4; the second voltage dnb is used for controlling the on-off state of the second discharge path;

the output end of the second and gate 136 is used as the output end of the sampling control circuit, is connected to the fifth switch S5, and is configured to control the opening or closing of the fifth switch S5 according to the output signal of the second and gate 136.

In an exemplary embodiment of the present invention, as shown in fig. 4, the charge pump circuit may further include: an initial bias voltage supply module 15;

the bias voltage output end of the initial bias voltage providing module 15 is connected with the bias voltage input end of the charge and discharge module 11, and is set to provide the bias voltage for the charge and discharge module 11 when the phase-locked loop does not reach the locking state.

In an exemplary embodiment of the present invention, the bias voltage output terminal of the initial bias voltage providing module 15 is connected to the bias voltage input terminal of the charge and discharge module 11 through the voltage sampling and holding module 14;

the voltage sample-and-hold module 14 is further configured to control the initial bias voltage providing module 15 to disconnect the charging/discharging module 11 before sampling the bias voltage of the operational amplifier 12.

In the exemplary embodiment of the present invention, after the bias voltage of the operational amplifier 12 is sampled, the initial bias voltage providing module 15 is no longer functional (no bias voltage is provided for the charge and discharge module 11), and the bias voltage can be provided by the voltage sampling and holding module 14 later.

In the exemplary embodiment of the present invention, the sampling control circuit 13 may be further configured to: detecting whether a phase-locked loop reaches a locked state, and generating the control signal and an on-off control signal of an initial bias voltage supply module according to a detection result of whether the phase-locked loop reaches the locked state and an output result of the PFD; before sampling the bias voltage of the operational amplifier, the initial bias voltage providing module is controlled to be disconnected from the charge-discharge module according to the on-off control signal.

In the exemplary embodiment of the present invention, the operational amplifier 12 samples or stops sampling the charge and discharge module 11 by the control of the sampling control circuit 13; the timing of the sampling control circuit 13 controlling the operational amplifier is determined by detecting the output result of the PFD and the phase difference of the feedback signal of the VCO circuit. The output result of the PFD may also be used to control the state of the charge-discharge module 11 (whether the charge-discharge module is in a charge-discharge state or in a sampled state, where the output result of the PFD may control the operational amplifier 12 to be turned on to start sampling when the charge-discharge module is in the sampled state); the phase difference of the feedback signal of the VCO circuit can reflect whether the phase-locked loop reaches a locked state or not; when the phase-locked loop reaches the locking state and the phase-locked loop does not reach the locking state, the operational amplifier can be controlled to stop sampling.

In the exemplary embodiment of the present invention, the sampling control circuit 13 may perform logical calculation on the output voltage of the obtained PFD and the obtained phase comparison result, and finally obtain a control signal for controlling the operational amplifier and the initial bias voltage providing module 15.

In an exemplary embodiment of the present invention, the sampling control circuit 13 may include: a lock detection circuit and a logical operation circuit;

the locking detection circuit is arranged to detect whether the phase-locked loop reaches a locking state and output a detection result; the detection result comprises a first detection result used for indicating that the phase-locked loop reaches a locking state and a second detection result used for indicating that the phase-locked loop does not reach the locking state;

the logic operation circuit is configured to obtain an output result of the PFD, generate the control signal according to a detection result of whether the phase-locked loop is in a locked state and the output result of the PFD, and control the operational amplifier to be turned on to start voltage sampling or to be turned off to stop voltage sampling according to the control signal; and before sampling the bias voltage of the operational amplifier, controlling the initial bias voltage providing module to be disconnected from the charge-discharge module according to the on-off control signal.

In the exemplary embodiment of the present invention, the lock detection circuit detects whether the phase-locked loop reaches the locked state, and outputs the detection result, which may include:

obtaining a feedback signal of the VCO, carrying out frequency division on the feedback signal, and obtaining a signal phase phi of the frequency-divided signal _div And the phase of the signal is phi _div With a predetermined reference source phase phi _ref In comparison, when the phase of the signal is phi _div With a predetermined reference source phase phi _ref When the phase difference is smaller than a preset phase difference threshold value, outputting the first detection result; when the phase of the signal is phi _div Phase phi of preset reference source _ref When the phase difference is larger than or equal to a preset phase difference threshold value, outputting the second detection result;

the logic operation circuit obtaining the output result of the PFD may include:

obtaining voltages which are output by the PFD and used for controlling the on-off states of different charging and discharging paths of the charging and discharging module; and the on-off states of the different charging and discharging paths are used for indicating that the charging and discharging module is in the charging and discharging state or the sampled state.

The utility model discloses an in the exemplary embodiment, the logical operation circuit acquires being used for of PFD output control the voltage of the on-off state of the different charge and discharge routes of charge and discharge module can include:

acquiring a second voltage dnb output by the PFD and used for controlling the on-off of the third switch S3; the second voltage dnb is used as a voltage for controlling the on/off state of the second discharge path. In an exemplary embodiment of the present invention, the initial bias voltage providing module 15 may include: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN 2;

In the exemplary embodiment of the present invention, when the initial bias voltage providing module 15 is present, before sampling the bias voltage of the operational amplifier 12, the initial bias voltage providing module 15 may be turned off by controlling the voltage sample-and-hold module 14-1 by the sample control circuit 13-1 (the sample control circuit 13-1 is different from the aforementioned absent initial bias voltage providing module 15 and may be regarded as an optimization of the aforementioned sample control circuit 13) and the voltage sample-and-hold module 14-1 ((the voltage sample-and-hold module 14-1 is different from the aforementioned absent initial bias voltage providing module 15 and may be regarded as an optimization of the aforementioned voltage sample-and-hold module 14) in the charge pump circuit).

In an exemplary embodiment of the present invention, as shown in fig. 4, the voltage sample-and-hold module 14-1 may include: a fifth switch S5, a sixth switch S6, and a first capacitor Cs; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module; the controlled end of the sixth switch S6 is used as the second controlled end of the voltage sample-and-hold module;

the voltage output end of the operational amplifier 12 is connected with the bias voltage input end of the charge and discharge module through the fifth switch S5; the first end of the fifth switch is used as the sampling input end of the voltage sampling and holding module and is connected with the voltage output end of the operational amplifier; a second end of the fifth switch S5 is connected to the gate of the first P-type MOS transistor MP 1;

the bias voltage output end of the initial bias voltage providing module 15 is connected with the bias voltage input end of the charge and discharge module 11 through the sixth switch S6; a first end of the sixth switch is connected with a gate of the second P-type MOS transistor MP 2; a second end of the sixth switch S6 is connected to the gate of the first P-type MOS transistor MP 1;

a first end of the first capacitor Cs is connected to the bias voltage input end of the charge and discharge module 11, and a second end of the first capacitor Cs is connected to a power supply VDD; a first end of the first capacitor Cs is connected to the gate of the first P-type MOS transistor MP1, and a second end of the first capacitor Cs is connected to a power supply VDD;

a first end of the first capacitor Cs is used as a voltage output end of the voltage sample-and-hold module 14, and is configured to output the held bias voltage;

the gate of the second P-type MOS transistor MP2 is connected to the bias voltage input terminal of the charge and discharge module 11 through the sixth switch S6.

In an exemplary embodiment of the present invention, the logic operation circuit generates the control signal according to the detection result of whether the phase-locked loop reaches the locked state and the output result of the PFD, and controls the operational amplifier to be turned on to start voltage sampling or controls the operational amplifier to be turned off to stop voltage sampling according to the control signal; before sampling the bias voltage of the operational amplifier, controlling the initial bias voltage providing module to be disconnected from the charge-discharge module according to the on-off control signal, comprising:

performing logic calculation on the first detection result or the second detection result and the acquired voltages on different charging and discharging paths to obtain a control signal of the fifth switch S5 and a control signal of the sixth switch S6, controlling the sixth switch S6 to be opened by the control signal of the sixth switch S6, and controlling the fifth switch S5 to be closed by the control signal of the fifth switch S5 to control the initial bias voltage providing module to be opened and control the operational amplifier to be turned on, or controlling the fifth switch S5 to be opened by the control signal to control the operational amplifier to be opened, so as to provide bias voltages for the charging and discharging modules by the voltage sampling and holding module.

In an exemplary embodiment of the present invention, as shown in fig. 5, the sampling control circuit may include: a first delay unit 131, a second delay unit 132, a first flip-flop 133, and a second flip-flop 134; the logical operation circuit may include: a first and gate 135, a second and gate 136, and a first not gate 137; a difference value between the second delay time length of the second delay unit 132 and the first delay time length of the first delay unit 131 is a preset phase difference threshold;

the input end of the first delay unit 131 is set to input a reference source phase phi _ref An output end of the first delay unit 131 is connected to a first input end of the first flip-flop 133 and a first input end of the second flip-flop 134, respectively;

the input end of the second delay unit 132 is set to the phase phi of the signal obtained by dividing the frequency of the feedback signal input to the VCO _div An output end of the second delay unit 132 is respectively connected to a second input end of the first flip-flop 133 and a second input end of the second flip-flop 134;

the output terminal of the first flip-flop 133 is connected to a first input terminal of the first and gate 135;

the output terminal of the second flip-flop 134 is connected to the second input terminal of the first and gate 135;

the output terminal of the first and gate 135 is connected to a first input terminal of the second and gate 136;

a second input end of the second and gate 136 is set to input a first voltage upb output by the PFD for controlling the on/off of the fourth switch S4; the first voltage upb is used for controlling the on-off state of the second charging path;

a third input end of the second and gate 136 is configured to input a second voltage dnb output by the PFD and used for controlling the third switch S4 to be switched on and off; the second voltage dnb is used for controlling the on-off state of the second discharge path;

the output end of the second and gate 136 is used as the first output end of the sampling control circuit, is connected to the controlled end of the fifth switch S5, and is configured to control the opening or closing of the fifth switch S5 through the output signal of the second and gate 136;

the input end of the first not gate 137 is connected to the output end of the first and gate 135, and the output end of the first not gate 137 is used as the second output end of the sampling control circuit 13, and is connected to the controlled end of the sixth switch S6.

In an exemplary embodiment of the present invention, the lock detection circuit may be composed of two delay units (the first delay unit 131, the second delay unit 132) and two flip-flops (the first flip-flop 133 and the second flip-flop 134). The delay time lengths of the two delay units may be T and 2T, respectively (so that the phase difference threshold is T), and the two delay units may be respectively composed of a plurality of inverters. Ctr is the AND logic of three signals, upb, dnb and lock. When phi is _ref And phi _div When the phase difference of (1) is less than T (a preset phase difference threshold value), the two signals are considered to be close to locking, and the output of lock can be high level; when phi is _ref And phi _div The output of lock may be low when the phase difference of (1) is greater than T. In an exemplary embodiment of the present invention, the phase of the reference source when the phase-locked loop is phi _ref And the phase phi of the feedback frequency-divided signal _div When the phase difference is greater than T, lockb is high, ctr is low, the switch S5 is turned off, and the switch S6 is turned on. At this time, the voltage of Vbp comes from Vgs voltage generated by diode connection of the MP2 tube, and a current matching circuit (namely, the operational amplifier 12) in the circuit does not work.

In an exemplary embodiment of the present invention, the phase of the reference source when the phase-locked loop is phi _ref And the phase phi of the signal after feedback frequency division _div When the phase difference is less than T, lock is high, and lockb is low, at which time the switch S6 is turned off, and the left MP1 circuit is no longer functional. The current matching circuit (i.e., operational amplifier 12) starts operating. When the switches S1 and S2 are both off and the switches S3 and S4 are both on, the control signal ctr of S5 is high and S5 is on, which is in the sampling phase. The negative feedback action of the operational amplifier 12 makes the voltage at the point Vm and the voltage at the point Vc approximately equal, so that the voltages of X and Y are approximately equal to the voltage at the point Vc, to avoid charge sharing. When phi is _ref And phi _div When the phases are not completely aligned, one of S1 and S2 is turned off, and the other is turned offWhen the charge pump is turned on, that is, when the charge pump charges or discharges externally, one of upb and dnb is at a low level, ctr is an and logic of three signals, namely upb, dnb and lock, so that ctr is at a low level, the switch S5 is turned off, and the circuit enters a holding state (at this time, the charge and discharge module 11 is in a charge and discharge state), that is, the first capacitor Cs holds the voltage at the turn-off time Vbp of S5. When the up and dn signals are high level at the same time, the up b and dn signals are low level, the circuit maintains the original holding state, and the operation of the holding state is consistent with the state after the phase-locked loop is locked. At this moment phi _ref And phi _div When the phases are completely aligned, the inherent pulse enables the switches S1 and S2 to be both turned on, the switches S3 and S4 to be both turned off, the Vbp keeps the previous sampling voltage value unchanged, the output voltage of the operational amplifier 12 does not work, and the slight change of the voltages at the Vm point and the Vc point does not affect the current matching.

In the exemplary embodiment of the present invention, as shown in fig. 6, in order to lock the signal waveform of the detection circuit in the non-state, C refers to sampling and B refers to holding.

In an exemplary embodiment of the present invention, the left side of fig. 5 shows phi _ref And phi _div In the case of a large phase difference, assume that _ref The phase of the operational amplifier is advanced, when the up signal and the dn signal are both low level, the circuit is in a sampling state, at the initial sampling stage, an establishing process is carried out in a loop of a phase-locked loop where the operational amplifier is located, so that Vbp voltage can oscillate briefly, when the loop of the phase-locked loop is stable, the loop can control the output of the operational amplifier to charge a sampling capacitor, when the up first shows high level, a logic operation circuit controls a voltage acquisition and holding circuit to enter a holding state, at the moment, the sampling is finished, the voltage on the sampling capacitor is held, at the moment, the voltage on the Vbp cannot change, and a charge pump is controlled to charge a backward filter capacitor.

In an exemplary embodiment of the present invention, the right diagram of FIG. 6 shows φ _ref And phi _div In the case of a phase difference of 0, the circuit is in the sampling state when both the up and dn signals are low, and there is an overshoot established in the loop of the phase locked loop in which the operational amplifier is located during the initial sampling periodAnd when the up and dn appear high level at the same time, the logic operation circuit controls the voltage acquisition and holding circuit to enter a holding state, the sampling is finished, the voltage on the sampling capacitor is held, the voltage on the Vbp cannot be changed, and the charge pump is controlled to charge the capacitor of the backward filter.

In exemplary embodiments of the present invention, at least the following advantages are included:

1. the currents of MP1 and MN1 can be matched accurately, the influence of the channel length modulation effect caused by the voltage change of Vc is eliminated, and the matching of the currents cannot be influenced by the deviation of a manufacturing process because the reference branch does not work after the phase-locked loop is locked.

2. The current of the branch where MP2 is located may be below 1/20 of the branch where MP1 is located, and the current of the branch where MP2 is located in the current similar scheme is the same as the current of the branch where MP1 is located, so the current power consumption of the embodiment of the present invention is smaller, and particularly, after the phase-locked loop is locked, the current of the branch where MP2 is located may be turned off, thereby further reducing the power consumption.

3. The embodiment of the utility model provides an only adopted an operational amplifier in the scheme, realized the elimination of charge sharing effect simultaneously to and the matching of charging and discharging current, reduced the complexity of circuit.

The embodiment of the utility model provides a phase-locked loop circuit 2 is still provided, as shown in fig. 7, can include: the charge pump circuit 1, the filter capacitor 2 and the phase frequency detector PFD connected to the charge pump circuit 1, the voltage controlled oscillator VCO connected to the filter capacitor 2, and the frequency divider 3 connecting the VCO and the PFD.

In the exemplary embodiment of the present invention, any of the foregoing charge pump circuits is applicable to the phase-locked loop circuit, and is not described herein again.

In the description of the present invention, it should be noted that the terms "upper", "lower", "one side", "the other side", "one end", "the other end", "side", "opposite", "four corners", "periphery", "mouth" word structure "and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplification of the description, but do not indicate or imply that the structure referred to has a specific orientation, is constructed and operated in a specific orientation, and thus, is not to be construed as limiting the present invention.

In the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "connected," "directly connected," "indirectly connected," "fixedly connected," "mounted," and "assembled" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; the terms "mounted," "connected," and "fixedly connected" may refer to a direct connection, an indirect connection through intervening media, and a connection between two elements. The specific meaning of the above terms in the present invention can be understood as a specific case by those skilled in the art.

Although the embodiments of the present invention have been described above, the description is only for the convenience of understanding the present invention, and the present invention is not limited thereto. Any modifications and variations in form and detail of the present invention may be made by those skilled in the art without departing from the spirit and scope of the present invention, but it is still intended to cover in the appended claims all such modifications and variations as fall within the true spirit and scope of the invention.

Claims

1. A charge pump circuit, comprising: the device comprises a charge-discharge module, an operational amplifier, a sampling control circuit and a voltage sampling holding module;

the state control end of the charge-discharge module is connected with the control output end of a preset Phase Frequency Detector (PFD), and the charge-discharge connection end of the charge-discharge module is connected with the charge-discharge input end of a post-stage filter capacitor; the output end of the filter capacitor is connected with the input end of the voltage controlled oscillator VCO;

the voltage output end of the operational amplifier is connected with the bias voltage input end of the charge-discharge module through the voltage sampling and holding module; the positive input end and the negative input end of the operational amplifier are respectively connected with different charging and discharging connecting ends of the charging and discharging module;

2. The charge pump circuit of claim 1, wherein the charge and discharge connection comprises: the charging and discharging circuit comprises a first charging and discharging connection end Vc and a second charging and discharging connection end Vm; the plurality of charging and discharging paths of the charging and discharging module comprise: a first charging path, a second charging path, a first discharging path and a second discharging path;

3. The charge pump circuit of claim 2, wherein the charge-discharge module comprises: a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4;

the second end of the first switch S1 is connected to the first charge-discharge connection end Vc; a second end of the third switch S3 is connected with a second charging and discharging connection end Vm;

4. The charge pump circuit of claim 3, wherein the voltage sample-and-hold module comprises: a fifth switch S5 and a first capacitor; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module;

5. The charge pump circuit of claim 4, wherein the sampling control circuit comprises: a logic operation circuit; the logical operation circuit includes: a second AND gate;

one input end of the second and gate is set to input a first voltage upb output by the PFD and used for controlling the on-off of the fourth switch S4; the first voltage upb is used for controlling the on-off state of the second charging path;

the other input end of the second and gate is set to input a second voltage dnb output by the PFD and used for controlling the on-off of the third switch S3; the second voltage dnb is used for controlling the on-off state of the second discharge path;

6. The charge pump circuit of claim 3, further comprising: an initial bias voltage providing module;

7. The charge pump circuit of claim 6, wherein the early bias voltage providing module comprises: a second P-type MOS transistor MP2 and a second N-type MOS transistor MN 2;

the source electrode of the second N-type MOS tube MN2 is grounded; the grid electrode of the second N-type MOS tube MN2 is connected with a preset bias voltage Vbn.

8. The charge pump circuit of claim 7, wherein the voltage sample and hold module comprises: a fifth switch S5, a sixth switch S6, and a first capacitor; the controlled end of the fifth switch S5 is used as the first controlled end of the voltage sample-and-hold module; the controlled end of the sixth switch S6 is used as the second controlled end of the voltage sample-and-hold module;

the first end of the first capacitor is used as the voltage output end of the voltage sampling and holding module and used for outputting the held bias voltage;

9. The charge pump circuit of claim 8, wherein the sampling control circuit comprises: a lock detection circuit and a logical operation circuit;

the lock detection circuit includes: the trigger circuit comprises a first delay unit, a second delay unit, a first trigger and a second trigger; the logical operation circuit includes: the first AND gate, the second AND gate and the first NOT gate; a difference value between a second delay time length of the second delay unit and a first delay time length of the first delay unit is a preset phase difference threshold value;

the input end of the first delay unit is set as an input reference source phase phi _ref The output end of the first delay unit is respectively connected with the first input end of the first trigger and the first input end of the second trigger;

a third input end of the second and gate is connected with a second result output end of the PFD, and is set to input a second voltage dnb output by the PFD and used for controlling the on-off of the third switch S3; the second voltage dnb is used for controlling the on-off state of the second discharge path;

10. A phase-locked loop circuit, comprising: the charge pump circuit of any one of claims 1-9, a filter capacitor and Phase Frequency Detector (PFD) coupled to the charge pump circuit, a Voltage Controlled Oscillator (VCO) coupled to the filter capacitor, and a frequency divider coupling the VCO and the PFD.