CN217239453U - Lead frame - Google Patents
Lead frame Download PDFInfo
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- CN217239453U CN217239453U CN202220262368.5U CN202220262368U CN217239453U CN 217239453 U CN217239453 U CN 217239453U CN 202220262368 U CN202220262368 U CN 202220262368U CN 217239453 U CN217239453 U CN 217239453U
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- bonding pad
- chip bonding
- dam
- chip
- center
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a lead frame, which relates to the technical field of integrated circuits, and is formed by processing a substrate; the chip packaging structure is characterized in that a plurality of chip areas are arranged on the top of the substrate; a chip bonding pad is arranged at the center of the chip area; the four corner positions of the chip bonding pad are connected with the corner disc through the first dam strip; a second dam strip is arranged between the adjacent corner plates; ten first pins are arranged on the inner side of the second dam bar; ten second pins corresponding to the first pins are arranged on the outer side of the second dam bar; and etching both sides of the top surfaces of the joints of the first pins, the second pins and the second dam bars. The lead frame of the utility model has high strength, good electric and heat conducting effects; a back nested structure is generated by etching, so that the reliability is improved; the silver plating in the specific area is not easy to fade, and the subsequent processing epoxy resin flow mark phenomenon can be inhibited while the conductivity is increased.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a lead frame.
Background
The lead frame is used as a chip carrier of an integrated circuit, is a key structural member for realizing the electrical connection between a lead-out end of an internal circuit of a chip and an outer pin by means of bonding materials (gold wires, aluminum wires and copper wires) to form an electrical circuit, plays a role of a bridge connected with an external lead, needs to be used in most semiconductor integrated blocks and is an important basic material in the electronic information industry.
The existing lead frame has poor reliability; discoloration easily occurs, and a flow mark phenomenon easily occurs when a chip is bonded by subsequent epoxy resin.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a lead frame to solve above-mentioned technical problem.
In order to achieve the above object, the lead frame of the present invention is formed by processing a substrate; the top of the substrate is provided with a plurality of chip areas; a chip bonding pad is arranged at the center of the chip area; the four corner positions of the chip bonding pad are connected with the corner disc through the first dam strip; a second dam strip is arranged between the adjacent corner plates; ten first pins are arranged on the inner side of the second dam bar; ten second pins corresponding to the first pins are arranged on the outer side of the second dam bar; etching both sides of the top surface of the joint of the first pin, the second pin and the second dam bar; etching the bottom surfaces of the end parts of the first pin and the second pin; the outer edge of the bottom surface of the chip bonding pad is provided with a square annular area; the bottom surfaces of the square annular area, the corner disc and the first dam bar and the second dam bar are all subjected to etching treatment.
Furthermore, silver-plated regions are arranged on the outer edge of the top surface of the chip bonding pad, the top surface of the end part of the first pin and the top surface of the first dam bar.
Preferably, the chip bonding pad is square with the width of 3.8 mm; the silver plating area is of a concentric square-shaped structure with the chip bonding pad; the distance between the inner edge of the square-back structure and the center of the chip bonding pad is 1.45-1.6 mm; the distance between the outer edge of the square-back structure and the center of the chip bonding pad is 2.3-2.5 mm.
Preferably, the etching thickness of the semi-etching treatment is 0.1 mm;
preferably, the center line of the first dam bar passes through the center of the chip bonding pad;
preferably, the distance between the second dam bars on the left side and the second dam bars on the right side and the center of the chip bonding pad is 2.56 mm; the width of the second dam bars on the left side and the right side is 0.18mm +/-0.025; the distance between the second dam bars on the upper side and the lower side and the center of the chip bonding pad is 2.575 mm; the width of the second dam bars at the upper side and the lower side is 0.15mm +/-0.025;
preferably, the distance between the adjacent first pins is 0.4 mm;
preferably, the distance from the end part of the first pin to the center of the chip bonding pad is 2.05 mm;
preferably, the outer edge of the square annular area of the bottom surface of the chip bonding pad is 1.9mm away from the center of the chip bonding pad; the inner edge distance of the square annular area on the bottom surface of the chip bonding pad is 1.8mm from the center of the chip bonding pad; and a right-angle chamfer of 0.3mm is arranged at the inner edge of the right upper side of the square annular area.
Further, the chip areas are distributed on the substrate in a rectangular array.
Furthermore, 4 marking holes are formed in the corner disc.
In addition, a rectangular plastic packaging wire slot is also arranged on the substrate outside all the chip areas.
Advantageous effects
The lead frame of the utility model has high strength, good electric and heat conducting effects; a back nested structure is generated by etching, so that the reliability is improved; the silver plating in the specific area is not easy to fade, and the subsequent processing epoxy resin flow mark phenomenon can be inhibited while the conductivity is increased.
Through reasonable layout and size design, the conductivity and strength of the chip to be mounted are ensured.
Drawings
Fig. 1 is a schematic top view of the lead frame according to the present invention.
Fig. 2 is an enlarged schematic view of the top surface of the chip region according to the present invention.
Fig. 3 is an enlarged schematic view of the bottom surface of the chip region according to the present invention.
Fig. 4 is a schematic view of the silver plating area on the top surface of the chip area according to the present invention.
Fig. 5 is a cross-sectional view of S-S of fig. 2 according to the present invention.
Fig. 6 is a sectional view taken along line L-L of fig. 2 according to the present invention.
Fig. 7 is a cross-sectional view taken along line Q-Q of fig. 3 according to the present invention.
Fig. 8 is a cross-sectional view taken along line N-N of fig. 3 according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the drawings of the present invention are combined to clearly and completely describe the technical solutions in the embodiments of the present invention, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To the problem that prior art exists, the embodiment of the utility model provides a lead frame.
Examples
As shown in fig. 1 to 8, a lead frame is formed by processing a substrate 1; the processing method is generally stamping or etching; the physical structures on the lead frame are all part of the substrate 1. The top of the substrate 1 is provided with a plurality of chip areas 2; a chip bonding pad 3 is arranged at the center of the chip area 2; the four corner positions of the chip bonding pad 3 are connected with the corner disc 5 through the first dam strip 4; a second dam bar 6 is arranged between the adjacent corner discs 5; ten first pins 7 are arranged on the inner side of the second dam bar 6; ten second pins 8 corresponding to the first pins 7 are arranged on the outer side of the second dam bar 6; etching both sides of the top surfaces of the joints of the first pins 7, the second pins 8 and the second dam bars 6 are marked as first etching areas 9; etching the bottom surfaces of the end parts of the first pin 7 and the second pin 8; denoted as second etched region 10; the outer edge of the bottom surface of the chip bonding pad 3 is provided with a square annular area 11; the bottom surfaces of the square annular region 11, the corner disc 5 and the first dam bar 4 and the second dam bar 6 are all etched.
Silver-plated regions 12 are provided on the top peripheral edge of the chip pad 3, the top surface of the end portion of the first pin 7, and the top surface of the first dam bar 4.
The chip bonding pad 3 is a square with the width of 3.8 mm; the silver plating area 12 is of a concentric square-shaped structure with the chip bonding pad 3; the distance between the inner edge of the square-shaped structure and the center of the chip bonding pad 3 is 1.45-1.6 mm; the distance between the outer edge of the square-back structure and the center of the chip bonding pad 3 is 2.3-2.5 mm.
The etching thickness of the semi-etching treatment is 0.1 mm;
the center line of the first dam bar 4 passes through the center of the chip bonding pad 3;
the distance between the second dam bars 6 at the left side and the right side and the center of the chip bonding pad 3 is 2.56 mm; the width of the second dam bar 6 at the left side and the right side is 0.18mm +/-0.025; the distance between the second dam bars 6 on the upper side and the lower side and the center of the chip bonding pad 3 is 2.575 mm; the width of the second dam bars 6 at the upper and lower sides is 0.15mm +/-0.025;
the distance between the adjacent first pins 7 is 0.4 mm;
the distance from the end part of the first pin 7 to the center of the chip bonding pad 3 is 2.05 mm;
the outer edge of the square annular region 11 on the bottom surface of the chip bonding pad 3 is 1.9mm away from the center of the chip bonding pad 3; the inner edge distance of the square annular area 11 on the bottom surface of the chip bonding pad 3 is 1.8mm from the center of the chip bonding pad 3; the inner edge of the right upper side of the square annular area 11 is provided with a right-angle chamfer of 0.3 mm.
The chip areas 2 are distributed in a rectangular array on the substrate 1.
The corner plate 5 is provided with 4 marking holes 13.
A rectangular plastic wire casing 14 is also arranged on the substrate 1 outside all the chip areas 2.
The lead frame of the utility model has high strength, good electric and heat conducting effects; a back nested structure is generated by etching, so that the reliability is improved; the silver plating in the specific area is not easy to fade, and the subsequent processing epoxy resin flow mark phenomenon can be inhibited while the conductivity is increased.
Through reasonable layout and size design, the conductivity and strength of the chip to be mounted are ensured.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the appended claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (9)
1. A lead frame is processed by a substrate; the chip packaging structure is characterized in that a plurality of chip areas are arranged on the top of the substrate; a chip bonding pad is arranged at the center of the chip area; the four corner positions of the chip bonding pad are connected with the corner disc through the first dam strip; a second dam strip is arranged between the adjacent corner plates; ten first pins are arranged on the inner side of the second dam bar; ten second pins corresponding to the first pins are arranged on the outer side of the second dam bar; etching both sides of the top surface of the joint of the first pin, the second pin and the second dam bar; etching the bottom surfaces of the end parts of the first pin and the second pin; the outer edge of the bottom surface of the chip bonding pad is provided with a square annular area; the bottom surfaces of the square annular area, the corner disc and the first dam bar and the second dam bar are all subjected to etching treatment.
2. The lead frame of claim 1, wherein silver plating is provided on the top peripheral edge of the die pad, the top surface of the end portion of the first lead, and the top surface of the first dam.
3. The lead frame according to claim 2, wherein the die pad is square with a width of 3.8 mm; the silver plating area is of a concentric square-shaped structure with the chip bonding pad; the distance between the inner edge of the square-back structure and the center of the chip bonding pad is 1.45-1.6 mm; the distance between the outer edge of the square-back structure and the center of the chip bonding pad is 2.3-2.5 mm.
4. A lead frame according to claim 3, characterized in that the etching thickness by the half etching process is 0.1 mm.
5. The lead frame of claim 4, wherein the centerline of the first dam passes through the center of the die pad; the distance between the second dam bars on the left side and the right side and the center of the chip bonding pad is 2.56 mm; the width of the second dam bars on the left side and the right side is 0.18mm +/-0.025; the distance between the second dam bars on the upper side and the lower side and the center of the chip bonding pad is 2.575 mm; the width of the second dam bars on the upper side and the lower side is 0.15mm +/-0.025.
6. A lead frame according to claim 5, characterized in that the spacing between adjacent first leads is 0.4 mm; the distance from the end part of the first pin to the center of the chip bonding pad is 2.05 mm; the outer edge of the square annular area of the bottom surface of the chip bonding pad is 1.9mm away from the center of the chip bonding pad; the inner edge distance of the square annular area of the bottom surface of the chip bonding pad is 1.8mm from the center of the chip bonding pad; and a right-angle chamfer of 0.3mm is arranged at the inner edge of the right upper side of the square annular area.
7. A leadframe according to claim 6, characterized in that the chip areas are distributed in a rectangular array on the substrate.
8. A lead frame according to claim 7, characterised in that the corner disc is provided with 4 flag holes.
9. A lead frame according to claim 8, characterized in that a rectangular plastic groove is provided on the substrate outside the total chip area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220262368.5U CN217239453U (en) | 2022-02-09 | 2022-02-09 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220262368.5U CN217239453U (en) | 2022-02-09 | 2022-02-09 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217239453U true CN217239453U (en) | 2022-08-19 |
Family
ID=82833936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220262368.5U Active CN217239453U (en) | 2022-02-09 | 2022-02-09 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217239453U (en) |
-
2022
- 2022-02-09 CN CN202220262368.5U patent/CN217239453U/en active Active
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