CN217181048U - Three-phase electricity acquisition circuit - Google Patents
Three-phase electricity acquisition circuit Download PDFInfo
- Publication number
- CN217181048U CN217181048U CN202220039533.0U CN202220039533U CN217181048U CN 217181048 U CN217181048 U CN 217181048U CN 202220039533 U CN202220039533 U CN 202220039533U CN 217181048 U CN217181048 U CN 217181048U
- Authority
- CN
- China
- Prior art keywords
- circuit
- analog
- signal
- digital converter
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
The application relates to a three-phase electricity acquisition circuit, which belongs to the technical field of three-phase electricity processing and comprises an acquisition circuit, an analog-to-digital converter, a digital isolation circuit and a single chip microcomputer; the acquisition circuit is respectively connected with three phase lines and a neutral line in three-phase power, and the output end of the acquisition circuit is connected with the input end of the analog-to-digital converter; the first synchronous serial interface of the analog-to-digital converter is connected with the signal input end of the digital isolation circuit; the signal output end of the digital isolation circuit is connected with a second synchronous serial interface of the singlechip; the second synchronous serial interface is connected with a DMA module of the single chip microcomputer, and the DMA module is connected with a CPU of the single chip microcomputer. This application has the effect that reduces the cost of electric isolation in three-phase electricity collection process.
Description
Technical Field
The application relates to the field of three-phase electric processing, in particular to a three-phase electric acquisition circuit.
Background
The three-phase alternating current is a transmission form of electric energy, and is called three-phase power for short, and consists of three alternating currents with equal magnitude, same frequency and 120-degree initial phase difference. Three-phase electricity is widely used in power plants and power grid production, transmission and distribution.
In the application of three-phase power, the acquisition and processing of the three-phase power are an important link. At present, a resistance voltage division and metering chip is generally used for carrying out data acquisition on three-phase electricity, then electric appliance isolation is carried out, and then data processing is carried out by a singlechip after AD conversion. The electric appliance isolation circuit not only enables the three-phase electric acquisition circuit to meet the requirements of safety regulations and insulation matching, enhances the EMC performance and reliability of the three-phase electric acquisition circuit, but also can protect important data when an external circuit is damaged due to lightning stroke and other events so as to avoid the damage of the important data.
However, in the electrical isolation circuit, linear optical coupler isolation is usually adopted, and the electrical isolation circuit uses a large number of devices, has high circuit cost, low linearity and large temperature influence on the circuit, is difficult to make into a high-precision low-temperature drift data acquisition system, and analog signals are sensitive to interference signals, so that the anti-interference capability of the circuit may not be high enough.
SUMMERY OF THE UTILITY MODEL
In order to reduce the cost of electric isolation in three-phase electricity collection process, the application provides a three-phase electricity collection circuit.
The application provides a three-phase electricity acquisition circuit adopts following technical scheme:
a three-phase electricity acquisition circuit comprises an acquisition circuit, an analog-to-digital converter, a digital isolation circuit and a single chip microcomputer;
the acquisition circuit is respectively connected with three phase lines and a neutral line in three-phase power, and the output end of the acquisition circuit is connected with the input end of the analog-to-digital converter;
the first synchronous serial interface of the analog-to-digital converter is connected with the signal input end of the digital isolation circuit;
the signal output end of the digital isolation circuit is connected with a second synchronous serial interface of the singlechip;
the second synchronous serial interface is connected with a DMA module of the single chip microcomputer, and the DMA module is connected with a CPU of the single chip microcomputer.
By adopting the technical scheme, the traditional analog-digital converter usually adopts a parallel port mode to complete communication with the singlechip, and adopts linear optical coupling isolation, so that the mode of electrical isolation needs more isolation devices, and the cost is increased sharply; the communication among the digital isolation circuit, the analog-to-digital converter and the single chip microcomputer is completed by adopting the synchronous serial interface, the data are transmitted and received by the DMA module in the single chip microcomputer, the interruption frequency of data transmission and reception is greatly reduced, and the processing of other real-time tasks is not influenced, so that the use of an isolation device is greatly reduced, and the cost is reduced; the acquired current and voltage are converted into digital signals through a high-precision analog-to-digital converter, then the digital signals are electrically isolated and finally sent to a CPU (central processing unit) in the single chip for data processing, the digital signals have higher noise tolerance threshold and better anti-interference capability, and the circuit measurement precision cannot be changed due to the fact that the isolation circuit is influenced by temperature because the digital signals exist.
Optionally, the digital isolation circuit further includes a first isolation circuit;
the singlechip outputs a first signal to the first isolation circuit;
the first isolation circuit is connected with a first signal and outputs a second signal to the analog-to-digital converter;
and the analog-to-digital converter is connected with a second signal for resetting.
By adopting the technical scheme, the control signal for resetting the control analog signal is electrically isolated through the first isolation circuit.
Optionally, the digital isolation circuit includes a second isolation circuit;
the singlechip outputs a third signal to the second isolation circuit;
the second isolation circuit is connected with a third signal and outputs a fourth signal to the analog-to-digital converter;
and the analog-to-digital converter accesses the fourth signal and starts to convert the analog signal.
By adopting the technical scheme, the control signal for controlling the analog signal to start analog-to-digital conversion is electrically isolated through the second isolation circuit.
Optionally, the digital isolation circuit further includes a third isolation circuit;
and a chip selection end, a clock signal end, a data output end and an AD conversion indicating end of the analog-to-digital converter are used as the first synchronous serial interface and are respectively connected with a signal input end of the third isolation circuit.
By adopting the technical scheme, the chip selection end, the clock signal end and the data output end are used as the first synchronous serial interface, so that the communication between the digital isolation circuit and the analog-to-digital converter is completed, the electrical isolation between the digital isolation circuit and the single chip microcomputer is also completed, and meanwhile, fewer isolation devices are used in the mode.
Optionally, the acquisition circuit includes four current circuits and three voltage circuits; each current circuit comprises a current sampling circuit; each voltage circuit comprises a voltage sampling circuit;
the four current sampling circuits respectively collect currents of three phase lines and one neutral line, convert the collected currents into voltages and output the converted voltages to the analog-to-digital converter;
the three voltage sampling circuits respectively collect voltages of three phase lines and output the sampled voltages to the analog-to-digital converter.
By adopting the technical scheme, the multichannel analog-to-digital converter synchronously samples the four-way voltage and the three-way voltage, ensures that the voltage and the circuit can be simultaneously sampled, and meets the measurement requirements of high-precision phase and reactive power.
Optionally, each of the current circuits further includes a first protection circuit;
one input end of the first protection circuit is connected with one phase line of the three-phase power, and one output end of the first protection circuit is connected with a load end; and the other input end and the other output end of the first protection circuit are respectively connected with the current sampling circuit.
Through adopting above-mentioned technical scheme, first protection circuit converts the heavy current of gathering into the undercurrent, and CT's transformation ratio is about several thousand to one to can provide electrical isolation, the security performance is high.
Optionally, each of the current circuits further includes two filter circuits;
one end of the filter circuit is connected between the first protection circuit and the current sampling circuit;
the other end of the filter circuit is grounded.
By adopting the technical scheme, the two filter circuits have the filtering function, and can inhibit and prevent interference.
Optionally, each voltage circuit further includes a voltage divider circuit;
one end of the voltage division circuit is connected with one phase line of the three-phase power, and the other end of the voltage division circuit is connected with the voltage sampling circuit in series.
By adopting the technical scheme, the voltage division circuit has the function of voltage division and acquires bipolar signals, namely high-impedance voltage signals.
Optionally, each voltage circuit further includes a buffer circuit;
one end of the buffer circuit is connected with the common end of the voltage division circuit and the voltage sampling circuit;
and the other end of the buffer circuit is connected with the analog-to-digital converter.
By adopting the technical scheme, the buffer circuit conditions the bipolar signal of the high-impedance voltage signal obtained after voltage division into the bipolar signal of the low-impedance voltage signal.
Optionally, each voltage circuit further includes a second protection circuit;
the second protection circuit is connected between the common end of the voltage division circuit and the voltage sampling circuit and the buffer circuit.
By adopting the technical scheme, the second protection circuit plays a role in protection, and the safety of the circuit is improved.
Drawings
Fig. 1 is a circuit diagram of a three-phase power acquisition circuit provided in this embodiment.
Fig. 2 is another circuit diagram of the three-phase power acquisition circuit provided in the present embodiment.
Fig. 3 is a circuit diagram of a current circuit for collecting the current of the first phase line according to this embodiment.
Fig. 4 is a chip circuit diagram of the analog-to-digital converter provided in the present embodiment.
Fig. 5 is a circuit diagram of a current circuit for collecting a second phase current according to the present embodiment.
Fig. 6 is a circuit diagram of a current circuit for collecting a current of a third phase line provided in the present embodiment.
Fig. 7 is a circuit diagram of a current circuit for collecting a neutral current according to the present embodiment.
Fig. 8 is a circuit diagram of a voltage circuit for collecting the voltage of the first phase line provided in this embodiment.
Fig. 9 is a circuit diagram of a voltage circuit for collecting the voltage of the second phase line provided in the present embodiment.
Fig. 10 is a circuit diagram of a voltage circuit for collecting a third phase line voltage provided in the present embodiment.
Fig. 11 is a circuit diagram of the first isolation circuit provided in this embodiment.
Fig. 12 is a circuit diagram of the second isolation circuit provided in the present embodiment.
Fig. 13 is a circuit diagram of a third isolation circuit provided in the present embodiment.
Description of reference numerals: l1, a first phase line; l2, second phase line; l3, third phase line; n, a neutral line; 1. an acquisition circuit; 11. a current circuit; CT1, current transformer; RJ7, current sampling resistor; c1, a first capacitance; c4, a second capacitor; RJ4, a first resistor; RJ10, a second resistor; U1D, first operational amplifier; RJ1, third resistor; RJ13, fourth resistor; 12. a voltage circuit; RJ18, a first divider resistor; RJ24, a second divider resistor; RJ27, third voltage dividing resistor; RJ25, fourth voltage dividing resistor; RJ19, fifth voltage-dividing resistor; RJ17, sixth voltage dividing resistor; RJ20, seventh voltage dividing resistor; RJ26, voltage sampling resistor; r1 and a protective resistor; U2B, a second operational amplifier; 2. an analog-to-digital converter; 3. a digital isolation circuit; 31. a first isolation circuit; r5, a first current limiting resistor; u5, a first optical coupler; r6, pull-down resistor; 32. a second isolation circuit; r4 and a second current limiting resistor; u4 and a second optical coupler; r3, pull-up resistor; c11, third capacitance; 33. a third isolation circuit; 4. a single chip microcomputer; 41. a DMA module; 42. a CPU.
Detailed Description
The present application is described in further detail below with reference to figures 1-12.
The embodiment of the application discloses three-phase electricity acquisition circuit 1. Referring to fig. 1, the digital signal processing circuit comprises an acquisition circuit 1, an analog-to-digital converter 2, a digital isolation circuit 3 and a single chip microcomputer 4. The acquisition circuit 1 is connected with the voltage and the current of three-phase power, the connected voltage and current are analog signals, the analog signals are output to the analog-to-digital converter 2, the analog-to-digital converter 2 is connected with the analog signals and converts the analog signals into digital signals, the digital signals are synchronously and serially communicated to the digital isolation circuit 3, the digital isolation circuit 3 is used for electrically isolating the connected digital signals, the circuit safety is guaranteed, and then the data are synchronously and serially communicated to the single chip microcomputer 4 for processing.
Referring to fig. 2, the three-phase power includes a first phase line L1, a second phase line L2, a third phase line L3, and a neutral line N; the acquisition circuit 1 comprises four current circuits 11, and each current circuit 11 comprises a first protection circuit, a current sampling circuit and two filter circuits.
Referring to fig. 3, for the current circuit 11 for collecting the current of the first phase line L1, the first protection circuit includes a current transformer CT1, and the current sampling circuit includes a current sampling resistor RJ 7. The first pin of the current transformer CT1 is connected with the current of a first phase line L1 in three-phase power, the fourth pin of the current transformer CT1 outputs the current to one end of a current sampling resistor RJ7, the other end of the current sampling resistor RJ7 outputs the current to the third pin of the current transformer CT1, and the second pin of the current transformer CT1 outputs the current to a load end. The resistance value of the current sampling resistor RJ7 can be several ohms to tens of ohms; the current transformer CT1 is used for converting large current into small current, i.e. generating a small current signal in the secondary side coil, the transformation ratio of the CT is about thousands to one, and electrical isolation is provided; the current sampling resistor RJ7 is used to convert the small current output from the current transformer CT1 into a voltage.
One of the filter circuits comprises a first capacitor C1, one end of the first capacitor C1 is connected between the current sampling resistor RJ7 and the third pin of the current transformer CT1, and the other end of the first capacitor C1 is grounded; the other filter circuit comprises a second capacitor C4, one end of the second capacitor C4 is connected between the current sampling resistor RJ7 and the fourth pin of the current transformer CT1, and the other end of the second capacitor C4 is grounded. The two filter circuits play a role in filtering.
The current sampling circuit further comprises a differential amplifying circuit, the differential amplifying circuit comprises a first resistor RJ4, a second resistor RJ10, a first operational amplifier U1D, a third resistor RJ1 and a fourth resistor RJ13, wherein the first resistor RJ4 and the second resistor RJ10 are kiloohm resistors, the resistance values of the first resistor RJ 3883 and the second resistor RJ10 are equal, the third resistor RJ1 and the fourth resistor RJ13 are hundreds of thousands of ohms, and the resistance values of the first resistor RJ4 and the second resistor RJ 3832 are equal.
The input end of the first resistor RJ4 is connected with the common end of the third pin of the current sampling resistor RJ7 and the current transformer CT1, and the input end of the second resistor RJ10 is connected with the common end of the fourth pin of the current sampling resistor RJ7 and the current transformer CT 1. The output terminal of the first resistor RJ4 is connected to the thirteenth pin of the first operational amplifier U1D, and the output terminal of the second resistor RJ10 is connected to the twelfth pin of the first operational amplifier U1D. The input end of the third resistor RJ1 is connected with the thirteenth pin of the first operational amplifier U1D, the output end of the third resistor RJ1 is connected with the fourteenth pin of the first operational amplifier U1D, one end of the fourth resistor RJ13 is connected with the common end of the second resistor RJ10 and the twelfth pin of the first operational amplifier U1D, and the other end of the fourth resistor RJ13 is grounded.
Referring to fig. 3 and 4, fig. 4 shows a chip circuit diagram of the analog-to-digital converter 2, in which the rc devices are standard peripheral circuits of the chip. The voltage signals at two ends of the current sampling resistor RJ7 are amplified through a differential amplification circuit, a voltage signal of 0 to +/-5V is output to the fifty-ninth pin of the analog-to-digital converter 2 at the fourteenth pin of the first operational amplifier U1D, the voltage obtained by the current sampling resistor RJ7 is a bipolar signal with high impedance, and the bipolar signal is conditioned into a bipolar signal with low impedance by the differential amplification circuit, so that the current sampling is completed.
Referring to fig. 4 and 5, fig. 5 shows a current circuit 11 for collecting the current of the second phase line L2, an output end of the current circuit 11 is connected to the sixteenth pin of the analog-to-digital converter 2, and the working principle thereof is the same as that of the current circuit 11 for collecting the current of the first phase line L1 in fig. 3, and details thereof are not repeated.
Referring to fig. 4 and 6, fig. 6 shows a current circuit 11 for collecting the current of the third phase line L3, an output end of the current circuit 11 is connected to the sixty-third pin of the analog-to-digital converter 2, and the working principle thereof is the same as that of the current circuit 11 for collecting the current of the first phase line L1 in fig. 3, and details thereof are not repeated.
Referring to fig. 4 and 7, fig. 7 shows a current circuit 11 for collecting the current of the neutral line N, an output end of the current circuit 11 is connected to the fifty-seventh pin of the analog-to-digital converter 2, and an operation principle thereof is consistent with the current circuit 11 for collecting the current of the first phase line L1 in fig. 3, and details thereof are not repeated.
Referring to fig. 2 and 8, the acquisition circuit 1 includes four voltage circuits 12, and each voltage circuit 12 includes a voltage dividing circuit, a voltage sampling circuit, a second protection circuit, and a buffer circuit.
For the voltage circuit 12 for collecting the voltage of the first phase line L1, the voltage dividing circuit includes a plurality of voltage dividing resistors, the voltage dividing resistors shown in this embodiment are seven, which are respectively a first voltage dividing resistor RJ18, a second voltage dividing resistor RJ24, a third voltage dividing resistor RJ27, a fourth voltage dividing resistor RJ25, a fifth voltage dividing resistor RJ19, a sixth voltage dividing resistor RJ17 and a seventh voltage dividing resistor RJ20, the seven voltage dividing resistors are sequentially connected in series, wherein an input end of the first voltage dividing resistor RJ18 is connected to the voltage of the first phase line L1 in the three-phase power.
The voltage sampling circuit comprises a voltage sampling resistor RJ26, one end of the voltage sampling resistor RJ26 is connected with the output end of the seventh voltage-dividing resistor RJ20, and the other end of the voltage sampling resistor RJ26 is grounded.
The second protection circuit comprises a protection resistor R1, the buffer circuit comprises a second operational amplifier U2B, the input end of the protection resistor R1 is connected with the common end of the voltage sampling resistor RJ26 and the seventh voltage dividing resistor RJ20, the output end of the protection resistor R1 is connected with the fifth pin of the second operational amplifier U2B, and the sixth pin of the second operational amplifier U2B is connected with the seventh pin.
Referring to fig. 4 and 8, a voltage signal of 0 to ± 5V is output to the fifty-third pin of the analog-to-digital converter 2 at the seventh pin of the second operational amplifier U2B, the voltage obtained by the voltage sampling resistor RJ26 is a high-impedance bipolar signal, and the buffer circuit conditions the bipolar signal into a low-impedance bipolar signal, thereby completing the sampling of the voltage.
Referring to fig. 9, fig. 9 shows a voltage circuit 12 for collecting the voltage of the second phase line L2, an output end of the voltage circuit 12 is connected to the fifty-first pin of the analog-to-digital converter 2, and the working principle thereof is the same as that of the voltage circuit 12 for collecting the voltage of the first phase line L1 in fig. 8, and details thereof are not repeated.
Referring to fig. 10, fig. 10 shows a voltage circuit 12 for collecting the voltage of the third phase line L3, an output end of the voltage circuit 12 is connected to the forty-ninth pin of the analog-to-digital converter 2, and the working principle thereof is consistent with the voltage circuit 12 for collecting the voltage of the first phase line L1 in fig. 8, and details thereof are not repeated.
Referring to fig. 4, the fifty-ninth pin, the sixty-first pin, the sixty-third pin, the fifty-seventh pin, the fifty-third pin, the fifty-first pin, and the forty-ninth pin of the analog-to-digital converter 2 input corresponding currents or voltages, and the currents and voltages of the three-phase power are sampled synchronously, so that the measurement accuracy of the phase, the power factor, and the reactive power is ensured.
The neutral line N is connected with the power grounds of the acquisition circuit 1 and the analog-to-digital converter 2, the common mode rejection capability is strong, the electric isolation effect is achieved, the influence between voltage circuit channels can be effectively reduced, and the anti-interference effect is good.
Referring to fig. 2, the digital isolation circuit 3 further includes a first isolation circuit 31, and referring to fig. 11, the first isolation circuit 31 includes a first current limiting resistor R5, a first optocoupler U5, and a pull-down resistor R6, where the first current limiting resistor R5 is a hundred ohm resistor, and the resistance of the pull-down resistor R6 may be tens of ohms to thousands of ohms.
A first pin of the first optical coupler U5 is connected with a power supply on the side of the single chip microcomputer 4, and a fourth pin of the first optical coupler U5 is connected with a power supply of the analog-to-digital converter 2. An IO interface of the single chip microcomputer 4 is connected with an input end of a first current limiting resistor R5, an output end of the first current limiting resistor R5 is connected with a second pin of a first optical coupler U5, and a third pin of the first optical coupler U5 is connected with an eleventh pin of the analog-to-digital converter 2. The first current limiting resistor R5 limits the magnitude of the current in the branch to prevent the current from being too large and burning out the series-connected components.
One end of the pull-down resistor R6 is connected between the third pin of the first optocoupler U5 and the eleventh pin of the analog-to-digital converter 2, and the other end of the pull-down resistor R6 is grounded. The pull-down resistor R6 pulls the level of the third pin of the first optocoupler U5 to a low level.
After the power supply on the side of the single chip microcomputer 4 and the power supply of the analog-to-digital converter 2 are switched on, a diode in the first optical coupler U5 is conducted, an IO interface of the single chip microcomputer 4 outputs a first signal to the input end of the first current limiting resistor R5, and a third pin of the first optical coupler U5 outputs a second signal to a eleventh pin of the analog-to-digital converter 2. The second signal is a reset signal of the analog-to-digital converter 2, and the analog-to-digital converter 2 starts to reset after accessing the second signal. The first signal is at a low level and the second signal is at a high level.
Referring to fig. 2, the digital isolation circuit 3 includes a second isolation circuit 32, and referring to fig. 12, the second isolation circuit 32 includes a second current limiting resistor R4, a second optocoupler U4, a pull-up resistor R3, and a third capacitor C11, where the second current limiting resistor R4 and the pull-up resistor R3 are all hundred ohm resistors.
The first pin of the second optical coupler U4 is connected with a power supply on the side of the single chip microcomputer 4, the IO interface of the single chip microcomputer 4 is connected with the input end of a second current-limiting resistor R4, the output end of the second current-limiting resistor R4 is connected with the second pin of the second optical coupler U4, and the fourth pin of the second optical coupler U4 is connected with the ninth pin and the tenth pin of the analog-to-digital converter 2 respectively. The second current limiting resistor R4 limits the magnitude of the current in the branch to prevent the current from being too large and burning out the series-connected components.
The sixth pin of the second optocoupler U4 is connected to a power supply of the analog-to-digital converter 2, which is at a voltage of 5V. One end of a pull-up resistor R3 is connected between a power supply of the analog-to-digital converter 2 and the sixth pin of the second optical coupler U4, the pull-up resistor R3 is also connected with the input end of the third capacitor C11, and the other end of the pull-up resistor R3 is connected with the fourth pin of the second optical coupler U4. The output end of the third capacitor C11 is connected with the fifth pin of the second optocoupler U4, and the common end of the third capacitor C11 and the fifth pin of the second optocoupler U4 is grounded. A fourth pin of the second optocoupler U4 is OC output and needs to be pulled to a high level by a pull-up resistor R3; the third capacitor C11 is a decoupling capacitor of the second optocoupler U4 and is used for filtering noise.
An IO interface of the singlechip 4 outputs a third signal to an input end of a second current limiting resistor R4, and a fourth pin of a second optocoupler U4 outputs a fourth signal to a ninth pin and a tenth pin of the analog-to-digital converter 2. The fourth signal is a start signal of the analog-to-digital converter 2, and is used for controlling the start of the analog-to-digital converter 2, and after the analog-to-digital converter 2 accesses the fourth signal, the analog signal starts to be converted into a digital signal. Wherein the third signal and the fourth signal are both high level.
The analog-to-digital converter 2 receives the reset signal first to perform reset, and then receives the start signal to start analog-to-digital conversion, so that the analog-to-digital converter 2 can start analog-to-digital conversion under the condition of normal power supply. The analog-to-digital converter 2 also needs to be reset after each end of operation.
Referring to fig. 2, the digital isolation circuit 3 further includes a third isolation circuit 33, referring to fig. 13, a twelfth pin of the analog-to-digital converter 2 is connected to a fourteenth pin of the third isolation circuit 33, a thirteenth pin of the analog-to-digital converter 2 is connected to a thirteenth pin of the third isolation circuit 33, a fourteenth pin of the analog-to-digital converter 2 is connected to a twelfth pin of the third isolation circuit 33, and a twenty-fourth pin of the analog-to-digital converter 2 is connected to an eleventh pin of the third isolation circuit 33. The twelfth pin of the analog-to-digital converter 2 is a clock signal end, the thirteenth pin of the analog-to-digital converter 2 is a chip selection end, the fourteenth pin of the analog-to-digital converter 2 is an AD conversion indication end, and the twenty-fourth pin of the analog-to-digital converter 2 is a data output end.
The clock signal end, the chip selection end and the data output end are a first synchronous serial interface of the analog-to-digital converter 2; the fourteenth pin, the thirteenth pin and the twelfth pin of the third isolation circuit 33 are signal input terminals, and the analog-to-digital converter 2 and the third isolation circuit 33 realize synchronous serial communication through the first synchronous serial interface and the signal input terminals, so that synchronous serial communication between the analog-to-digital converter 2 and the digital isolation circuit 3 is realized.
The third pin, the fourth pin and the sixth pin of the third isolation circuit 33 are signal output ends, and the signal output ends are connected with the second synchronous serial interface of the single chip microcomputer 4, so that synchronous serial communication between the third isolation circuit 33 and the single chip microcomputer 4 is realized, and synchronous serial communication between the digital isolation circuit 3 and the single chip microcomputer 4 is realized.
The second synchronous serial interface is connected with the DMA module 41 of the single chip microcomputer 4, and the DMA module 41 is connected with the CPU42 of the single chip microcomputer 4.
In the analog-to-digital conversion process of the analog-to-digital converter 2, a fourteenth pin of the analog-to-digital converter 2 outputs a first conversion signal to a twelfth pin of the third isolation circuit 33, and a fifth pin of the third isolation circuit 33 outputs a second conversion signal to the single chip microcomputer; wherein the first converted signal and the second converted signal are both at a high level. After the analog-to-digital conversion of the analog-to-digital converter 2 is finished, the fourteenth pin of the analog-to-digital converter 2 outputs a first conversion completion signal to the twelfth pin of the third isolation circuit 33, and the fifth pin of the third isolation circuit 33 outputs a second conversion completion signal to the single chip microcomputer; wherein the first and second transition completion signals are both low level.
After the analog-to-digital conversion of the analog-to-digital converter 2 is completed, the DMA module 41 controls the fourth pin of the third isolation circuit 33 to output the first chip selection signal, and the thirteenth pin of the third isolation circuit 33 outputs the second chip selection signal to the thirteenth pin of the analog-to-digital converter 2; wherein the second chip select signal is low. Next, the DMA module 41 controls the third pin of the third isolation circuit 33 to output the first clock signal, the fourteenth pin of the third isolation circuit 33 outputs the second clock signal to the twelfth pin of the analog-to-digital converter 2, and the twenty-fourth pin of the analog-to-digital converter 2 outputs the digital signal to the eleventh pin of the third isolation circuit 33 bit by bit, that is, the analog-to-digital converter 2 outputs serial data under the second clock signal, then the third isolation circuit 33 completes electrical isolation, the eleventh pin of the third isolation circuit 33 outputs the serial data to the DMA module 41, the DMA module 41 puts the received data into a memory block, and then notifies the CPU42 to manage and operate, at this time, the received data is real data, and the DMA module can send the whole block of data to the CPU 42.
Synchronous serial communication is adopted between the analog-to-digital converter 2 and the digital isolation circuit 3, and synchronous serial communication is adopted between the digital isolation circuit 3 and the single chip microcomputer 4, so that the number of used isolation devices can be greatly reduced, and the cost is reduced.
The DMA module 41 of the single chip microcomputer 4 manages the reception of the digital signal, and the received digital signal is processed and operated by the CPU42 of the single chip microcomputer 4. The DMA module 41 of the single chip microcomputer 4 is used for managing the digital signals received by the second synchronous serial interface, the frequency of interrupting the single chip microcomputer 4 is greatly reduced, the processing of other real-time tasks is not influenced, the single chip microcomputer 4 can process data in real time by using a complex algorithm, the single chip microcomputer 4 or a processor with high cost and high performance is not required, the number of devices for digital isolation is reduced to 1/3 to 1/4 in the prior art by using synchronous serial communication, and the cost is greatly reduced.
The implementation principle of a three-phase power acquisition circuit 1 in the embodiment of the application is as follows:
the acquisition circuit 1 synchronously acquires the current and voltage of the first phase line L1, the second phase line L2, and the third phase line L3 and the current of the neutral line N, converts the acquired current and voltage into a low-impedance bipolar signal, which is an analog signal and outputs the analog signal to the analog-to-digital converter 2.
The singlechip 4 outputs a first signal to the digital isolation circuit 3, the digital isolation circuit 3 outputs a second signal to the analog-to-digital converter 2, and the analog-to-digital converter 2 resets after receiving the second signal so as to ensure normal power supply.
The singlechip 4 outputs a third signal to the digital isolation circuit 3, the digital isolation circuit 3 outputs a fourth signal to the analog-to-digital converter 2, and the analog-to-digital converter 2 starts to convert the analog signal into a digital signal after receiving the fourth signal, wherein the digital signal can be 16 bits.
After the analog-to-digital conversion of the analog-to-digital converter 2 is completed, under the condition that the digital isolation circuit 3 receives the second clock signal, the digital signal is output bit by bit through the first synchronous serial interface, that is, the analog-to-digital converter 2 outputs serial data to the digital isolation circuit 3, after the digital isolation circuit 3 performs electrical isolation, the DMA module 41 controls the second synchronous serial interface to access the serial data, and then the DMA module 41 prepares all the received data and notifies the CPU42 of data processing and operation.
The above are preferred embodiments of the present application, and the scope of protection of the present application is not limited thereto, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.
Claims (10)
1. A three-phase electricity acquisition circuit is characterized in that: the system comprises an acquisition circuit, an analog-to-digital converter, a digital isolation circuit and a singlechip;
the acquisition circuit is respectively connected with three phase lines and a neutral line in three-phase power, and the output end of the acquisition circuit is connected with the input end of the analog-to-digital converter;
the first synchronous serial interface of the analog-to-digital converter is connected with the signal input end of the digital isolation circuit;
the signal output end of the digital isolation circuit is connected with a second synchronous serial interface of the singlechip;
the second synchronous serial interface is connected with a DMA module of the single chip microcomputer, and the DMA module is connected with a CPU of the single chip microcomputer.
2. The three-phase power acquisition circuit of claim 1, wherein: the digital isolation circuit further comprises a first isolation circuit;
the singlechip outputs a first signal to the first isolation circuit;
the first isolation circuit is connected with a first signal and outputs a second signal to the analog-to-digital converter;
and the analog-to-digital converter is connected with a second signal for resetting.
3. The three-phase power acquisition circuit of claim 2, wherein: the digital isolation circuit comprises a second isolation circuit;
the singlechip outputs a third signal to the second isolation circuit;
the second isolation circuit is connected with a third signal and outputs a fourth signal to the analog-to-digital converter;
and the analog-to-digital converter accesses the fourth signal and starts to convert the analog signal.
4. A three-phase power acquisition circuit according to claim 3, characterized in that: the digital isolation circuit further comprises a third isolation circuit;
and a chip selection end, a clock signal end and a data output end of the analog-to-digital converter are used as the first synchronous serial interface and are respectively connected with a signal input end of the third isolation circuit.
5. The three-phase power acquisition circuit according to any one of claims 1 to 4, characterized in that: the acquisition circuit comprises four current circuits and three voltage circuits; each current circuit comprises a current sampling circuit; each voltage circuit comprises a voltage sampling circuit;
the four current sampling circuits respectively collect currents of three phase lines and one neutral line, convert the collected currents into voltages and output the converted voltages to the analog-to-digital converter;
the three voltage sampling circuits respectively collect voltages of three phase lines and output the sampled voltages to the analog-to-digital converter.
6. The three-phase power acquisition circuit of claim 5, wherein: each current circuit further comprises a first protection circuit;
one input end of the first protection circuit is connected with one phase line of the three-phase power, and one output end of the first protection circuit is connected with a load end; and the other input end and the other output end of the first protection circuit are respectively connected with the current sampling circuit.
7. The three-phase power acquisition circuit of claim 6, wherein: each current circuit also comprises two filter circuits;
one end of the filter circuit is connected between the first protection circuit and the current sampling circuit;
and the other end of the filter circuit is grounded.
8. The three-phase power acquisition circuit of claim 5, wherein: each voltage circuit also comprises a voltage division circuit;
one end of the voltage division circuit is connected with one phase line of the three-phase power, and the other end of the voltage division circuit is connected with the voltage sampling circuit in series.
9. The three-phase power acquisition circuit of claim 8, wherein: each voltage circuit further comprises a buffer circuit;
one end of the buffer circuit is connected with the common end of the voltage division circuit and the voltage sampling circuit;
and the other end of the buffer circuit is connected with the analog-to-digital converter.
10. The three-phase power acquisition circuit of claim 9, wherein: each voltage circuit further comprises a second protection circuit;
the second protection circuit is connected between the common end of the voltage division circuit and the voltage sampling circuit and the buffer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220039533.0U CN217181048U (en) | 2022-01-06 | 2022-01-06 | Three-phase electricity acquisition circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220039533.0U CN217181048U (en) | 2022-01-06 | 2022-01-06 | Three-phase electricity acquisition circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217181048U true CN217181048U (en) | 2022-08-12 |
Family
ID=82732584
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220039533.0U Active CN217181048U (en) | 2022-01-06 | 2022-01-06 | Three-phase electricity acquisition circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217181048U (en) |
-
2022
- 2022-01-06 CN CN202220039533.0U patent/CN217181048U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205982509U (en) | Hollow parallel reactor turn -to -turn short circuit on -line monitoring system of dry -type | |
| CN104020346A (en) | Micro-current signal extraction system | |
| CN103413747B (en) | Space plasma measurement apparatus | |
| CN105572453A (en) | Voltage acquisition electronic sensor apparatus | |
| CN107666300A (en) | Signal filtering process Compare System based on analog-digital converter | |
| CN101984418B (en) | Multi-channel parallel isolated data acquisition device based on PXI bus | |
| CN203479876U (en) | Digital multimeter based on PXI/PCI bus | |
| CN217181048U (en) | Three-phase electricity acquisition circuit | |
| CN209417268U (en) | A kind of parameter testing diagnostic machine of the pulse power | |
| CN210109188U (en) | Electric information sampling circuit | |
| CN110850761A (en) | High-precision analog quantity acquisition circuit | |
| CN110609164A (en) | AC/DC voltage acquisition circuit of data acquisition recorder | |
| CN207516439U (en) | Alternating current acquisition module and detection device | |
| CN104931814A (en) | Digital isolation type grid detector | |
| CN204758714U (en) | Isolated electric wire netting detector of digit | |
| CN113884963A (en) | High-precision direct-current standard electric energy meter | |
| CN218584881U (en) | Three-phase four-wire electric energy metering circuit and electric energy meter | |
| CN203179278U (en) | Sensor signal acquisition module based on optical fiber communication technology | |
| CN110824220A (en) | Novel signal acquisition circuit of electronic sensor | |
| CN218567469U (en) | Three-phase four-wire electric energy metering circuit and electric energy meter | |
| CN204216846U (en) | Based on the photovoltaic combiner box measure and control device of sample resistance | |
| CN210775823U (en) | Rogowski coil electronic transformer frequency aliasing characteristic testing device | |
| CN217642697U (en) | Multifunctional detection device for secondary voltage of transformer substation | |
| CN216670097U (en) | Iron core grounding current detection device | |
| CN218470897U (en) | Transformer core and partial discharge online monitoring device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |