CN217158196U - Transistor with a metal gate electrode - Google Patents
Transistor with a metal gate electrode Download PDFInfo
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- CN217158196U CN217158196U CN202220953315.8U CN202220953315U CN217158196U CN 217158196 U CN217158196 U CN 217158196U CN 202220953315 U CN202220953315 U CN 202220953315U CN 217158196 U CN217158196 U CN 217158196U
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Abstract
A transistor includes a substrate, a channel, a gate dielectric layer, a gate, a source and a drain. The channel is formed on the surface of the substrate and is provided with a buffer layer, a first semiconductor layer formed on the buffer layer and a second semiconductor layer formed on the first semiconductor layer, wherein the surface of the first semiconductor layer is provided with a plurality of micro-holes, and the second semiconductor layer fills the micro-holes. The grid dielectric layer is formed on the second semiconductor layer; the grid is formed on the grid dielectric layer; the source electrode is formed on one side of the channel and connected with the channel; the drain is formed at the other side opposite to the side of the channel and connected to the channel. The second semiconductor layer can fill micro-cavities on the surface of the first semiconductor layer caused by epitaxial growth, so that the problem of leakage current is solved.
Description
Technical Field
The present invention relates to a transistor, and more particularly to a transistor with low leakage current.
Background
First generation semiconductor silicon (Si) makes it suitable for power semiconductors based on its having an energy gap of 1.17eVA body device. However, as IC process technology has been continuously developed, semiconductor devices have been increasingly miniaturized, and there is a demand for IC logic operation, and so on, the related art industry has been developing second generation semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP), and third generation semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), and has been concerned in recent years with gallium oxide (Ga) having a band gap as high as 4.9eV 2 O 3 ) Such a fourth generation semiconductor.
For the related industries in the field, the challenges of fabricating Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) on sapphire substrates or SOI substrates are not limited to the problems of poor thickness, lattice mismatch, surface defects (e.g., surface micro-bumps, micro-cavities), and voids caused by GaN buffer layers.
Referring to fig. 1 and 2, for example, taiwan patent application No. TWI715311 (hereinafter referred to as "japanese patent application 1") discloses a metal oxide silicon semiconductor field effect transistor (Si MOSFET)1 having a wide energy gap iii-v group drain (drain) and a method for fabricating the same. The prior art 1 employs Metal Organic Chemical Vapor Deposition (MOCVD) to selectively grow a GaN drain 12 at a hundreds of nano-scale holes 100 of a (111) crystal plane of a silicon wafer 11 of an SOI substrate 10, so that single-crystal hexagonal gallium nitride (h-GaN) can start to grow from above the (111) crystal plane of the silicon wafer 11, which can end at the slope of the hundreds of nano-scale holes 100 during the dislocation (dislocation) of the crystallization process, and high-crystallinity cubic gallium nitride (c-GaN) can be obtained when h-GaN is merged in the middle of the hundreds of nano-scale holes 100. The foregoing solution 1 solves the aforementioned lattice mismatch problem, and also increases the breakdown voltage of the silicon semiconductor high field effect transistor 1 by the GaN drain 12.
Although the foregoing lattice mismatch problem can be solved by the foregoing scheme 1; however, the thickness difference caused by MOCVD film formation (e.g., the microbump/thickness difference between the GaN drain 12 and the silicon wafer 11 shown in fig. 2) is also a major factor affecting the leakage current and breakdown voltage of the fet.
As can be seen from the above description, it is a subject to be broken by those skilled in the art of the present application to solve the problem of leakage current of a transistor by improving the problem of thickness difference caused by MOCVD film formation.
Disclosure of Invention
The utility model aims to provide a transistor of the poor problem of thickness that improves MOCVD filming and causes in order to reduce the leakage current problem.
The utility model discloses a transistor, including base plate, passageway, grid dielectric layer, grid, source electrode, and drain electrode. The channel is formed on the surface of the substrate and is provided with a buffer layer, a first semiconductor layer formed on the buffer layer and a second semiconductor layer formed on the first semiconductor layer, wherein the surface of the first semiconductor layer is provided with a plurality of micro-cavities, and the second semiconductor layer fills the micro-cavities. The gate dielectric layer is formed on the second semiconductor layer of the channel. The gate is formed on the gate dielectric layer. The source electrode is formed on one side of the channel and connected with the channel. The drain is formed on the other side opposite to the side of the channel and connected to the channel.
The transistor of the present invention, the second semiconductor layer of the channel has a thickness of 500nm or less.
The transistor of the present invention, the second semiconductor layer of the channel further has an average surface roughness of less than 10 nm.
The beneficial effects of the utility model reside in that: the second semiconductor layer can fill micro-holes on the surface of the first semiconductor layer caused by epitaxial growth, thereby improving the problem of leakage current.
Drawings
Other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings, in which:
FIG. 1 is a schematic front view of a MOSFET with wide-bandgap three-five-group drains disclosed in Taiwan patent application No. TWI 715311;
FIG. 2 is a Scanning Electron Microscope (SEM) image illustrating surface defects of the MOSFET of FIG. 1;
fig. 3 is a schematic front view illustrating a step (a) of a method of fabricating an embodiment of a transistor according to the present invention;
FIG. 4 is a schematic front view illustrating a step (b) of the manufacturing method according to the embodiment of the present invention;
fig. 5 is a schematic front view illustrating a step (c) of the manufacturing method according to the embodiment of the present invention;
fig. 6 is a schematic front view illustrating a step (d) of the manufacturing method according to the embodiment of the present invention;
fig. 7 is an atomic force microscope (hereinafter, AFM) image illustrating the average surface roughness (Ra) of a second semiconductor layer obtained in step (d) of the manufacturing method according to the embodiment of the present invention;
fig. 8 is an AFM three-dimensional image illustrating the average surface roughness (Ra) three-dimensional image obtained through the step (d) of the manufacturing method according to the embodiment of the present invention;
fig. 9 is a schematic front view illustrating a step (e) of the manufacturing method according to the embodiment of the present invention;
fig. 10 is a schematic front view illustrating a step (f) of the manufacturing method according to the embodiment of the present invention;
fig. 11 is a schematic front view illustrating a step (g) of the manufacturing method according to the embodiment of the present invention; and
fig. 12 is a schematic front view illustrating a step (h) of the method of the present embodiment of the invention and illustrating the finally obtained transistor.
Detailed Description
An embodiment of the transistor of the present invention is shown in fig. 12, and the manufacturing method of the embodiment includes the following steps: a step (a), a step (b), a step (c), a step (d), a step (e), a step (f), a step (g), and a step (h).
Referring to fig. 3, the step (a) is to epitaxially grow a buffer layer (not shown) and a first semiconductor layer 31 on a surface of a substrate 2 by MOCVD in sequence. The buffer layer and the first semiconductor layer 31 are made of a GaN-based semiconductor material, and a surface of the first semiconductor layer 31 has a plurality of MOCVD-induced micro-bumps 311 and a plurality of micro-cavities 312. The substrate 2 suitable for use in this embodiment of the invention is a substrate selected from the group consisting of: sapphire, silicon carbide (SiC), and SOI. In the embodiment of the present invention, the substrate 2 is a sapphire substrate, the buffer layer and the first semiconductor layer 31 are made of GaN, and the thickness of the buffer layer and the first semiconductor layer 31 is between 0.1nm to 50nm and 700 μm to 2000 μm, but not limited thereto.
Referring to fig. 4, in the step (b), the first semiconductor layer 31 is planarized to remove the microbumps 311 on the surface of the first semiconductor layer 31, and the microholes 312 are left on the surface of the first semiconductor layer 31. Preferably, the planarization in step (b) of the method for manufacturing a transistor according to the embodiment of the present invention is performed by applying a chemical-mechanical polishing (CMP) technique to the first semiconductor layer 31.
Referring to fig. 5, the step (c) grows a second semiconductor layer 32 on the surface of the first semiconductor layer 31 of the step (b) by using an ALD technique to fill the micro-cavities 312. The second semiconductor layer 32 is composed of Ga and at least one element selected from the group consisting of: o and N; one surface of the second semiconductor layer 32 has Ga vacancies 321 and vacancies of at least one of the foregoing elements (see fig. 6, e.g., N vacancies 322) formed by precursors (precursors) that are not completely reacted during the ALD process. In the embodiment of the present invention, the second semiconductor layer 32 is made of GaN. Although the second semiconductor layer 32 is made of GaN in the embodiment of the present invention, it is not limited thereto. It should be appreciated that the second semiconductor layer 32 is ultimately used as a channel for a transistor when the transistor is fabricated; therefore, the second semiconductor layer 32 may be formed of Ga2O3 having a larger energy gap than GaN.
Referring to fig. 6, in the step (d), an etching process containing an etchant 8 is applied to the second semiconductor layer 32 in the step (c) to repair the vacancy (e.g., Ga vacancy 321 and N vacancy 322 of the embodiment) on the surface of the second semiconductor layer 32, so as to planarize the surface of the second semiconductor layer 32, and remove the second semiconductor layer 32Surface defects (surface defects); wherein the etchant 8 contains halogen element and at least one of the elements. The halogen element suitable for the etchant 8 of the present invention is selected from F or Cl. Preferably, the etching process of step (d) is selected from a wet etching method (wet etching) or a dry etching method (dry etching). More preferably, the etching process of step (d) is a dry etching method. In the embodiment of the present invention, the dry etching method is an Atomic Layer Etching (ALE) technique. The etchant 8 suitable for the ALE technique of this step (d) of the present invention is a gas molecule selected from the group consisting of: NF 3 And POCl 3 . In this embodiment of the invention, the etchant 8 is NF 3 The gas molecules are illustrated by way of example, but not by way of limitation.
As shown in fig. 6, in detail, the second semiconductor layer 32 of step (d) is performed in an ALE chamber (not shown) while the etchant 8 (NF) is present 3 Gas molecules) is introduced into the ALE reaction chamber, NF 3 Fluorine atoms in gas molecules are dissociated into anions (3F) － ) And anion (3F) － ) Will react with adatoms (atoms; that is, Ga vacancy 321) is converted into a nanoscale byproduct (GaF) 3 )80, followed by the nanoscale byproduct (GaF) by argon (Ar, not shown) introduced into the ALE reaction chamber 3 )80 are desorbed from the surface of the second semiconductor layer 32 and carried away from the ALE chamber, and the dissociated N also repairs the N vacancy 322 at the surface of the second semiconductor layer 32 to complete a cycle of ALE. It can be seen that the etching process performed in step (d) of the present embodiment can achieve a nano-level polishing effect, not only can planarize the surface of the second semiconductor layer 32, but also can remove the surface defects of the second semiconductor layer 32 to improve the problem of shallow impurities (shallow impurities). Therefore, after the step (d) is performed, the second semiconductor layer 32 has an average surface roughness (Ra) of 10nm or less. In the embodiment of the present invention, the average surface roughness (Ra) of the second semiconductor layer 32 is about 0.31nm as shown in fig. 7 and 8.
More specifically, each ALE cycle described in step (d) includes the following steps in sequence: one step (d1), one step (d2), one step (d3), and one step (d 4).
The sub-step (d1) is to perform a surface treatment process. Further, an oxygen body is introduced into the ALE chamber (not shown) to ionize the oxygen gas into oxygen plasma by a high voltage, thereby oxidizing the surface of the second semiconductor layer 32.
The sub-step (d2) is to perform an etchant dipping (rinsing) process. Further, NF is introduced into the ALE reaction chamber 3 Gas molecules to dissociate the aforementioned NF by high voltage 3 Gas molecules, the F atoms of which are electrically dissociated into 3F － To order 3F － The nano-scale by-product (GaF) is synthesized with the Ga vacancy 321 on the surface of the second semiconductor layer 32 3 )80。
The sub-step (d3) is to perform a desorption process. Further, Ar is introduced into the ALE chamber to dissociate the Ar into Ar plasma by high voltage, so that the nanoscale byproduct (GaF) 3 )80 are desorbed from the surface of the second semiconductor layer 32.
The sub-step (d4) is to perform a purge process. Further, Ar is introduced into the ALE reaction chamber to remove nano-sized byproducts (GaF) desorbed from the surface of the second semiconductor layer 32 3 )80 and carried away from the ALE reaction chamber.
Preferably, an electrode output power, a reaction time and a cycle number in performing the sub-step (d1), the sub-step (d2) and the sub-step (d3) are respectively between 100W and 300W, between 5 s and 10 s and between 25 s and 100 s.
Referring to fig. 9, in the step (e), a channel 3 is defined in the buffer layer, the first semiconductor layer 31 and the second semiconductor layer 32. Specifically, the step (e) defines the channel 3 through photolithography, etching, and other processes, and the means for defining the channel 3 is not the technical focus of the present invention, and will not be described herein. As can be seen from the detailed description of the ALE described in step (d), the ALE can provide a nano-scale polishing effect for the second semiconductor layer 32. Therefore, it is preferable that the second semiconductor layer 32 of the channel 3 has a thickness of 500nm or less, and the second semiconductor layer 32 of the channel 3 has an average surface roughness of 10nm or less. In this embodiment of the present invention, the thickness of the second semiconductor layer 32 is about 100nm, and as described above, the average surface roughness (Ra) is about 0.31 nm.
Referring to fig. 10, step (f) is to form a gate dielectric layer 4 over the channel 3.
Referring to fig. 11, step (g) is to form a gate 5 on the gate dielectric layer 4.
Referring to fig. 12, the step (h) is to form a source electrode 6 and a drain electrode 7 on one side of the channel 3 and the other side opposite to the one side, respectively.
As can be seen from the detailed description of the manufacturing method of the embodiment of the present invention, the transistor manufactured by the manufacturing method of the embodiment of the present invention is shown in fig. 12, and includes the substrate 2, the channel 3 formed on the surface of the substrate 2, the gate dielectric layer 4, the gate 5, the source 6, and the drain 7.
The channel 3 comprises the buffer layer (not shown), the first semiconductor layer 31 formed on the buffer layer and the second semiconductor layer 32 formed on the first semiconductor layer 31, wherein the buffer layer and the first semiconductor layer 31 are made of GaN-based semiconductor material, the first semiconductor layer 31 has the micro-cavities 312 on the surface, the second semiconductor layer 32 fills the micro-cavities 312 and is GaN, or Ga, sequentially prepared by ALD and ALE shown in FIG. 6 2 O 3 Or GaO x N y 。
The gate dielectric layer 4 is formed on the second semiconductor layer 32 of the channel 3; the gate 5 is formed on the gate dielectric layer 4. The source electrode 6 is formed at one side of the channel 3 and connected to the channel 3. The drain electrode 7 is formed on the other side opposite to the side of the channel 3 and connects the channel 3.
To sum up, the transistor of the present invention, which is implemented by the CMP technique after MOCVD, not only can improve the thickness difference problem caused by MOCVD, but also can fill up the micro-hole 312 caused by MOCVD on the surface of the first semiconductor layer 31 to solve the leakage current problem, and also can repair the Ga vacancy 321 on the surface of the second semiconductor layer 32 to make it reach the nano-level polishing effect and thus solve the problem of shallow impurities, so as to achieve the objective of the present invention.
The above mentioned embodiments are only examples of the present invention, and the scope of the present invention should not be limited thereby, and all the simple equivalent changes and modifications made according to the claims and the contents of the specification of the present invention are still included in the scope of the present invention.
Claims (3)
1. A transistor, characterized by: comprises the following steps:
a substrate;
the channel is formed on the surface of the substrate and provided with a buffer layer, a first semiconductor layer formed on the buffer layer and a second semiconductor layer formed on the first semiconductor layer, the surface of the first semiconductor layer is provided with a plurality of micro-holes, and the second semiconductor layer fills the micro-holes;
a gate dielectric layer formed on the second semiconductor layer of the channel;
a gate formed on the gate dielectric layer;
a source electrode formed at one side of the channel and connected to the channel; and
and a drain electrode formed at the other side opposite to the side of the channel and connected to the channel.
2. The transistor of claim 1, wherein: the second semiconductor layer of the channel has a thickness of 500nm or less.
3. The transistor of claim 2, wherein: the second semiconductor layer of the channel also has an average surface roughness of 10nm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220953315.8U CN217158196U (en) | 2022-04-24 | 2022-04-24 | Transistor with a metal gate electrode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220953315.8U CN217158196U (en) | 2022-04-24 | 2022-04-24 | Transistor with a metal gate electrode |
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| Publication Number | Publication Date |
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| CN217158196U true CN217158196U (en) | 2022-08-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202220953315.8U Active CN217158196U (en) | 2022-04-24 | 2022-04-24 | Transistor with a metal gate electrode |
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