CN217135174U - Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply - Google Patents
Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply Download PDFInfo
- Publication number
- CN217135174U CN217135174U CN202123272297.1U CN202123272297U CN217135174U CN 217135174 U CN217135174 U CN 217135174U CN 202123272297 U CN202123272297 U CN 202123272297U CN 217135174 U CN217135174 U CN 217135174U
- Authority
- CN
- China
- Prior art keywords
- power supply
- equivalent load
- output end
- circuit
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a reduce the circuit that newly-increased equipment capacity equivalent load strikeed to the power, belong to the field of charging control circuit, when charging for load electric capacity in the circuit that solves now, instantaneous charging current arouses power chip overcurrent protection or causes other circuit inoperative technical problem. Includes a power supply J 1 Current limiting resistor R 1 And integrating the unipolar transistor module with a capacitive equivalent load C1, wherein: the output end of the power supply is the integrated sheetThe input ends of the polar transistor modules are connected in parallel with the current limiting resistor R 1 And is provided with a voltage input terminal V IN (ii) a The output end of the integrated unipolar transistor module is connected with the input end of the capacitive equivalent load C1, the output end of the integrated unipolar transistor module and the input end of the capacitive equivalent load C1 are connected with a power VCC, and the capacitive equivalent load C1 and the output end of the integrated unipolar transistor module are grounded. Reducing load capacitance C 1 The power supply overcurrent protection is caused by the instantaneous impact of the power supply VCC at the moment of power-on.
Description
Technical Field
The utility model belongs to the technical field of the control circuit that charges, especially, relate to a reduce circuit that newly-increased equipment capacitive equivalent load assaulted the power.
Background
With the development of microelectronic technology, stable power supply is the key point for the normal operation of the whole electronic system, and power chips with overcurrent and overvoltage protection functions are applied in large scale to drive the load circuit to operate, but due to the capacitive load characteristic of the load circuit, at the moment of electrifying the load, the capacitive load is equivalent to a short circuit to the ground, so an instantaneous charging current can be generated in a circuit loop, the overcurrent protection of a power chip or the large instantaneous voltage drop of the power output can be caused to influence the work of other circuits or the damage of electronic components, for example, the load capacitance causes the instantaneous large current of the power supply at the moment of power-on, which causes the overcurrent protection of the power supply chip to shut down the equipment, or the instant of power-up of the load capacitor causes the power supply to generate a large voltage drop instantly, thereby affecting the operation of other circuits or the operation of other electronic equipment of the power supply is abnormal.
In view of this, the present invention is especially provided.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a reduce newly-increased circuit that equipment capacity equivalent load assaulted the power, when charging for load capacitance in solving current circuit, because instantaneous charging current arouses power chip overcurrent protection or causes other circuit inoperative technical problem. The technical scheme of the scheme has a plurality of technical beneficial effects, which are introduced as follows:
a circuit for reducing the impact of capacitive equivalent load on power supply of newly added equipment is provided, which comprises a power supply J 1 Current limiting resistor R 1 And integrating the unipolar transistor module with a capacitive equivalent load C1, wherein:
the output end of the power supply is connected with the input end of the integrated unipolar transistor module and is connected with the current-limiting resistor R in parallel 1 And is provided with a voltage input terminal V IN ；
The output end of the integrated unipolar transistor module is connected with the input end of the capacitive equivalent load C1, the output end of the integrated unipolar transistor module and the input end of the capacitive equivalent load C1 are connected with a power supply VCC, and the capacitive equivalent load C1 and the output end of the integrated unipolar transistor module are grounded;
the integrated unipolar transistor module is arranged at the voltage input end V IN When a preset voltage is input, the capacitive equivalent load C can be reduced or lowered 1 For the input terminal V IN The transient impact at the moment of power-up causes power supply overcurrent protection.
In a preferred or alternative embodiment, the integrated unipolar transistor module comprises a complementary circuit consisting of an enhancement-type PMOS transistor M1 and an NMOS transistor M2, and the capacitive equivalent load C can be reduced or lowered 1 For the voltage input terminal V IN The transient impact at the moment of power-up causes power supply overcurrent protection.
In a preferred or alternative embodiment, the source of the PMOS transistor M1 is connected to the output terminal of the power supply, the gate thereof is connected to the drain of the NMOS transistor M2, and the drain thereof is connected to the capacitive equivalent load C 1 The input ends of the two-way valve are connected;
the current limiting resistor R 1 Has an input end connected with the source electrode of the PMOS tube M1 and an output end connected with the drain electrode of the PMOS tube M1Connecting;
the source electrode of the NMOS tube M2 is grounded, and the grid electrode of the NMOS tube M2 and the capacitive equivalent load C 1 Is connected with the output end of the power supply.
In a preferred or optional embodiment, the voltage divider further comprises a voltage divider resistor R 2 、R 3 、R 4 And R 5 Wherein:
divider resistor R 2 With the output of the power supply and the current-limiting resistor R, respectively 1 Is connected with the input end of the voltage dividing resistor R 2 The output ends of the PMOS transistor and the NMOS transistor are respectively connected with the grid electrode of the PMOS transistor M1 and the drain electrode of the NMOS transistor M2;
voltage dividing resistor R 3 Respectively with said current-limiting resistor R 1 The output end of the NMOS transistor M2 is connected with the drain electrode of a PMOS transistor M1, and the output end of the PMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2;
voltage dividing resistor R 4 Respectively connected with a voltage dividing resistor R 2 The output end of the NMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2;
voltage dividing resistor R 5 Respectively with the gate of the NMOS transistor M2 and the voltage dividing resistor R 3 Is connected with the output end of the power supply.
In a preferred or alternative embodiment, the power supply J 1 Is a direct current power supply.
In a preferred or alternative embodiment, a power supply VCC is also included n N is a natural number, and each of the power supplies VCC n Corresponding to a capacitive load capacitor Cm, m is a natural number.
In a preferred or optional embodiment, a voltage dividing resistor R is disposed between adjacent power supplies VCC.
Compared with the prior art, the utility model provides a technical scheme includes following beneficial effect:
the circuit provided by the scheme can play a role of delaying or prolonging the charging time through the complementary circuit, reduce the over-current protection of the power supply caused by the instantaneous impact of the capacitive equivalent load C1 on the power supply at the power-on moment, cause the abnormal working of other load equipment on the power supply, and when V is used CC Voltage raising and power supply V IN When the current is consistent, the load capacitor can be charged by large current.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit diagram of the present invention;
fig. 2 is a schematic diagram of charging a plurality of load capacitors.
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, amount and ratio of the components in actual implementation can be changed at will, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that aspects may be practiced without these specific details. In order to make the technical field better understand the solution of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings and the detailed description. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
The circuit for reducing the impact of the capacitive equivalent load of the newly added device on the power supply shown in FIG. 1 comprises a power supply J 1 And a current limiting resistor R 1 And integrating unipolar transistor module, capacitive equivalent load C1 and power supply J 1 Preferably a DC charging power supply, the capacitive equivalent load can be a charging and discharging capacitor in the prior art or a capacitive load C 1 Or a rechargeable workload or other rechargeable power device, etc., wherein:
output end of power supply and integrated unipolar transistor moduleIs connected in parallel with a current limiting resistor R 1 And is provided with a voltage input end VIN;
the output end of the integrated unipolar transistor module is connected with the input end of a capacitive equivalent load C1, and the output end of the integrated unipolar transistor module and the input end of the capacitive equivalent load C1 are connected with a power supply V CC The capacitive equivalent load C1 is grounded with the output end of the integrated unipolar transistor module;
integrated unipolar transistor module at voltage input end V IN When a predetermined voltage is input, the load capacitance C can be reduced or lowered 1 For voltage input terminal V IN The instantaneous impact at the moment of power-on causes the overcurrent protection of the power supply, and the port V IN The power supply is provided with a control module, and the power supply can detect the current magnitude to cause the overcurrent protection of the power supply.
The complementary circuit functions as follows: power supply J 1 Transient stress current causes overcurrent protection of the power chip and influences the operation of other circuits or the operation of other electronic equipment of the power supply. The complementary circuit can start time delay or slow action, and reduce the over-current protection of the power supply caused by the transient impact of the load capacitor C1 on the power supply at the power-on moment, so that the other load devices on the power supply can not work normally. V CC Voltage raising and power supply V IN And can be applied to a load with a large current.
An embodiment of a complementary circuit is provided, for example, an integrated unipolar transistor module comprises a complementary circuit formed by an enhancement PMOS transistor M1 and an NMOS transistor M2, which can reduce or reduce the load capacitance C 1 For voltage input terminal V IN The transient impact at the moment of power-up causes power supply overcurrent protection. It should be emphasized that a depletion type MOS transistor cannot be used, and when the gate-source voltage Ugs of the depletion type MOS transistor is zero, the drain current is not zero, which affects the function of the whole circuit and increases the control deviation, specifically:
the source of PMOS transistor M1 is connected to the output of power supply, the gate is connected to the drain of NMOS transistor M2, and the drain is connected to load capacitor C 1 The input ends of the two-way valve are connected;
current limiting resistor R 1 The input end of the PMOS tube M1 is connected with the source electrode of the PMOS tube M1, and the output end of the PMOS tube M1The drain electrode of the PMOS tube M1;
the source of the NMOS transistor M2 is grounded, and the gate thereof is connected to the load capacitor C 1 Is connected with the output end of the power supply.
The MOS tube is started only by controlling the potential, the MOS tube serves as a switching tube and does not serve as a resistor, and the MOS tube further comprises a divider resistor R 2 、R 3 、R 4 And R 5 Wherein:
voltage dividing resistor R 2 Respectively connected with the output terminal of the power supply and the current-limiting resistor R 1 Is connected with the input end of a divider resistor R 2 The output end of the NMOS transistor is respectively connected with the grid electrode of the PMOS transistor M1 and the drain electrode of the NMOS transistor M2;
voltage dividing resistor R 3 Respectively with a current limiting resistor R 1 The output end of the NMOS transistor M2 is connected with the drain electrode of a PMOS transistor M1, and the output end of the PMOS transistor M1 is connected with the grid electrode of an NMOS transistor M2;
voltage dividing resistor R 4 Respectively connected with a voltage dividing resistor R 2 The output end of the NMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2;
voltage dividing resistor R 5 Respectively with the gate of the NMOS transistor M2 and the divider resistor R 3 Is connected with the output end of the power supply.
V IN At the moment of power-up, M 1 、M 2 Are all in an off state, and a power supply V IN By R 1 To C 1 (capacitive equivalent load) charging, R 1 The initial charging current is determined according to the equivalent load C of different capacitances 1 The size of the model is adjusted. With C 1 Charging voltage V CC Gradually increasing, at which time the partial pressures of R3 and R5 are such that M 2 Open (satisfy M) 2 Starting condition of (1), R 4 By M 2 Ground, R 2 And R 5 Partial pressure of M 1 Is turned on and power supply V IN By M 1 Conducting V CC ，V CC Voltage raising and power supply V IN And can be applied to a load with a large current.
As an embodiment provided in the present application, as shown in fig. 2, the power supply VCC is further included n N is a natural number, and each power supply VCC n Corresponding to a capacitive equivalent load C N N and N are natural numbers, a divider resistor R is provided at a high potential of a load capacitor between adjacent power supplies VCC, the divider resistors R may be the same or different, and are preferably provided in a stepwise decreasing manner, and generally, N or N is 5.
The product provided by the utility model is introduced in detail above. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the core concepts of the present invention. It should be noted that, for a person skilled in the art, without departing from the inventive concept of the present invention, several improvements and modifications can be made to the invention, and these improvements and modifications also fall within the scope of the claims of the invention.
Claims (7)
1. A circuit for reducing the impact of capacitive equivalent load of a newly added device on a power supply is characterized by comprising a power supply J 1 Current limiting resistor R 1 And integrating the unipolar transistor module and the capacitive equivalent load C 1 Wherein:
the output end of the power supply is connected with the input end of the integrated unipolar transistor module and is connected with the current-limiting resistor R in parallel 1 And is provided with a voltage input terminal V IN ；
The output end of the integrated unipolar transistor module is connected with the capacitive equivalent load C 1 And the output end of the integrated unipolar transistor module and a capacitive equivalent load C 1 Is connected with a power supply V CC Capacitive equivalent load C 1 The output end of the integrated unipolar transistor module is grounded;
the integrated unipolar transistor module is arranged at the voltage input end V IN When a preset voltage is input, the capacitive equivalent load C can be reduced or lowered 1 For the power supply V CC The transient impact at the moment of power-up causes power supply overcurrent protection.
2. The circuit of claim 1, wherein the integrated unipolar transistor module comprises a complementary circuit of an enhancement-type PMOS transistor M1 and an NMOS transistor M2, and is capable of reducing or reducing a capacitive equivalent load C 1 For the voltage input terminal V IN The transient impact at the moment of power-up causes power supply overcurrent protection.
3. The circuit of claim 2, wherein the source of the PMOS transistor M1 is connected to the output of the power supply, the gate thereof is connected to the drain of the NMOS transistor M2, and the drain thereof is connected to a capacitive equivalent load C 1 The input ends of the two-way valve are connected;
the current limiting resistor R 1 The input end of the transistor is connected with the source electrode of the PMOS transistor M1, and the output end of the transistor is connected with the drain electrode of the PMOS transistor M1;
the source electrode of the NMOS tube M2 is grounded, and the grid electrode of the NMOS tube M2 and the capacitive equivalent load C 1 Is connected with the output end of the power supply.
4. The circuit of claim 3, further comprising a voltage dividing resistor R 2 、R 3 、R 4 And R 5 Wherein:
voltage dividing resistor R 2 With the output of the power supply and the current-limiting resistor R, respectively 1 Is connected with the input end of the voltage dividing resistor R 2 The output ends of the PMOS transistor and the NMOS transistor are respectively connected with the grid electrode of the PMOS transistor M1 and the drain electrode of the NMOS transistor M2;
voltage dividing resistor R 3 Respectively with said current-limiting resistor R 1 The output end of the NMOS transistor M2 is connected with the drain electrode of a PMOS transistor M1, and the output end of the PMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2;
voltage dividing resistor R 4 Respectively connected with a voltage dividing resistor R 2 The output end of the NMOS transistor M1 is connected with the grid electrode of the NMOS transistor M2;
voltage dividing resistor R 5 Respectively with the gate of the NMOS transistor M2 and the voltage dividing resistor R 3 Is connected with the output end of the power supply.
5. The circuit of claim 1, wherein the power supply J is coupled to the power supply 1 Is a direct current power supply.
6. The circuit of claim 1, further comprising a power supply VCC n N is a natural number, and each of the power supplies VCC n Corresponding to a capacitive equivalent load C m And m is a natural number.
7. The circuit of claim 6, wherein a voltage dividing resistor R is disposed between adjacent power sources VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123272297.1U CN217135174U (en) | 2021-12-23 | 2021-12-23 | Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123272297.1U CN217135174U (en) | 2021-12-23 | 2021-12-23 | Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217135174U true CN217135174U (en) | 2022-08-05 |
Family
ID=82618599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123272297.1U Active CN217135174U (en) | 2021-12-23 | 2021-12-23 | Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217135174U (en) |
-
2021
- 2021-12-23 CN CN202123272297.1U patent/CN217135174U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW473786B (en) | Method and apparatus for reducing stress across capacitors used in integrated circuits | |
| CN101325411B (en) | Slow starting circuit for electrifying DC power supply | |
| CN203102064U (en) | Overshoot protection circuit of low-dropout linear regulator (LDO) and LDO | |
| CN101882926B (en) | A kind of power on reset circuit for constant-current driving chip | |
| CN105988495A (en) | LDO (Low Drop-out voltage regulator) overshooting protection circuit | |
| CN104362606A (en) | Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof | |
| CN109286181A (en) | Power clamp ESD protective circuit | |
| CN113328734A (en) | Fast blocking switch | |
| CN107565528A (en) | A kind of circuit structure for suppressing surge current | |
| WO2016184026A1 (en) | Circuit for slowly starting power supply loop to discharge electricity | |
| CN217135174U (en) | Circuit for reducing impact of capacitive equivalent load of newly-added equipment on power supply | |
| CN110445216B (en) | Charging chip | |
| CN106200763A (en) | Real Time Clock System based on pulsewidth modulation and method | |
| CN107947556A (en) | A kind of Switching Power Supply start-up circuit | |
| CN105867523B (en) | The mainboard of discharge circuit and the application discharge circuit | |
| CN108111150B (en) | Power-on reset circuit, integrated circuit and EEPROM system | |
| CN108829174A (en) | Linear regulator circuit | |
| CN212541261U (en) | Shutdown reset circuit and electronic equipment | |
| CN109473426B (en) | Electrostatic discharge circuit and electronic device | |
| TWI501498B (en) | Esd protection circuit and esd protection method thereof | |
| TWI779942B (en) | Electrical discharge circuit having stable discharging mechanism | |
| CN104104070A (en) | Surge current regulating circuit | |
| KR102627169B1 (en) | current limiting circuit | |
| TWI792767B (en) | Electrical discharge circuit having stable discharging mechanism | |
| CN110798187B (en) | Power-on reset circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |