CN217085191U - Aging board for integrated circuit chip - Google Patents
Aging board for integrated circuit chip Download PDFInfo
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- CN217085191U CN217085191U CN202221576635.2U CN202221576635U CN217085191U CN 217085191 U CN217085191 U CN 217085191U CN 202221576635 U CN202221576635 U CN 202221576635U CN 217085191 U CN217085191 U CN 217085191U
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Abstract
The utility model discloses integrated circuit chip's ageing board, which comprises a chip, eight pins are respectively stretched out to the left and right sides of chip, first pin connects the one end that first direct current constant voltage power supply reconnected first input capacitance, the other end ground connection of first input capacitance, the sixteenth pin connects the one end that second direct current constant voltage power supply reconnected second input capacitance, input capacitance's other end ground connection, eighth pin and ninth pin ground connection, second pin, third pin, fourth pin, fifth pin, sixth pin, seventh pin, tenth pin, eleventh pin, twelfth pin, thirteenth pin, fourteenth pin, fifteenth pin connect an input \ output resistance's one end separately, another termination digital signal of input \ output resistance inputs. The utility model discloses with a burn-in board can accomplish the burn-in test of seven model devices, reduced the experimental hardware cost of burn-in, be convenient for deposit and arrange in order.
Description
Technical Field
The utility model relates to an integrated circuit's the field of smelting always, concretely relates to integrated circuit chip's board of smelting always.
Background
When a batch of products are manufactured, due to the fact that the devices have inherent defects or are influenced by various factors such as improper control of a manufacturing process, the reliability of each component in the batch of products is different, and in order to guarantee the quality of the products, aging tests can be conducted on the components before the components leave a factory or before the components are used, and the components which are not qualified are removed. The aging test can shorten the early failure time of the components, can fully expose the failure mechanism of most components, leads the components to enter the accidental failure period in advance, and ensures the reliability of the components in use.
When a traditional aging board in an aging test mode is used for aging seven types of devices, namely ADuM150, ADuM151, ADuM152 and ADuM16X, ADuM160, ADuM161, ADuM162 and ADuM163, seven aging boards are needed to realize aging tests, the price is high, resources are wasted, the aging boards are not convenient to arrange and store, and the large-batch aging tests of the ADuM15X series and the ADuM16X series are not convenient to realize at one time.
Disclosure of Invention
The utility model aims at providing an integrated circuit chip's burn-in board.
The utility model discloses a following technical scheme realizes above-mentioned purpose: the aging board of the integrated circuit chip comprises a chip, wherein eight pins respectively extend out of the left side and the right side of the chip, the left eight pins are a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin from top to bottom, the right eight pins are a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin, a fourteenth pin, a fifteenth pin and a sixteenth pin from bottom to top, the first pin is connected with a first direct current stabilized voltage power supply and then connected with one end of a first input capacitor, the other end of the first input capacitor is grounded, the sixteenth pin is connected with a second direct current stabilized voltage power supply and then connected with one end of a second input capacitor, the other end of the input capacitor is grounded, the eighth pin and the ninth pin are grounded, the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin and the eighth pin, The seventh pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the fourteenth pin and the fifteenth pin are respectively connected with one end of an input/output resistor, and the other end of the input/output resistor is connected with a digital signal input.
Furthermore, the resistance values of the input/output resistors are all 10K omega.
Further, the capacitance values of the first input capacitor and the second input capacitor are both 0.1 muF.
Further, the voltage of the first direct current stabilized power supply and the voltage of the second direct current stabilized power supply are 5V.
Compared with the prior art, the utility model discloses integrated circuit chip's ageing board's beneficial effect is: the aging test of seven types of devices can be completed by using an aging plate, so that the hardware cost of the aging test is reduced, and the aging test is convenient to store and arrange.
Drawings
Fig. 1 is a schematic structural diagram of the present invention.
Fig. 2 is a schematic diagram of a structure of a chip of the ADuM150 model.
Fig. 3 is a schematic diagram of a chip structure of the ADuM160 model.
Detailed Description
Referring to fig. 1, an aging board for an integrated circuit chip includes a chip 1, eight pins respectively extend from the left and right sides of the chip 1, the eight pins on the left side are a first pin J1, a second pin J2, a third pin J3, a fourth pin J4, a fifth pin J5, a sixth pin J6, a seventh pin J7, and an eighth pin J8 from top to bottom, and the eight pins on the right side are a ninth pin J9, a tenth pin J10, an eleventh pin J11, a twelfth pin J12, a thirteenth pin J13, a fourteenth pin J14, a fifteenth pin J15, and a sixteenth pin J16 from bottom to top.
The first pin J1 is connected to the first dc regulated power supply 3 and then to one end of the first input capacitor 29, and the other end of the first input capacitor 29 is grounded.
The sixteenth pin J16 is connected to the second dc regulated power supply 2 and then to one end of the second input capacitor 30, and the other end of the input capacitor 30 is grounded.
The second pin J2 is connected to one end of the first input/output resistor 17, and the other end of the first input/output resistor 17 is connected to the first digital signal input 5.
The third pin J3 is connected to one end of the second input/output resistor 18, and the other end of the second input/output resistor 18 is connected to the second digital signal input 6.
The fourth pin J4 is connected to one end of the third input/output resistor 19, and the other end of the third input/output resistor 19 is connected to the third digital signal input 7.
The fifth pin J5 is connected to one end of the fourth input/output resistor 20, and the other end of the fourth input/output resistor 20 is connected to the fourth digital signal input 8.
The sixth pin J6 is connected to one end of the fifth input/output resistor 21, and the other end of the fifth input/output resistor 21 is connected to the fifth digital signal input 9.
The seventh pin J7 is connected to one end of the sixth input/output resistor 22, and the other end of the sixth input/output resistor 22 is connected to the sixth digital signal input 10.
The tenth pin J10 is connected to one end of the seventh input/output resistor 28, and the other end of the seventh input/output resistor 28 is connected to the seventh digital signal input 16.
The eleventh pin J11 is connected to one end of the eighth input/output resistor 27, and the other end of the eighth input/output resistor 27 is connected to the eighth digital signal input 15.
The twelfth pin J12 is connected to one end of the ninth input/output resistor 26, and the other end of the ninth input/output resistor 26 is connected to the ninth digital signal input 14.
The thirteenth pin J13 is connected to one end of the tenth input/output resistor 25, and the other end of the tenth input/output resistor 25 is connected to the tenth digital signal input 13.
The fourteenth pin J14 is connected to one end of the eleventh input/output resistor 24, and the other end of the eleventh input/output resistor 24 is connected to the eleventh digital signal input 12.
The fifteenth pin J15 is connected to one end of the twelfth input/output resistor 23, and the other end of the twelfth input/output resistor 23 is connected to the twelfth digital signal input 11.
The eighth pin J8 and the ninth pin J9 are grounded.
The resistance values of all the input/output resistors are 10K omega, the capacitance values of the first input capacitor 29 and the second input capacitor 30 are 0.1 muF, and the voltage of the first direct current stabilized power supply 3 and the voltage of the second direct current stabilized power supply 2 are 5V. The DC stabilized voltage power supply and the digital signal input are provided by an external integrated circuit high-temperature dynamic aging system. The integrated circuit high-temperature dynamic aging system is used for a semiconductor component aging experiment, is suitable for high-temperature dynamic aging experiments of various digital, analog and digital-analog hybrid integrated circuits and microelectronic circuits such as SOC circuits, microprocessors, memories and the like, and can provide environments required by direct-current stabilized voltage power supplies, 64-path digital signals, 4-path analog signals and aging experiments for the semiconductor component aging experiment.
The working principle of the present invention is illustrated by two embodiments.
Example 1
Referring to fig. 2, when the burn-in board is used to perform a burn-in test for a chip of the ADuM150 model, after the pin definition of the device is verified, after the burn-in condition of the device is programmed, a program is programmed to apply a correct voltage, according to the pin definition, a square wave digital signal is applied to the VI input pins of the corresponding chip 1, i.e., the first digital signal input 5, the second digital signal input 6, the third digital signal input 7, the fourth digital signal input 8, and the fifth digital signal input 9 of the second pin J2, the third pin J3, the fourth pin J4, the fifth pin J5, and the sixth pin J6, and the VO output pins of the corresponding chip 1, i.e., the eleventh pin J11, the twelfth pin J12, the thirteenth pin J13, the fourteenth pin J14, and the fifteenth pin J15, the eighth digital signal input 15, the ninth digital signal input 14, the tenth digital signal input 13, and the eleventh digital signal input 12, The twelfth digital signal input 11 may be a low level signal. The NIC pins have no internal connections so the connection status is not a matter of care.
Example 2
Referring to fig. 3, when the burn-in board is used to perform a burn-in test for a chip of an ADuM160 model, after verifying the pin definition of the device, after programming a corresponding program to apply a correct voltage to the burn-in board, according to the pin definition, the VI input pins of the corresponding chip 1, i.e., the second pin J2, the third pin J3, the fourth pin J4, the fifth pin J5, the sixth pin J6, and the seventh pin J7, input the first digital signal input 5, the second digital signal input 6, the third digital signal input 7, the fourth digital signal input 8, the fifth digital signal input 9, and the sixth digital signal input 10 into the square wave digital signal, and the VO output pins of the corresponding chip 1, i.e., the tenth pin J10, the eleventh pin J11, the twelfth pin J12, the thirteenth pin J13, the fourteenth pin J14, and the seventh digital signal input 16 of the fifteenth pin J15, input, The eighth digital signal input 15, the ninth digital signal input 14, the tenth digital signal input 13, the eleventh digital signal input 12, and the twelfth digital signal input 11 may be supplied with a low level signal.
The utility model discloses a SOP 16's anchor clamps can match the encapsulation and be SOP 16's chip, ADuM150, ADuM151, ADuM152, ADuM160, ADuM161, ADuM162, the burn-in of ADuM163 promptly, only need place the device of these SOP16 encapsulation in SOP 16's anchor clamps, send the program-controlled procedure of the integrated circuit high temperature dynamic ageing system of corresponding model can.
The utility model discloses a to except that the power and manage on other input and output pin are all received digital input, only need to adjust the experimental programme-controlled procedure of burn-in of integrated circuit high temperature dynamic aging system according to the pin definition of different devices and can accomplish for burn-in of seven model numbers of devices can be accomplished to a burn-in board, has reduced the experimental hardware cost of burn-in, is convenient for deposit and arranges in order.
The basic principles and the main features of the invention and the advantages of the invention have been shown and described above, it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, but that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (4)
1. A burn-in board for an integrated circuit chip, comprising: the chip comprises eight pins which extend out of the left side and the right side of the chip, wherein the eight pins on the left side sequentially comprise a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin from top to bottom, the eight pins on the right side sequentially comprise a ninth pin, a tenth pin, an eleventh pin, a twelfth pin, a thirteenth pin, a fourteenth pin, a fifteenth pin and a sixteenth pin from bottom to top, the first pin is connected with a first direct current stabilized voltage power supply and then connected with one end of a first input capacitor, the other end of the first input capacitor is grounded, the sixteenth pin is connected with a second direct current stabilized voltage power supply and then connected with one end of a second input capacitor, the other end of the input capacitor is grounded, the eighth pin and the ninth pin are grounded, the second pin, the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, the tenth pin and the eleventh pin are connected with one end of the eighth pin, The twelfth pin, the thirteenth pin, the fourteenth pin and the fifteenth pin are respectively connected with one end of an input/output resistor, and the other end of the input/output resistor is connected with a digital signal input.
2. The integrated circuit chip burn-in board of claim 1, wherein: and the resistance values of the input/output resistors are all 10K omega.
3. The integrated circuit chip burn-in board of claim 1, wherein: the capacitance values of the first input capacitor and the second input capacitor are both 0.1 muF.
4. The integrated circuit chip burn-in board of claim 1, wherein: and the voltage of the first direct current stabilized power supply and the second direct current stabilized power supply is 5V.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202221576635.2U CN217085191U (en) | 2022-06-23 | 2022-06-23 | Aging board for integrated circuit chip |
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| CN202221576635.2U CN217085191U (en) | 2022-06-23 | 2022-06-23 | Aging board for integrated circuit chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117233516A (en) * | 2023-11-13 | 2023-12-15 | 朗思传感科技(深圳)有限公司 | Pin detection method and pin detection device |
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- 2022-06-23 CN CN202221576635.2U patent/CN217085191U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117233516A (en) * | 2023-11-13 | 2023-12-15 | 朗思传感科技(深圳)有限公司 | Pin detection method and pin detection device |
| CN117233516B (en) * | 2023-11-13 | 2024-03-01 | 朗思传感科技(深圳)有限公司 | Pin detection method and pin detection device |
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