CN217063681U - High-precision clock generation circuit with digital temperature compensation - Google Patents

Abstract

The utility model discloses a take digital temperature compensation's high accuracy clock to produce circuit, including voltage reference circuit, analog-to-digital conversion circuit, memory, negative temperature sensor and the crystal oscillator of electrified capacitance network, voltage reference circuit respectively with negative temperature sensor with analog-to-digital conversion circuit electric connection and negative temperature sensor's output with analog-to-digital conversion circuit's input electric connection, analog-to-digital conversion circuit's output with the input electric connection of memory and the output of memory with the crystal oscillator's of electrified capacitance network input electric connection, electrified capacitance network's crystal oscillator still with analog-to-digital conversion circuit electric connection. The utility model discloses a take digital temperature compensation's high accuracy clock to produce circuit, it is used for solving the problem that the temperature floats.

Description

High-precision clock generation circuit with digital temperature compensation

Technical Field

The utility model belongs to clock generation circuit, concretely relates to take digital temperature compensation's high accuracy clock generation circuit.

Background

The characteristics of a semiconductor device usually have a certain temperature coefficient, and its output signal "drifts" with the change of temperature. The drift can affect whether the system in which the semiconductor device is located can work normally, and the purpose of the temperature compensation circuit is to eliminate the drift and stabilize the working characteristics of the semiconductor device.

Temperature compensation circuits have a wide range of requirements in the fields of medical electronics and fiber optic communications. In precision electronic equipment and measuring instruments, in order to overcome the influence of environmental temperature change on the work of the electronic equipment or improve the precision grade of the instruments and meters, a temperature sensitive circuit needs to be subjected to temperature compensation design. In optical fiber communications, whether a semiconductor laser in an optical transmitter can operate stably directly affects the efficiency of the communication system, and therefore, a temperature compensation circuit is also required to eliminate the "drift" of the laser caused by temperature changes.

SUMMERY OF THE UTILITY MODEL

A primary object of the present invention is to provide a high-precision clock generating circuit with digital temperature compensation, which is used to solve the temperature drift problem.

In order to achieve the above object, the utility model provides a take digital temperature compensation's high accuracy clock to produce circuit, including voltage reference circuit, analog-to-digital conversion circuit, memory, negative temperature sensor and the crystal oscillator who takes the capacitance network, wherein:

the voltage reference circuit is respectively electrically connected with the negative temperature sensor and the analog-to-digital conversion circuit, the output end of the negative temperature sensor is electrically connected with the input end of the analog-to-digital conversion circuit, the output end of the analog-to-digital conversion circuit is electrically connected with the input end of the memory, the output end of the memory is electrically connected with the input end of the crystal oscillator with the capacitor network, and the crystal oscillator with the capacitor network is also electrically connected with the analog-to-digital conversion circuit.

As a further preferable technical solution of the above technical solution, the voltage reference circuit includes an operational amplifier U1, an operational amplifier U2, and an operational amplifier U3, wherein:

the negative electrode input end of the operational amplifier U1 is grounded through a resistor R13 and a triode Q2, a resistor R12 is connected between the negative electrode input end and the output end of the operational amplifier U1, the positive electrode input end of the operational amplifier U1 is grounded through the triode Q1, a resistor R11 is connected between the positive electrode input end and the output end of the operational amplifier U1, and the output end of the operational amplifier U1 is grounded through a resistor R14, a resistor R15, a resistor R16 and a resistor R17 in sequence;

a common terminal (serving as VDAC) of the resistor R15 and the resistor R16 is electrically connected to a positive input terminal of the operational amplifier U2 and a positive input terminal of the operational amplifier U3, respectively, an output terminal of the operational amplifier U2 outputs a reference voltage VRH, and an output terminal of the operational amplifier U3 outputs a reference voltage VRL;

the output end of the negative temperature sensor outputs a temperature voltage Vin.

As a further preferable technical solution of the above technical solution, the analog-to-digital conversion circuit includes a resistor switch circuit and a capacitor switch circuit, the capacitor switch circuit includes a capacitor C1, one path of a negative electrode of the capacitor C1 is connected to a temperature voltage Vin through a switch Sin, and the other path of the negative electrode of the capacitor C1 is electrically connected to the resistor switch circuit through a switch # Sin.

As a further preferable technical solution of the above technical solution, the capacitance switching circuit further includes a capacitance C2, a capacitance C3, a capacitance C4, a capacitance C5, and a capacitance C6, wherein:

one path of the negative electrode of the capacitor C2 is connected with a reference voltage VRH through a switch SC1, and the other path of the negative electrode of the capacitor C2 is connected with a reference voltage VRL through a switch # SC1 and a switch # Sin 1;

one path of the negative electrode of the capacitor C3 is connected with a reference voltage VRH through a switch SC2, and the other path of the negative electrode of the capacitor C3 is connected with a reference voltage VRL through a switch # SC2 and a switch # Sin 1;

one path of the negative electrode of the capacitor C4 is connected with a reference voltage VRH through a switch SC3, and the other path of the negative electrode of the capacitor C4 is connected with a reference voltage VRL through a switch # SC3 and a switch # Sin 1;

one path of the negative electrode of the capacitor C5 is connected with a reference voltage VRH through a switch SC4, and the other path of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC4 and a switch # Sin 1;

one way of the negative electrode of the capacitor C6 is connected with a reference voltage VRH through a switch SC5, and the other way of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC5 and a switch # Sin 1.

As a further preferable technical solution of the above technical solution, the resistance switch circuit includes a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R4, a resistor R5, a resistor R6, and a resistor R7 connected between the reference voltage VRL and the reference voltage VRH, wherein:

the common end of the resistor R0 and the resistor R1 is electrically connected with the capacitor C1 through a switch SR0 and a switch # Sin;

the joint end of the resistor R1 and the resistor R2 is electrically connected with the capacitor C1 through a switch SR1 and a switch # Sin;

the common end of the resistor R2 and the resistor R3 is electrically connected with the capacitor C1 through a switch SR2 and a switch # Sin;

the common end of the resistor R3 and the resistor R4 is electrically connected with the capacitor C1 through a switch SR3 and a switch # Sin;

the joint end of the resistor R4 and the resistor R5 is electrically connected with the capacitor C1 through a switch SR4 and a switch # Sin;

the joint end of the resistor R5 and the resistor R6 is electrically connected with the capacitor C1 through a switch SR5 and a switch # Sin;

the joint end of the resistor R6 and the resistor R7 is electrically connected with the capacitor C1 through a switch SR6 and a switch # Sin;

the common end of the resistor R7 and the reference voltage VRH is electrically connected with the capacitor C1 through a switch SR7 and a switch # Sin.

As a further preferable technical solution of the above technical solution, the high-precision clock generating circuit with digital temperature compensation further includes a low voltage detection circuit, and the low voltage detection circuit is electrically connected to the voltage reference circuit.

Drawings

Fig. 1 is a schematic diagram of a high-precision clock generation circuit with digital temperature compensation according to the present invention.

Fig. 2 is a voltage reference circuit diagram of a high-precision clock generating circuit with digital temperature compensation according to the present invention.

Fig. 3 is an analog-to-digital conversion circuit diagram of the high-precision clock generation circuit with digital temperature compensation of the present invention.

Fig. 4 is a circuit diagram of a memory and a crystal oscillator of a high-precision clock generation circuit with digital temperature compensation according to the present invention.

Detailed Description

The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents and other technical solutions without departing from the spirit and scope of the invention.

The utility model discloses a take digital temperature compensation's high accuracy clock to produce circuit combines preferred embodiment below, further describes utility model's concrete embodiment.

In the embodiments of the present invention, those skilled in the art will note that the negative temperature sensor and the resistor, etc. of the present invention can be regarded as the prior art.

Preferred embodiments.

The utility model discloses a take digital temperature compensation's high accuracy clock to produce circuit, including voltage reference circuit, analog-to-digital conversion circuit, memory, negative temperature sensor and the crystal oscillator of taking the capacitance network, wherein:

the voltage reference circuit is respectively electrically connected with the negative temperature sensor and the analog-to-digital conversion circuit, the output end of the negative temperature sensor is electrically connected with the input end of the analog-to-digital conversion circuit, the output end of the analog-to-digital conversion circuit is electrically connected with the input end of the memory, the output end of the memory is electrically connected with the input end of the crystal oscillator with the capacitor network, and the crystal oscillator with the capacitor network is also electrically connected with the analog-to-digital conversion circuit.

Specifically, the voltage reference circuit comprises an operational amplifier U1, an operational amplifier U2, and an operational amplifier U3, wherein:

the negative electrode input end of the operational amplifier U1 is grounded through a resistor R13 and a triode Q2, a resistor R12 is connected between the negative electrode input end and the output end of the operational amplifier U1, the positive electrode input end of the operational amplifier U1 is grounded through the triode Q1, a resistor R11 is connected between the positive electrode input end and the output end of the operational amplifier U1, and the output end of the operational amplifier U1 is grounded through a resistor R14, a resistor R15, a resistor R16 and a resistor R17 in sequence;

a common terminal (as VDAC) of the resistor R15 and the resistor R16 is electrically connected to a positive input terminal of the operational amplifier U2 and a positive input terminal of the operational amplifier U3, respectively, an output terminal of the operational amplifier U2 outputs a reference voltage VRH, and an output terminal of the operational amplifier U3 outputs a reference voltage VRL;

the output end of the negative temperature sensor outputs a temperature voltage Vin.

More specifically, the analog-to-digital conversion circuit comprises a resistance switch circuit and a capacitor switch circuit, the capacitor switch circuit comprises a capacitor C1, one path of the negative electrode of the capacitor C1 is connected with a temperature voltage Vin through a switch Sin, and the other path of the negative electrode of the capacitor C1 is electrically connected with the resistance switch circuit through a switch # Sin.

Further, the capacitance switch circuit further includes a capacitance C2, a capacitance C3, a capacitance C4, a capacitance C5, and a capacitance C6, wherein:

one path of the negative electrode of the capacitor C2 is connected with a reference voltage VRH through a switch SC1, and the other path of the negative electrode of the capacitor C2 is connected with a reference voltage VRL through a switch # SC1 and a switch # Sin 1;

one path of the negative electrode of the capacitor C3 is connected with a reference voltage VRH through a switch SC2, and the other path of the negative electrode of the capacitor C3 is connected with a reference voltage VRL through a switch # SC2 and a switch # Sin 1;

one path of the negative electrode of the capacitor C4 is connected with a reference voltage VRH through a switch SC3, and the other path of the negative electrode of the capacitor C4 is connected with a reference voltage VRL through a switch # SC3 and a switch # Sin 1;

one path of the negative electrode of the capacitor C5 is connected with a reference voltage VRH through a switch SC4, and the other path of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC4 and a switch # Sin 1;

one way of the negative electrode of the capacitor C6 is connected with a reference voltage VRH through a switch SC5, and the other way of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC5 and a switch # Sin 1.

Further, the resistance switch circuit includes a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R4, a resistor R5, a resistor R6, and a resistor R7 (the number of resistors connected in series is determined by requirements), which are connected between the reference voltage VRL and the reference voltage VRH, wherein:

the joint end of the resistor R0 and the resistor R1 is electrically connected with the capacitor C1 through a switch SR0 and a switch # Sin;

the joint end of the resistor R1 and the resistor R2 is electrically connected with the capacitor C1 through a switch SR1 and a switch # Sin;

the joint end of the resistor R2 and the resistor R3 is electrically connected with the capacitor C1 through a switch SR2 and a switch # Sin;

the joint end of the resistor R3 and the resistor R4 is electrically connected with the capacitor C1 through a switch SR3 and a switch # Sin;

the common end of the resistor R4 and the resistor R5 is electrically connected with the capacitor C1 through a switch SR4 and a switch # Sin;

the joint end of the resistor R5 and the resistor R6 is electrically connected with the capacitor C1 through a switch SR5 and a switch # Sin;

the common end of the resistor R6 and the resistor R7 is electrically connected with the capacitor C1 through a switch SR6 and a switch # Sin;

the common end of the resistor R7 and the reference voltage VRH is electrically connected with the capacitor C1 through a switch SR7 and a switch # Sin.

Specifically, the high-precision clock generation circuit with digital temperature compensation further comprises a low-voltage detection circuit, and the low-voltage detection circuit is electrically connected with the voltage reference circuit.

Preferably, the principle of the utility model is that:

a high-precision clock generation mode with digital temperature compensation is provided, and comprises a voltage reference circuit, a low-voltage detection circuit, a negative temperature sensor, an ADC (analog-to-digital conversion circuit), an EEPROM (memory) and a crystal oscillator with a capacitance network, as shown in FIG. 1.

The illustrated negative temperature sensor can detect ambient temperature and at any temperature point, there is a corresponding voltage correspondence. According to the curve of the negative temperature sensor in the whole chip working temperature range, 2 extreme temperature voltages can be obtained, constant voltages VRL and VRH which are independent of temperature can be obtained through a voltage reference circuit, and therefore any voltage between VRL and VRH is independent of temperature. The ADC utilizes the 2 voltages as reference voltages, and after a current voltage value obtained by the negative temperature sensing curve enters the ADC, a current temperature value can be detected through approximation comparison, and the temperature value is recorded by the ADC through a group of binary numbers with 8 bits, namely 256 temperature points can be recorded.

In addition to frequency errors caused by different parasitics, the frequency of the crystal oscillator also deviates at each temperature, therefore, in order to obtain a high-precision clock, the frequency must be adjusted back by adjusting the capacitor, and the speed is better as soon as possible, in order to facilitate the fast adjustment of the capacitor network, each temperature point corresponds to the switch address of the 11-bit capacitor, that is, a 256 × 11 address table, after the test, a complete temperature-capacitor mapping table can be obtained through the relationship between the frequency and the capacitor, after the EPPROM memory mapping table is obtained, as long as the environmental temperature changes, the sensor can quickly maintain the constant of the clock by searching the address and changing the capacitance value after obtaining the temperature, the clock of the crystal oscillator also serves as the sampling clock of the ADC, the whole process only needs 8 clock cycles, that is, about 320us, and can be completed, the clock frequency can be kept constant even in a scene where the ambient temperature frequently changes.

The low voltage detection circuit is provided to prevent the power supply voltage from being too low and thus the correct temperature cannot be obtained.

In a specific implementation, fig. 2 is a voltage reference (generation) circuit, where VRH and VRL are both generated by VDAC through proportional operation, and the set voltage value is associated with the negative temperature sensor. Fig. 3 is divided into an ADC, and the input Vin of the ntc sensor is read out to be converted into a digital temperature by SAR Logic (successive approximation register), and then the value of the capacitive switch set by the EPPROM after the test is read out, so as to adjust the frequency.

The novel point of the circuit is that the VREF voltage reference circuit and the ADC circuit are integrated. A string of resistors (a resistor switch circuit) in the ADC is used as a load of the operational amplifier and a voltage scaling DAC of the ADC, a driving end of the operational amplifier can quickly pull up VRH and VRL to a specified voltage, and meanwhile, current flowing through the string of resistors is small, power consumption is extremely low, so that when the whole circuit meets a certain speed requirement, the power consumption can be extremely low.

The approximation principle in the ADC is as follows:

all switches, S and # S, are inverse signals to each other, and "1" represents on;

the high-order 5 bits (5MSB) are charge scaling sub-DACs, the precision of the ADC is guaranteed, the capacitor C1 on the leftmost side is a reference capacitor, one end of the capacitor C1 is connected with a compression amplifier sub-DAC (resistance switch circuit), the other end of the capacitor C1 is connected with an input voltage Vin, the capacitor C2-C6 on the right side is a two-level system weighting capacitor, one end of the capacitor C2-C6 is connected with a high voltage VRH, and the other end of the capacitor C2-C6 is connected with a voltage VRL.

The lower 3 bits (3LSB) are voltage scaling sub-DACs (successive approximation register U1) with better monotonicity. After the MSB approaches, the purpose of changing the approaching voltage is achieved by changing the value of one end of the reference capacitor.

The utility model discloses a VRH and VRL come from the reference voltage, are fit for some specific voltage range's application. Because of the large resistor string, the current consumed is very small, about 10uA for speed reasons.

INV1 is a special-sized inverter, and is used as a comparator, the comparison voltage is a dc voltage with equal input and output, after comparison, the voltage amplitude is still not large enough, so it is input into INV2 after capacitance coupling, INV2 is also used as a comparator, the voltage after INV2 can be shaped by normal inverter INV3, and then output to the Logic circuit (SAR Logic) of SAR. When the comparator is reset, the comparator works in a direct current state, the current consumption is the largest at the moment and is about 100uA, but because of a dynamic structure, the average current is far less than 100uA

The working principle of successive approximation is described as follows:

the first stage is as follows: reset, RST is 1, Sin is 0, the voltages of all the capacitor upper plates are reset voltages Vcm, and the lower plate voltage is VRH (for the reference capacitor, since Sin is 0 and SR7 is 1, Vmux is VRH).

In the second stage, the voltages of the upper plates of all capacitors are still the reset voltage Vcm and the voltage of the lower plate is Vin, so that the sampled charges are equal to 1 and Sin is 1

Qsample＝32C(Vin-Vcm)；

In the third stage, RST is 0, Sin is 0, the upper plates of all capacitors are suspended, the voltage of the lower plate is still connected with Vin, leakage is neglected, and the charge is kept unchanged

Qhold＝32C*(Vin-Vcm)；

The fourth stage, the approximation operation, first of all, the highest position 0 (this is designed as guess 0), i.e. SC5 is equal to 0, and according to the conservation of charge, the formula can be listed

Qmsb＝(VRH-Vx)16C+(VRL-Vx)16C；

Obtaining Vx ═ VRL + (VRH-VRL)/2- (Vin-Vcm), and comparing the value with Vcm to obtain the output of the comparator;

the value of Vx can also be calculated by the following equation, M being the capacitance level and K being the resistance level.

By analogy, the value of Vin (output at inverter INV 3) can be obtained by gradual approximation.

It should be mentioned that the technical features such as the negative temperature sensor and the resistor related to the present invention should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of these technical features may be regarded as the conventional selection in the field, and should not be regarded as the invention point of the present invention, and the present invention does not further expand the detailed description.

It will be appreciated by those skilled in the art that changes may be made in the embodiments described above, or equivalents may be substituted for some of the features thereof.

Claims (6)

1. A high-precision clock generation circuit with digital temperature compensation is characterized by comprising a voltage reference circuit, an analog-to-digital conversion circuit, a memory, a negative temperature sensor and a crystal oscillator with a capacitance network, wherein:

the voltage reference circuit is respectively electrically connected with the negative temperature sensor and the analog-to-digital conversion circuit, the output end of the negative temperature sensor is electrically connected with the input end of the analog-to-digital conversion circuit, the output end of the analog-to-digital conversion circuit is electrically connected with the input end of the memory, the output end of the memory is electrically connected with the input end of the crystal oscillator with the capacitance network, and the crystal oscillator with the capacitance network is further electrically connected with the analog-to-digital conversion circuit.

2. The high-precision clock generation circuit with digital temperature compensation of claim 1, wherein the voltage reference circuit comprises an operational amplifier U1, an operational amplifier U2 and an operational amplifier U3, wherein:

the negative electrode input end of the operational amplifier U1 is grounded through a resistor R13 and a triode Q2, a resistor R12 is connected between the negative electrode input end and the output end of the operational amplifier U1, the positive electrode input end of the operational amplifier U1 is grounded through the triode Q1, a resistor R11 is connected between the positive electrode input end and the output end of the operational amplifier U1, and the output end of the operational amplifier U1 is grounded through a resistor R14, a resistor R15, a resistor R16 and a resistor R17 in sequence;

the common terminal of the resistor R15 and the resistor R16 is electrically connected to the positive input terminal of the operational amplifier U2 and the positive input terminal of the operational amplifier U3, respectively, the output terminal of the operational amplifier U2 outputs a reference voltage VRH and the output terminal of the operational amplifier U3 outputs a reference voltage VRL;

the output end of the negative temperature sensor outputs a temperature voltage Vin.

3. The high-precision clock generation circuit with digital temperature compensation of claim 2, wherein the analog-to-digital conversion circuit comprises a resistance switch circuit and a capacitance switch circuit, the capacitance switch circuit comprises a capacitor C1, one path of the negative pole of the capacitor C1 is connected with a temperature voltage Vin through a switch Sin, and the other path of the negative pole of the capacitor C1 is electrically connected with the resistance switch circuit through a switch # Sin.

4. A high accuracy clock generation circuit with digital temperature compensation as claimed in claim 3 wherein the capacitance switch circuit further comprises capacitance C2, capacitance C3, capacitance C4, capacitance C5 and capacitance C6, wherein:

one path of the negative electrode of the capacitor C2 is connected with a reference voltage VRH through a switch SC1, and the other path of the negative electrode of the capacitor C2 is connected with a reference voltage VRL through a switch # SC1 and a switch # Sin 1;

one path of the negative electrode of the capacitor C3 is connected with a reference voltage VRH through a switch SC2, and the other path of the negative electrode of the capacitor C3 is connected with a reference voltage VRL through a switch # SC2 and a switch # Sin 1;

one path of the negative electrode of the capacitor C4 is connected with a reference voltage VRH through a switch SC3, and the other path of the negative electrode of the capacitor C4 is connected with a reference voltage VRL through a switch # SC3 and a switch # Sin 1;

one path of the negative electrode of the capacitor C5 is connected with a reference voltage VRH through a switch SC4, and the other path of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC4 and a switch # Sin 1;

one path of the negative electrode of the capacitor C6 is connected with a reference voltage VRH through a switch SC5, and the other path of the negative electrode of the capacitor C5 is connected with a reference voltage VRL through a switch # SC5 and a switch # Sin 1.

5. The high-precision clock generation circuit with digital temperature compensation of claim 4, wherein the resistance switch circuit comprises a resistor R0, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R4, a resistor R5, a resistor R6 and a resistor R7 connected between the reference voltage VRL and the reference voltage VRH, wherein:

the common end of the resistor R0 and the resistor R1 is electrically connected with the capacitor C1 through a switch SR0 and a switch # Sin;

the common end of the resistor R1 and the resistor R2 is electrically connected with the capacitor C1 through a switch SR1 and a switch # Sin;

the common end of the resistor R2 and the resistor R3 is electrically connected with the capacitor C1 through a switch SR2 and a switch # Sin;

the joint end of the resistor R3 and the resistor R4 is electrically connected with the capacitor C1 through a switch SR3 and a switch # Sin;

the joint end of the resistor R4 and the resistor R5 is electrically connected with the capacitor C1 through a switch SR4 and a switch # Sin;

the joint end of the resistor R5 and the resistor R6 is electrically connected with the capacitor C1 through a switch SR5 and a switch # Sin;

the joint end of the resistor R6 and the resistor R7 is electrically connected with the capacitor C1 through a switch SR6 and a switch # Sin;

the common end of the resistor R7 and the reference voltage VRH is electrically connected with the capacitor C1 through a switch SR7 and a switch # Sin.

6. The circuit of claim 5, further comprising a low voltage detection circuit electrically connected to the voltage reference circuit.

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