CN104267244A - Integral proportion circuit and impedance measurement method based on integral proportion circuit - Google Patents

Abstract

The invention provides an integral proportion circuit and an impedance measurement method based on the integral proportion circuit. Measuring of the proportion of DC components of two AC and DC voltage signals can be achieved, the impedance measuring is converted into the measuring of the voltage DC components, and the measuring precision of the impedance is greatly improved. The integral proportion circuit comprises an operation amplifier, an integral amplifier and a comparator. The positive input end of the operation amplifier is connected with the measured signals, the positive output end and the negative output end of a standard voltage source and a ground potential through four switches respectively, the output end of the operation amplifier is connected with the negative input end and is connected with the negative input end of the integral amplifier through a current limiting resistor, and the output end of the integral amplifier is connected with the positive input end of the comparator. An integral capacitor is connected between the negative input end and the output end of the integral amplifier, charging switches are arranged at the two ends of the integral capacitor respectively, the positive input end of the integral amplifier is connected with the positive end reference voltage, and the negative input end of the comparator is connected with the negative end reference voltage.

Description

A kind of integration ratio circuit and the impedance measurement method based on integration ratio circuit

Technical field

The present invention relates to ac electric quantity measuring technical field, particularly relate to a kind of integration ratio circuit and the impedance measurement method based on integration ratio circuit.

Background technology

Impedance is that resistance in circuit, inductance, electric capacity are to the general designation of the inhibition of alternating current.The concept of resistance is extended to alternating circuit field by impedance, not only describes the relative amplitude of voltage and electric current, also describes its relative phase.When the electric current by circuit is direct current, resistance is equal with impedance, and resistance can be considered as the impedance that phase place is zero.Impedance is usually with symbols Z mark, and according to the active definition of impedance, impedance is plural number, and be complex number voltage and the ratio of power plural current, i.e. Z=U/I, also can with phasor Z _m< θ or Z _me ^{j θ}represent; Wherein, Z _mrepresent the size of impedance, be the absolute value ratio of voltage amplitude and current amplitude, θ represents the phase place of impedance, is the phase differential of voltage and electric current, and this tabular form method is called " phasor representation method ".

At present, the method for measurement impedance mainly contains bridge method, resonance method and vector impedance method, and bridge method basic functional principle is based on four arm electrical bridge circuit, but bridge method needs repeatedly to carry out balance adjustment, method of operating is loaded down with trivial details, time-consuming, and measurement range is limited, is difficult to realize fast automatic measurement; Resonance method is based on the resonance characteristic in LC loop, tested impedance is calculated by measuring resonance frequency and known inductance or C meter, vector impedance method is defined as basis with impedance, test signal voltage is added to measured piece, current test signal flows through measured piece, calculates test lead impedance by the ratio of voltage and current; But these measuring methods all require that pumping signal is the sine wave signal of low distortion, but the sine wave signal of the low distortion that frequency is higher is difficult to obtain, and which limits the raising of impedance measurement precision and the expansion of measurement range.

In recent years, along with the progress of science and technology, the method for measurement impedance to digitizing, intellectuality, programme-controlled levels, to improve measuring accuracy and the measurement range of impedance.The normal double integration circuit that uses is used for impedance measurement at present, and its ultimate principle is the measurement measurement of impedance parameter being converted to voltage.But the double integration circuit of current used measurement impedance mostly adopts the double integration circuit directly measuring DC voltage, measure four magnitudes of voltage respectively, then calculate, because four magnitude of voltage polarity are indefinite, have just have negative, be respectively its positive voltage source and negative voltage source surveyed, the initial voltage of positive voltage source, negative voltage source and integration is vulnerable to the impact of its long term drift and humiture change, and then affects the accuracy of measured value.

Summary of the invention

The invention provides a kind of integration ratio circuit and the impedance measurement method based on integration ratio circuit, the ratio measuring DC component can be realized, impedance measurement is converted to the ratio of measuring voltage DC component, greatly improves the measuring accuracy of impedance; Its integration ratio circuit can be widely used in the instrument that needs such as comprising impedance instrument, power analyzer, phase meter, phase angle table are tested two voltage magnitudes and phase relation.

Technical scheme of the present invention is:

1. an integration ratio circuit, for measuring the ratio of two combined-voltage signal DC component, is characterized in that, comprising operational amplifier, integrating amplifier, comparer; The positive input terminal of described operational amplifier connects measured signal, the positive-negative output end of standard voltage source and earth potential respectively by the first interrupteur SW 1, second switch SW2, the 3rd interrupteur SW 3, the 4th interrupteur SW 4, the output terminal of operational amplifier is connected with negative input end, and connected the negative input end of described integrating amplifier by integrating resistor R, the output terminal of described integrating amplifier connects the positive input terminal of described comparer; Connect integrating capacitor between the negative input end of described integrating amplifier and output terminal, the two ends of described integrating capacitor have charge switch SW0; The positive input terminal of described integrating amplifier connects forward end reference voltage U _rEF1, the negative input end of described comparer connects negative end reference voltage U _rEF2.

2. based on an impedance measurement method for above-mentioned integration ratio circuit, it is characterized in that, by measuring the in-phase component U of ac voltage signal under reference orthogonal coordinate system of tested impedance _1awith quadrature component U _1band the in-phase component U of the ac voltage signal of normal impedance under reference orthogonal coordinate system _2awith quadrature component U _2bbetween the ratio of DC component, impedance measurement is converted to the ratio of measuring voltage DC component, concrete steps are as follows:

Step 1), first determine the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2size;

Step 2), measure and draw the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2, integration initial voltage U _sbetween proportionate relationship;

Step 3), measure respectively and draw the in-phase component U of the ac voltage signal of tested impedance under reference orthogonal coordinate system _1a, quadrature component U _1b, normal impedance ac voltage signal with reference to the in-phase component U under orthogonal coordinate system _2a, quadrature component U _2bwith described forward end reference voltage U _rEF1, negative end reference voltage U _rEF2, the integration initial voltage U be carried on integrating resistor R _sbetween proportionate relationship;

Step 4), utilize step 2) with step 3) result that draws, by formula

$Z_1=\frac{\sqrt{U_{1a}^2+U_{1b}^2}}{\sqrt{U_{2a}^2+U_{2b}^2}}\left|Z_2\right|$

Calculate tested impedance.

3. step 1 described in) in, determine forward end reference voltage U _rEF1, with negative end reference voltage U _rEF2concrete steps as follows:

When earthy 4th interrupteur SW 4 of connection is in closed, when other switches disconnect, select U _rEF1making electric capacity C charging direction perseverance be forward or perseverance is negative sense, i.e. U _gND+ V _oS1-U _eperseverance be just or perseverance be negative; During charging:

U _e＝U _REF1+V _OS2+I _B2·R+I _SW0·R

V _oS1, V _oS2---the bias voltage of-operational amplifier and integrating amplifier;

I _b2---the bias current of-operational amplifier;

I _sW0----be divided into, interrupteur SW 0 was at closed situation and the leakage current under opening situation;

Equally, U is selected _rEF2make the positive and negative input voltage of comparer A3 under integrate-dump state difference permanent for just or perseverance be negative; I.e. U _rEF2-V _oS3-U _eperseverance be just or perseverance be negative, Vos ₃for the bias voltage of comparer.

4. step 2 described in) in, measuring process selects integration direction to be U _gND+ V _oS1-U _e>0, U _rEF2-V _oS3-U _e>0, comprises the following steps:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity C is with (U _rEF--U _sthe current charges of)/R<0, integrating amplifier output voltage U ₁rise to comparer reversion, this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW4 closes, and rest switch disconnects, and start timing after SW4 is closed, now electric capacity C is with (U _gND-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₁, this stage U ₁voltage reduces;

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₂, this stage terminates;

E) fourth stage, SW2 closes, and rest switch disconnects, and start timing after SW2 is closed, now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₃, this stage U ₁voltage reduces;

F) five-stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₄, this stage terminates;

Wherein: U _rEF+, U _rEF-be respectively the positive and negative terminal output voltage of standard voltage source.

5. step 2 described in) in, by t1, t2, t3, t4 of recording,

According to charge conservation, can be obtained by subordinate phase and phase III:

$\frac{U_{\mathrm{GND}}-U_s}{R}\&CenterDot;t_1+\frac{U_{\mathrm{REF}}-U_s}{R}\&CenterDot;t_2=0---\left(11\right)$

Get U _gND=0, can draw:

$\frac{U_s}{U_{\mathrm{REF}-}}=\frac{t_2}{t_1-t_2}---\left(12\right)$

According to charge conservation, can be obtained by fourth stage and five-stage:

$\frac{U_{\mathrm{REF}+}-U_s}{R}\&CenterDot;t_3+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_4=0---\left(13\right)$

Namely

$\frac{U_{\mathrm{REF}+}}{U_{\mathrm{REF}-}}=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(14\right)$

Order

U _REF+＝a·U _REF- (15)

In formula:

$a=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(16\right)$

Order

U _s＝b·U _REF- (17)

In formula:

$b=\frac{t_2}{t_1-t_2}.---\left(18\right)$

6. step 3 described in) in, work as U _in-U _sduring >0, whole integration is divided into four-stage:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage reduces; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle, now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₆, this stage terminates.

7. step 3 described in) in, according to t5, t6 of recording,

According to principle of charge conservation, can be obtained by subordinate phase and phase III

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_6=0$

Convolution (15), (16), (17), (18)

Can obtain:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-t_6}{t_5}---\left(18\right)$

Order

U _in＝c·U _REF- (19)

In formula:

$c=\frac{b(t_5+t_6)-t_6}{t_5}.---\left(20\right)$

8. step 3 described in) in, work as U _in-U _sduring <0, whole integration is divided into double teacher:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R<0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage rise; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle, now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW2 closes, and rest switch disconnects, and now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, U ₁voltage drop reverses to comparer, then continues a bit of time t of charging again ₀, total integral time is t ₆, this stage terminates;

E) fourth stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₇, this stage terminates.

9. step 3 described in) in, according to t5, t6, t7 of recording,

According to principle of charge conservation, can be obtained by subordinate phase, phase III and fourth stage

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_6+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_7=0$

Convolution (15), (16), (17), (18)

That is:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}---\left(21\right)$

Make U _in=cU _rEF-(22)

In formula:

$c=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}.---\left(23\right)$

Technique effect of the present invention:

1. the invention provides a kind of integration ratio circuit, for measuring the ratio of the DC component of two combined-voltage signals, based on charge balance concept, respectively discharge and recharge is carried out to integrating capacitor in different integration phase, and integral time is controlled, filtering AC compounent, realizes the ratio measuring DC component.Utilize repeatedly integration to eliminate the measuring error brought integrating circuit of leakage current of the offset voltage of operational amplifier, bias current, temperature drift and analog switch, improve measuring accuracy.

2. the invention provides a kind of impedance measurement method based on integration type circuit, the method uses integration ratio circuit, impedance measurement is converted to the ratio of measuring voltage DC component, thus realizes high-precision impedance measurement.What need to measure due to method of the present invention is proportionate relationship between four tested voltage, and it is insensitive to its absolute value, first the present invention measures positive voltage source, ratio between negative voltage source and integration initial voltage, then measure four tested voltages and positive voltage source again, ratio between negative voltage source and integration initial voltage, draw the ratio between four tested voltage, this process eliminate the impact of long term device drift on measurement result, and due to Measuring Time very short (at 1s or in the shorter time), can think that the external environment such as humiture at system place is substantially unchanged, so also eliminate external environment to the impact of measuring, improve the accuracy of measurement result.

3. the integration ratio circuit that the present invention relates to and can be widely used in the thermometrically of 100Hz ~ 1MHz electric capacity, inductance, resistance and any resistance based on the impedance measurement method of integration ratio circuit, its orthogonal demodulation method based on integration ratio circuit and circuit can be widely used in the instrument that needs such as comprising impedance instrument, power analyzer, phase meter, phase angle table are tested two voltage magnitudes and phase relation.Therefore, based on technical scheme provided by the present invention, above-mentioned multiple instrument can be researched and developed.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of integration ratio circuit of the present invention.

Fig. 2 is the measurement U of the inventive method _rEF1, U _rEF2, U _sbetween the integration sequence figure of proportionate relationship.

Fig. 3 is the measurement U of the inventive method _1a, U _1b, U _2a, U _2bwith U _rEF1, U _rEF2, U _sbetween one of the integration sequence figure (U of proportionate relationship _in-U _s>0).

Fig. 4 is the measurement U of the inventive method _1a, U _1b, U _2a, U _2bwith U _rEF1, U _rEF2, U _sbetween the integration sequence figure bis-(U of proportionate relationship _in-U _s<0).

Embodiment

Below in conjunction with accompanying drawing, embodiments of the invention are described further.

As shown in Figure 1, it is the circuit diagram of integration ratio circuit of the present invention, the ratio of the DC component of measurement two combined-voltage signals can be realized, the ratio also namely between in-phase component under reference frame of two ac voltage signals with flip-flop and the DC component of quadrature component.A kind of integration ratio circuit, comprises operational amplifier, integrating amplifier, comparer; The positive input terminal of operational amplifier connects measured signal, the positive-negative output end of standard voltage source and earth potential respectively by the first interrupteur SW 1, second switch SW2, the 3rd interrupteur SW 3, the 4th interrupteur SW 4, the output terminal of operational amplifier is connected with negative input end, and the negative input end of described integrating amplifier is connected by integrating resistor R, the output terminal of integrating amplifier connects the positive input terminal of described comparer, connect integrating capacitor between the negative input end of integrating amplifier and output terminal, the two ends of integrating capacitor have charge switch SW0; The positive input terminal of integrating amplifier connects forward end reference voltage U _rEF1, the negative input end of comparer connects negative end reference voltage U _rEF2.

Figure ₁in, U _rEF+, U _rEF-be respectively positive and negative standard voltage source; U _infor measured signal, i.e. U _infor U _1a, U _1b, U _2a, U _2bfour one of them, U _1abe the in-phase component of the first measured signal under reference orthogonal coordinate system, U _1bbe quadrature component, the U of the first measured signal under reference orthogonal coordinate system _2abe the in-phase component of the second measured signal under reference orthogonal coordinate system, U _2bbe the quadrature component of the second measured signal under reference orthogonal coordinate system; GND is earth potential; Operational amplifier A 1 is speed buffering amplifier; A2 is integrating amplifier; A3 is comparer; U _rEF1for A2 forward end reference voltage; U _rEF2for A3 negative end reference voltage.

A kind of impedance measurement method based on above-mentioned integration ratio circuit, by the ac voltage signal of measuring tested impedance at the ac voltage signal with reference to the in-phase component under orthogonal coordinate system and quadrature component and normal impedance in the ratio with reference to the DC component between the in-phase component under orthogonal coordinate system and quadrature component, impedance measurement is converted to the ratio of measuring voltage DC component.

According to the measuring principle of phasor Orthogonal Decomposition rule of three, make tested impedance and normal impedance by identical electric current, then to get in tested impedance voltage signal on voltage signal and normal impedance and carry out Treatment Analysis, obtain tested impedance information.

If in voltage signal and normal impedance, voltage signal is respectively u in tested impedance ₁and u ₂, can be expressed as with reference to the voltage phasor under orthogonal coordinate system:

${\stackrel{*}{U}}_1=U_{1a}+j{U}_{1b}---\left(1\right)$

${\stackrel{*}{U}}_2=U_{2a}+j{U}_{2b}---\left(2\right)$

Wherein, be respectively alternating voltage u ₁and u ₂voltage phasor under reference orthogonal coordinate system, U _1a, U _1balternating voltage u respectively ₁in-phase component under reference orthogonal coordinate system and quadrature component, U _2a, U _2balternating voltage and u respectively ₂in-phase component under reference orthogonal coordinate system and quadrature component.

Be multiplied with measured signal respectively with reference to the pair of orthogonal basis function on coordinate system, obtain measured signal homophase or quadrature component.If measured signal u ₁time-domain expression:

u ₁(t)＝Asin(ωt+θ) (3)

In formula, A is u ₁amplitude, ω is u ₁angular frequency, θ is u ₁initial phase.

The time-domain expression of the pair of orthogonal basis function of reference frame is:

u _a(t)＝sin(ωt) (4)

$u_b\left(t\right)=\sin (\mathrm{\&omega;t}+\frac{\mathrm{\&pi;}}{2})---\left(5\right)$

Orthogonal basis function is unit amplitude, angular frequency must and u ₁angular frequency identical, orthogonal basis function is multiplied with measured signal respectively:

$\begin{array}{c}{u}_{1a}\left(t\right)=u_a\left(t\right)\&CenterDot;u_1\left(t\right)\\ =\sin \left(\mathrm{\&omega;t}\right)\&CenterDot;A\sin (\mathrm{\&omega;t}+\mathrm{\&theta;})\\ =A\cos \mathrm{\&theta;}{\sin }^2\left(\mathrm{\&omega;t}\right)+A\sin \mathrm{\&theta;}\sin \left(\mathrm{\&omega;t}\right)\cos \left(\mathrm{\&omega;t}\right)\\ =\frac{A}{2}\cos \mathrm{\&theta;}+\frac{A}{2}\cos (2\mathrm{\&omega;t}-\mathrm{\&theta;})\end{array}$

Similarly to obtain use low-pass filter, by the item elimination of upper two formula band 2 ω t, obtain in-phase component that measured signal fastens at reference coordinate or quadrature component:

$U_{1a}=\frac{A}{2}\cos \mathrm{\&theta;}---\left(6\right)$

$U_{1b}=\frac{A}{2}\sin \mathrm{\&theta;}---\left(7\right)$

In like manner U can be drawn _2aand U _2b, tested impedance can be calculated:

$Z_1=\frac{\sqrt{U_{1a}^2+U_{1b}^2}}{\sqrt{U_{2a}^2+U_{2b}^2}}\left|Z_2\right|---\left(8\right)$

From above-mentioned principle, measurement impedance key measures in-phase component and quadrature component U _1a, U _1b, U _2a, U _2bbetween the ratio of DC component.

Concrete steps are as follows:

Step 1), first determine the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2size;

Step 2), measure and draw the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2, the integration initial voltage U be carried on integrating resistor R _sbetween proportionate relationship;

Step 3), measure respectively and draw the in-phase component U of the ac voltage signal of tested impedance under reference orthogonal coordinate system _1a, quadrature component U _1b, normal impedance ac voltage signal with reference to the in-phase component U under orthogonal coordinate system _2a, quadrature component U _2bwith described forward end reference voltage U _rEF1, negative end reference voltage U _rEF2, the integration initial voltage U be carried on integrating resistor R _sbetween proportionate relationship;

Step 4), utilize step 1) with step 2) result that draws, by formula

$Z_1=\frac{\sqrt{U_{1a}^2+U_{1b}^2}}{\sqrt{U_{2a}^2+U_{2b}^2}}\left|Z_2\right|$

Calculate tested impedance.

Usually, in basic integrating circuit, U _rEF1and U _rEF2earthing potential, this method Problems existing is as follows:

1, U _rEF1earthing potential: make when SW4 closes, when other switches disconnect, capacitor charging direction is just likely, is also likely negative, needs extra integral time and goes to determine its charging direction.

2, U _rEF2earthing potential: the output voltage resetting rear comparer A3 just can be born, make troubles to the selection of integral voltage.

Therefore, before integral measurement process starts, first reference voltage U will be carried out _rEF1with U _rEF2size determine, provide corresponding magnitude of voltage in advance, selected U _rEF1capacitor charging direction is determined, selected U when SW4 is closed _rEF2value is determined to reset rear A3 output voltage.The method specifically determined is as follows:

When considering system drifting, when SW4 closes, when other switches disconnect, select U _rEF1making electric capacity C charging direction perseverance be forward or perseverance is negative sense, i.e. U _gND+ V _oS1-U _eperseverance be just or perseverance be negative.During charging:

U _e＝U _REF1+V _OS2+I _B2·R+I _SW0·R (10)

V _oS1, V _oS2---the bias voltage of-operational amplifier 1 and operational amplifier 2;

I _b2---the bias current of-operational amplifier;

I _sW0----be divided into, switch was at closed situation and the leakage current under opening situation, because this electric current is less, and did not affect system index, did not distinguish it in formula.

Because this absolute value of voltage is larger, measuring speed is slower, and be therefore usually chosen as tens of mV to hundreds of mV comparatively appropriate, its absolute value is less than U simultaneously _rEF+and U _rEF-.

This voltage refers to U _gND+ V _oS1-U _eits multifactorial impact of value audient can be found out by formula, best its set to zero in theory, but due to long term drift and the environmental change of device, its value also has drift, and drift size affects by selected device and environmental change, if set to zero when dispatching from the factory, the value so affecting it by long term drift may be greater than zero, may be less than zero.The size of its drift is determined by the size of the change of the environmental factor such as drift and system temperature along with selected device, generally speaking, this drift between number mV to tens of mV, but is also likely greater or lesser value, but its formula is constant.At selection U _rEF1time, need to calculate U according to the environmental change of device handbook and work thereof _gND+ V _oS1-U _emaximum drift, guarantee U _gND+ V _oS1-U _epermanent in just or under the permanent prerequisite for bearing selecting U _rEF1, and make U _gND+ V _oS1-U _eabsolute value as far as possible little, and reserve corresponding allowance, because absolute value crosses conference reduce measuring speed.

Equally, U is selected _rEF2make the positive and negative input voltage of comparer A3 under integrate-dump state difference permanent for just or perseverance be negative; I.e. U _rEF2-V _oS3-U _eperseverance be just or perseverance be negative.This absolute value of voltage is larger, and measuring speed is slower, and be therefore usually chosen as tens of mV to hundreds of mV comparatively appropriate, its absolute value is less than U simultaneously _rEF+and U _rEF-.

In like manner, this voltage refers to U _rEF2-V _oS3-U _eits multifactorial impact of value audient can be found out by formula, best its set to zero in theory, but due to long term drift and the environmental change of device, its value also has drift, and drift size affects by selected device and environmental change, if set to zero when dispatching from the factory, the value so affecting it by long term drift may be greater than zero, may be less than zero.The size of its drift is determined by the size of the change of the environmental factor such as drift and system temperature along with selected device, generally speaking, this drift between number mV to tens of mV, but is also likely greater or lesser value, but its formula is constant.At selection U _rEF2time, need to calculate U according to the environmental change of device handbook and work thereof _rEF2-V _oS3-U _emaximum drift, guarantee U _rEF2-V _oS3-U _epermanent in just or under the permanent prerequisite for bearing selecting U _rEF2, and make U _rEF2-V _oS3-U _eabsolute value as far as possible little, and reserve corresponding allowance, because absolute value crosses conference reduce measuring speed.

Whole measuring process is divided into two steps, and the first step is for measuring U _rEF+, U _rEF-, U _sbetween proportionate relationship, second step is for measure U respectively _1a, U _1b, U _2a, U _2bwith U _rEF+, U _rEF-, U _sbetween proportionate relationship, then calculate can draw U _1a, U _1b, U _2a, U _2bbetween proportionate relationship.

According to U _rEF1and U _rEF2four kinds of situations can be there are in the difference selected:

U _GND+V _OS1-U _e>0，U _REF2-V _OS3-U _e>0；

U _GND+V _OS1-U _e>0，U _REF2-V _OS3-U _e<0；

U _GND+V _OS1-U _e<0，U _REF2-V _OS3-U _e>0；

U _GND+V _OS1-U _e<0，U _REF2-V _OS3-U _e<0；

These four kinds of situations are different unlike the integration direction selected in measuring process, but its ultimate principle is consistent, existing with U _gND+ V _oS1-U _e>0, U _rEF2-V _oS3-U _e>0 is that example illustrates integral process:

The first step: measure U _rEF+, U _rEF-, U _sbetween proportionate relationship

Note: U _s=U _e-V _oS1

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW4 closes, and rest switch disconnects, and now electric capacity is with (U _gND-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₁, this stage U ₁voltage reduces;

Select the method for integral time as follows:

Start timing after SW4 is closed, the selection of timing time is relevant with selected clock and required resolution, will reduce the impact of AC compounent simultaneously.The resolution of the count value decision systems of counter, if index is 10 ^-4, so count value will be reached for more than ten times of index resolution, as 10 ⁵~ 10 ⁶, time=clock period × count value, in order to prevent the leakage of integrating condenser self, using the polytetrafluoroethylene capacitor that Leakage Current is little on the one hand, being no more than 0.1s integral time on the other hand.Simultaneously integral time should be measured signal cycle/2 integral multiple (because system frequency can be established, being known conditions), to eliminate measured signal AC compounent to the impact of measuring, reach the object of filtering AC compounent.

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₂, this stage terminates;

E) fourth stage, SW2 closes, and rest switch disconnects, and now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₃, this stage U ₁voltage reduces;

Timing is started, the resolution of the count value decision systems of counter, if index is 10 after SW2 is closed ^-4, so count value will be reached for more than ten times of index resolution, as 10 ⁵~ 10 ⁶, time=clock period × count value, in order to prevent the leakage of integrating condenser self, using the polytetrafluoroethylene capacitor that Leakage Current is little on the one hand, being no more than 0.1s integral time on the other hand.Simultaneously integral time should be measured signal cycle/2 integral multiple (because system frequency can be established, being known conditions);

F) five-stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₄, this stage terminates.

Note: to the charging direction of the positive and negative decision electric capacity of the electric current of capacitor charging, U during negative current charging ₁increase, otherwise reduce.

According to charge conservation, can be obtained by subordinate phase and phase III:

$\frac{U_{\mathrm{GND}}-U_s}{R}\&CenterDot;t_1+\frac{U_{\mathrm{REF}}-U_s}{R}\&CenterDot;t_2=0---\left(11\right)$

Get U _gND=0, can draw:

$\frac{U_s}{U_{\mathrm{REF}-}}=\frac{t_2}{t_1-t_2}---\left(12\right)$

According to charge conservation, can be obtained by fourth stage and five-stage:

$\frac{U_{\mathrm{REF}+}-U_s}{R}\&CenterDot;t_3+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_4=0---\left(13\right)$

Namely

$\frac{U_{\mathrm{REF}+}}{U_{\mathrm{REF}-}}=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(14\right)$

Order

U _REF+＝a·U _REF- (15)

In formula:

$a=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(16\right)$

Order

U _s＝b·U _REF- (17)

In formula:

$b=\frac{t_2}{t_1-t_2}.---\left(18\right)$

Second step: measure U _1a, U _1b, U _2a, U _2bwith U _rEF+, U _rEF-, U _sbetween proportionate relationship:

For integrating circuit, measuring these four magnitudes of voltage is the same for this integrating circuit, needs to measure successively, now provides and measures tested voltage U _insequential chart:

By U _in-U _spolarity integral process can be divided into two kinds of situations, the first situation U _in-U _s>0, as shown in Figure 3, the second situation U _in-U _s<0, as shown in Figure 4:

The first situation U _in-U _s>0: whole integration can be divided into four-stage, the stage that wherein resets does not draw in the drawings:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage rise; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle.Now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₆, this stage terminates.

According to principle of charge conservation, can be obtained by subordinate phase and phase III

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_6=0$

Convolution (15), (16), (17), (18)

Can obtain:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-t_6}{t_5}---\left(18\right)$

Order

U _in＝c·U _REF- (19)

In formula:

$c=\frac{b(t_5+t_6)-t_6}{t_5}.---\left(20\right)$

The second situation U _in-U _s<0, whole integration can be divided into double teacher, and the stage that wherein resets does not draw in the drawings:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R<0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage rise; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle.Now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW2 closes, and rest switch disconnects, and now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, U ₁voltage drop reverses to comparer, then continues a bit of time t of charging again ₀, total integral time is t ₆, this stage terminates.

E) fourth stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₇, this stage terminates.

The reason not terminating timing when phase III comparer reversion is to reduce comparer at different directions, the inconsistent error brought of the transmission delay of reversing under different slew rate.Error is brought because comparer reverses from different directions, index can be made to decline, and after recharging a period of time, coordinate fourth stage, make the starting point of integration be that comparer reverses and draws from equidirectional, identical slew rate, eliminate to the full extent by the inconsistent error brought of comparer twice inversion delay.

According to principle of charge conservation, can be obtained by subordinate phase, phase III and fourth stage

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_6+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_7=0$

Convolution (15), (16), (17), (18)

That is:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}---\left(21\right)$

Make U _in=cU _rEF-(22)

In formula:

$c=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}.---\left(23\right)$

After second step completes, U can be drawn by formula (19), (20), (22), (23) _inwith U _rEF-relation, i.e. U _1a, U _1b, U _2a, U _2bwith U _rEF-relation: (due to U _rEF+, U _rEF-, U _sbetween proportionate relationship known, also can draw U _1a, U _1b, U _2a, U _2bwith U _rEF+or U _srelational expression)

U _1a＝c _1a·U _REF- (24)

U _1b＝c _1b·U _REF- (25)

U _2a＝c _2a·U _REF- (26)

U _2b＝c _2b·U _REF- (27)

Can be obtained by formula (24), (25), (26), (27):

$Z_1=\frac{\sqrt{c_{1a}^2+c_{1b}^2}}{\sqrt{c_{2a}^2+c_{2b}^2}}\left|Z_2\right|---\left(28\right)$

Foregoing is the specific embodiment of the invention, does not form limiting the scope of the present invention.Any amendment done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within claims of the present invention.

Claims (9)

1. an integration ratio circuit, for measuring the ratio of two combined-voltage signal DC component, is characterized in that, comprising operational amplifier, integrating amplifier, comparer; The positive input terminal of described operational amplifier connects measured signal, the positive-negative output end of standard voltage source and earth potential respectively by the first interrupteur SW 1, second switch SW2, the 3rd interrupteur SW 3, the 4th interrupteur SW 4, the output terminal of operational amplifier is connected with negative input end, and connected the negative input end of described integrating amplifier by integrating resistor R, the output terminal of described integrating amplifier connects the positive input terminal of described comparer; Connect integrating capacitor between the negative input end of described integrating amplifier and output terminal, the two ends of described integrating capacitor have charge switch SW0; The positive input terminal of described integrating amplifier connects forward end reference voltage U _rEF1, the negative input end of described comparer connects negative end reference voltage U _rEF2.

2. based on an impedance measurement method for integration ratio circuit as claimed in claim 1, it is characterized in that, by measuring the in-phase component U of ac voltage signal under reference orthogonal coordinate system of tested impedance _1awith quadrature component U _1band the in-phase component U of the ac voltage signal of normal impedance under reference orthogonal coordinate system _2awith quadrature component U _2bbetween the ratio of DC component, impedance measurement is converted to the ratio of measuring voltage DC component, concrete steps are as follows:

Step 1), first determine the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2size;

Step 2), measure and draw the forward end reference voltage U be connected with the positive input terminal of integrating amplifier _rEF1, the negative end reference voltage U to be connected with the negative input end of comparer _rEF2, the integration initial voltage U be carried on current-limiting resistance R _sbetween proportionate relationship;

Step 3), measure respectively and draw the in-phase component U of the ac voltage signal of tested impedance under reference orthogonal coordinate system _1a, quadrature component U _1b, normal impedance ac voltage signal with reference to the in-phase component U under orthogonal coordinate system _2a, quadrature component U _2bwith described forward end reference voltage U _rEF1, negative end reference voltage U _rEF2, the voltage U be carried on resistance R _sbetween proportionate relationship;

Step 4), utilize step 2) with step 3) result that draws, by formula

$Z_1=\sqrt{\frac{U_{1a}^2+U_{1b}^2}{\sqrt{U_{2a}^2+U_{2b}^2}}}\left|Z_2\right|$

Calculate tested impedance.

3. impedance measurement method according to claim 2, is characterized in that, described step 1) in, determine forward end reference voltage U _rEF1, with negative end reference voltage U _rEF2concrete steps as follows:

When earthy 4th interrupteur SW 4 of connection is in closed, when other switches disconnect, select U _rEF1making electric capacity C charging direction perseverance be forward or perseverance is negative sense, i.e. U _gND+ V _oS1-U _eperseverance be just or perseverance be negative; During charging:

U _e＝U _REF1+V _OS2+I _B2·R+I _SW0·R

V _oS1, V _oS2---the bias voltage of-operational amplifier and integrating amplifier;

I _b2---the bias current of-operational amplifier;

I _sW0----be divided into, interrupteur SW 0 was at closed situation and the leakage current under opening situation;

Equally, U is selected _rEF2make the positive and negative input voltage of comparer A3 under integrate-dump state difference permanent for just or perseverance be negative; I.e. U _rEF2-V _oS3-U _eperseverance be just or perseverance be negative, Vos ₃for the bias voltage of comparer.

4. impedance measurement method according to claim 3, is characterized in that, described step 2) in, measuring process selects integration direction to be U _gND+ V _oS1-U _e>0, U _rEF2-V _oS3-U _e>0, comprises the following steps:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity C is with (U _rEF--U _sthe current charges of)/R<0, integrating amplifier output voltage U ₁rise to comparer reversion, this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW4 closes, and rest switch disconnects, and start timing after SW4 is closed, now electric capacity C is with (U _gND-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₁, this stage U ₁voltage reduces;

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₂, this stage terminates;

E) fourth stage, SW2 closes, and rest switch disconnects, and start timing after SW2 is closed, now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₃, this stage U ₁voltage reduces;

F) five-stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₄, this stage terminates;

Wherein: U _rEF+, U _rEF-be respectively the positive and negative terminal output voltage of standard voltage source.

5. impedance measurement method according to claim 4, is characterized in that, described step 2) in, by t1, t2, t3, t4 of recording,

According to charge conservation, can be obtained by subordinate phase and phase III:

$\frac{U_{\mathrm{GND}}-U_s}{R}\&CenterDot;t_1+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_2=0---\left(11\right)$

Get U _gND=0, can draw:

$\frac{U_s}{U_{\mathrm{REF}-}}=\frac{t_2}{t_1-t_2}---\left(12\right)$

According to charge conservation, can be obtained by fourth stage and five-stage:

$\frac{U_{\mathrm{REF}+}-U_s}{R}\&CenterDot;t_3+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_4=0---\left(13\right)$

Namely

$\frac{U_{\mathrm{REF}+}}{U_{\mathrm{REF}-}}=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(14\right)$

Order

U _REF+＝a·U _REF- (15)

In formula:

$a=\frac{t_2{t}_3+2t_2{t}_4-t_1{t}_4}{(t_1-t_2)\&CenterDot;t_3}---\left(16\right)$

Order

U _s＝b·U _REF- (17)

In formula:

$b=\frac{t_2}{t_1-t_2}.---\left(18\right)$

6. impedance measurement method according to claim 5, is characterized in that, described step 3) in, work as U _in-U _sduring >0, whole integration is divided into four-stage:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R>0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage reduces; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle, now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₆, this stage terminates.

7. impedance measurement method according to claim 6, is characterized in that, described step 3) in, according to t5, t6 of recording,

According to principle of charge conservation, can be obtained by subordinate phase and phase III

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_6=0$

Convolution (15), (16), (17), (18)

Can obtain:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-t_6}{t_5}---\left(18\right)$

Order

U _in＝c·U _REF- (19)

In formula:

$c=\frac{b(t_5+t_6)-t_6}{t_5}.---\left(20\right)$

8. impedance measurement method according to claim 5, is characterized in that, described step 3) in, work as U _in-U _sduring <0, whole integration is divided into double teacher:

A) reset stage: SW0 and SW4 to close, now integrating capacitor electric discharge;

B) first stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and this stage terminates, and this stage act as provides integration starting point to integration;

C) subordinate phase, SW1 closes, and rest switch disconnects, and now electric capacity is with (U _in-U _sthe current charges of)/R<0, according to selected clock and required resolution, selects suitable integral time, and timing time is t ₅, this stage U ₁voltage rise; Due to U _insignal is the signal of an alternating current-direct current superposition, in order to its AC compounent of filtering, and t ₅for the integral multiple in its AC compounent cycle, now according to U _othe polarity of voltage judges U _in-U _spolarity;

D) phase III, SW2 closes, and rest switch disconnects, and now electric capacity is with (U _rEF+-U _sthe current charges of)/R>0, U ₁voltage drop reverses to comparer, then continues a bit of time t of charging again ₀, total integral time is t ₆, this stage terminates;

E) fourth stage, SW3 closes, and rest switch disconnects, and now electric capacity is with (U _rEF--U _sthe current charges of)/R<0, U ₁voltage rise is reversed to comparer, and timing time is t ₇, this stage terminates.

9. impedance measurement method according to claim 8, is characterized in that, described step 3) in, according to t5, t6, t7 of recording,

According to principle of charge conservation, can be obtained by subordinate phase, phase III and fourth stage

$\frac{U_{\mathrm{in}}-U_s}{R}\&CenterDot;t_5+\frac{U_{\mathrm{REF}+}-U_s}{R}\&CenterDot;t_6+\frac{U_{\mathrm{REF}-}-U_s}{R}\&CenterDot;t_7=0$

Convolution (15), (16), (17), (18)

That is:

$\frac{U_{\mathrm{in}}}{U_{\mathrm{REF}-}}=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}---\left(21\right)$

Make U _in=cU _rEF-(22)

In formula:

$c=\frac{b(t_5+t_6)-a{t}_6+(b-1)t_7}{t_5}.---\left(23\right)$