CN217009193U - Semiconductor package - Google Patents

Abstract

The present disclosure relates to a semiconductor package. According to an embodiment of the present disclosure, a semiconductor package includes a substrate and a die stack. The substrate has a first surface. The die stack is disposed on the first surface of the substrate. A top die of the die stack includes a first notch at an edge of the top die. Due to the design of the first recess of the top die, the non-conductive film used to attach the die to another die to form a stack of dies does not contact the top surface of the top die, thereby avoiding reliability problems caused by exposing the non-conductive film at the edge of the top die when a subsequent thinning process is performed from the top surface of the top die.

Description

Semiconductor package

Technical Field

The present disclosure generally relates to a semiconductor package.

Background

In High Bandwidth Memory (HBM) packages such as HBM3, a non-conductive film (NCF) is used to attach a die to another die to form a die stack. Since NCFs are fluid, when a die is attached to another die by an NCF to form a die stack, the NCF between the dies may be squeezed out and spread to the die edge of the die stack. When the NCF is extruded, the extruded NCF will encapsulate a small amount of air creating voids. If the NCF at the edge of the die is exposed to air, moisture is likely to enter the package through voids in the NCF and cause reliability problems.

The die stack and the NCF at the die edge of the die stack are typically packaged using a molding material so that the NCF is not exposed to air. However, since the top die of the die stack continues to be thinned after packaging in subsequent processes such as grinding, the NCF adjacent the edge of the top die is exposed to air, causing reliability problems due to voids.

In view of the above, there is a strong need in the art to provide improved solutions to the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

In view of this, the present disclosure provides a semiconductor package including a die stack having a notch at an edge of a top die, and because the notch is formed at the edge of the top die, the NCF does not contact the top surface of the top die and is located at a distance from the top surface of the top die, thereby avoiding reliability problems caused by exposing the NCF at the edge of the top die when a subsequent thinning process is performed from the top surface of the top die.

According to an embodiment of the present disclosure, a semiconductor package includes a substrate and a die stack. The substrate has a first surface. The die stack is disposed on the first surface of the substrate, and a top die of the die stack includes a first notch located at an edge of the top die.

According to some embodiments of the present disclosure, the semiconductor package further includes a molding material disposed on the first surface of the substrate and encapsulating the die stack, wherein a portion of the molding material is in the first recess.

According to some embodiments of the present disclosure, the top die includes a protruding portion and the molding material surrounds a side surface of the protruding portion.

According to some embodiments of the present disclosure, a top surface of the protruding portion is exposed from a top surface of the molding material.

According to some embodiments of the present disclosure, the semiconductor package further comprises a non-conductive film disposed between the top die and a die below the top die, wherein the non-conductive film climbs a side surface of the top die.

According to some embodiments of the present disclosure, the non-conductive film climbs a side surface of the die below the top die.

According to some embodiments of the present disclosure, the top die includes a surface connected to the side surface of the top die and the non-conductive film extends to the surface of the top die.

According to some embodiments of the disclosure, the molding material encapsulates the non-conductive film.

According to some embodiments of the present disclosure, the first recess includes a bottom surface and a distance between the bottom surface of the first recess to a top surface of the molding material is greater than a maximum particle size of a filler of the molding material.

According to some embodiments of the present disclosure, wherein the non-conductive film comprises at least one void adjacent to the side surface of the top die or a side surface of the die below the top die.

According to some embodiments of the present disclosure, the top die includes a second recess at an opposite edge of the top die.

According to some embodiments of the present disclosure, a thickness of the top die is greater than a thickness of the die below the top die.

According to some embodiments of the disclosure, the substrate is a logic die.

According to some embodiments of the disclosure, the die stack is a memory die stack.

Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the utility model.

Drawings

Fig. 1 shows a cross-sectional view of a semiconductor package with NCF exposed easily.

Fig. 2 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure.

Fig. 3A to 3F illustrate methods of manufacturing semiconductor packages according to some embodiments of the present disclosure, wherein fig. 3C is an enlarged view of a dotted frame in fig. 3B.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. The shapes of the respective members illustrated in the drawings are merely exemplary shapes, and do not limit the actual shapes of the members. Additionally, the implementations illustrated in the figures may be simplified for clarity. Thus, the figures may not illustrate all of the components of a given device or apparatus. Finally, the same reference numerals may be used throughout the description and drawings to refer to the same features.

Detailed Description

In order to better understand the spirit of the present invention, the following description is given with reference to some embodiments of the present invention.

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The specific embodiments of components and arrangements described below are provided to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the utility model be constructed or operated in a particular orientation.

Various embodiments of the present invention are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. A person skilled in the relevant art will recognize that other components and configurations may be used without parting from the spirit and scope of the utility model. The present invention may be implemented without including all the components or steps in the embodiments described in the specification, and the execution sequence of each step may be adjusted according to the actual application.

Fig. 1 shows a cross-sectional view of a semiconductor package with NCF exposed easily. As shown in fig. 1, the semiconductor package 10 includes a substrate 100 and a die stack 110. The die stack 110 is located on a first surface 1001 of the substrate 100. The die stack 110 includes a top die 111 and a plurality of dies 112 (only one 112 is labeled in fig. 1 as an example) stacked below the top die 111. The multiple dies 112 can have the same or different lengths, widths, and thicknesses. The top die 111 may be the same or different in length, width, and thickness as each die 112. In some embodiments, the top die 111 has a thickness greater than a thickness of the at least one die 112. The die stack 110 also includes bumps 113 between the dies to electrically connect the top die 111 and the underlying die 112 or to electrically connect multiple dies 112. The die stack 110 may also be electrically connected to the substrate 100 by bumps 113 on its lowermost die 112. The semiconductor package 10 may further include an NCF120, the NCF120 being disposed between the top die 110 and the die 112, between the die 112 and the die 112, and between the die 112 and the substrate 100 for bonding thereof. The NCF120 may climb up the side surface of the die stack 110 to the side surface of the top die 111 and may include a plurality of voids 121. Voids 121 in NCF120 may be adjacent to a side surface of top die 111 or a side surface of die 112. The semiconductor package 10 may further include a molding material 130, the molding material 130 being disposed on the first surface 1001 of the substrate 100 and encapsulating the die stack 110 and the NCF 120. Although the NCF120 in the semiconductor package 10 is encapsulated by the molding material 130, when the semiconductor package 10 is subjected to a subsequent thinning process from the top surface of the top die 111, the top die 111 is thinned together with the molding material 130 on the side surfaces thereof, so that the NCF120 on the side surfaces of the top die 111 is exposed to air, and moisture is likely to enter the semiconductor package 10 through the voids 121 in the NCF120 and cause a reliability problem of the semiconductor package 10.

To overcome the foregoing technical problems, the present disclosure provides a semiconductor package having notches at the edges of the top die that may be protected from the risk of NCF exposure on the side surfaces of the top die or the problems described above.

Fig. 2 illustrates a cross-sectional view of a semiconductor package according to some embodiments of the present disclosure. As shown in fig. 2, the semiconductor package 20 includes a substrate 200 and a die stack 210. The substrate 200 has a first surface 2001. The die stack 210 is disposed on the first surface 2001 of the substrate 200. The die stack 210 includes a top die 211, the top die 211 including a first notch 215a at an edge thereof.

In some embodiments, die stack 210 further includes at least one die 212 located below top die 211. Fig. 2 shows 5 dies 212, but it is not limited thereto, and the die stack 210 may include one, two, or more dies 212. The plurality of dies 212 may have the same or different lengths, widths, and thicknesses. The length, width, and thickness of the top die 211 may be the same or different from each die 212. In some embodiments, the thickness of the top die 211 is greater than the thickness of the at least one die 212.

In some embodiments, the die stack 210 can further include conductive connections 213, the conductive connections 213 being located between the top die 211 and the die 212, between the die 212 and the die 212, and between the die 212 and the substrate 200 to electrically connect the top die 211, the plurality of dies 212, and the substrate 200. In some embodiments, the conductive connection 213 is a bump.

In some embodiments, top die 211 may further include a second recess 216a at opposing edges and a protruding portion 211p between first recess 215a and second recess 216 a. In some embodiments, the top die 211 generally has a "raised" shaped cross section. The first recess 215a may have a bottom surface 215b, the bottom surface 215b connected to a side surface 211c of the top die 211 and a side surface 211a of the protruding portion 211 p. The distance between the side surface 211c and the side surface 211a is the width of the first recess 215 a. The second recess 216a has a bottom surface 216b, the bottom surface 216b being connected to the side surface 211d of the top die 211 and the side surface 211b of the protruding portion 211 p. The distance between the side surface 211d and the side surface 211b is the width of the second recess 216 a. In some embodiments, the first recess 215a has the same width as the second recess 216 a.

In some embodiments, the semiconductor package 20 further includes a molding material 230. A molding material 230 is disposed on the first surface 2001 of the substrate 200 and encapsulates the die stack 120. In some embodiments, a portion of the molding material 230 is in at least one of the first recess 215a and the second recess 216 a. In some embodiments, the molding material 230 surrounds the side surfaces of the protruding portion 211p, and the top surface 211t of the protruding portion 211p is exposed from the top surface 230t of the molding material 230 and coplanar with the top surface 230 t. The distance h1 between the bottom surface 215b of the first recess 215a and the top surface 230t of the molding material 230 is the depth of the first recess 215 a. The distance h2 between the bottom surface 216b of the second recess 216a and the top surface 230t of the molding material 230 is the depth of the second recess 216 a. In some embodiments, the first recess 215a and the second recess 216a have the same depth.

In some embodiments, the semiconductor package 20 further includes an NCF 220, the NCF 220 being encapsulated with the die stack 210 by a molding material 230. In some embodiments, NCF 220 is disposed between top die 211 and die 212, between die 212 and die 212, and between die 212 and substrate 200, and extends along a side surface of die stack 210. In some embodiments, at the side of the die stack 210 having the first recess 215a, the NCF 220 climbs up the side surface 212c of the die 212 and the side surface 211c of the top die 211 to the bottom surface 215b of the first recess 215a of the top die 211 and is coplanar with the bottom surface 215b of the first recess 215 a. In some embodiments, on the opposite side of die stack 210 having second recess 216a, NCF 220 climbs up side surface 212d of die 212 and side surface 211d of top die 211 to bottom surface 216b of second recess 216a of top die 211 and is coplanar with bottom surface 216b of second recess 216 a. In some embodiments, NCF 220 includes at least one void 221, and void 221 may be adjacent to side surfaces 211c and 211d of top die 211 or side surfaces 212c and 212d of die 212 below the top die.

Since the top die 211 in the semiconductor package 20 has the first recess 215a and the second recess 216a and the first recess 215a and the second recess 216a are filled with the molding material 230, the side surface of the protruding portion 211p of the top die 211 is surrounded by the molding material 230 without the NCF 220, thereby making the semiconductor package 20 less susceptible to exposure of the NCF in a subsequent thinning process (e.g., a grinding process). That is, in the semiconductor package 20, even if the protruding portion 211p of the top die 211 and the molding material 230 on the side surface of the protruding portion 211p are thinned by a certain thickness, it is still ensured that the NCF 220 on the side surface 211c of the top die 211 is covered with the molding material 230 so that the NCF 220 is not exposed to the air, thereby avoiding the reliability problem due to the void 221 in the NCF 220.

In some embodiments, the molding material 230 includes fillers of different particle sizes, and h1 and/or h2 are larger than the maximum particle size of the fillers of the molding material 230 in order to provide a safety margin for the subsequent thinning process. In some embodiments, the maximum particle size of the filler in molding material 230 is 25 μm, and each of h1 and h2 is greater than or equal to 30 μm, such that molding material 230 over NCF 220 or bottom surface 215b of first indentation 215a or bottom surface 216b of second indentation 216a has a thickness of at least 30 μm to ensure that the coating of molding material 230 remains over NCF 220 even if the maximum particle size filler is pulled over NCF 220 in a subsequent thinning process.

In some embodiments, the molding material 230 includes an epoxy resin and a silica filler.

In some embodiments, substrate 200 is a logic die and die stack 210 is a memory die stack.

Fig. 3A-3F illustrate methods of making semiconductor packages according to some embodiments of the present disclosure. A method of manufacturing the semiconductor package of the present disclosure will be described in detail below with reference to fig. 3A to 3F.

As shown in fig. 3A, the die stack 310 is disposed on the first surface 3001 of the substrate 300 using the NCF 320. The other surface of the substrate 300 opposite to the first surface 3001 is bonded to a carrier substrate 302 by an adhesive 301. The die stack 310 has a top die 311 and at least one die 312 located below the top die 311. The NCF 320 is disposed between the dies of the die stack 310 and may extend onto the side surfaces of the die stack 310. NCF 320 may include voids (not shown) on the side surfaces of die stack 310.

As shown in fig. 3B, a half-cut process is performed along the edge of the top die 311 using a thick blade 350. Fig. 3C is an enlarged view of a dotted frame in fig. 3B. As shown in fig. 3B and 3C, the thick blade 350 cuts down the edge of the top die 311 of the die stack 310 to remove a portion of the top die 311 and the NCF 320 on the side surface of the top die 311. Thus, a notch is formed at the edge of the top die 311, and the NCF 320 on the side surface of the top die 311 is coplanar with the bottom surface of the notch. The notch may be formed to any depth using a half-cut process, and the depth of the notch is not limited to half the height of the top die 311. The width of the notch can be adjusted according to the process requirements.

As shown in fig. 3D, the half-cut process is repeated along the x-direction and y-direction of the substrate 300 using the thick blade 350, respectively, such that each edge of the top die 311 of each die stack 310 is subjected to the half-cut process.

Next, as shown in fig. 3E, the substrate 300 is molded on the first surface 3001 of the substrate 300 using a molding material 330. Such that the die stack 310 and the NCF 320 on the substrate 300 are completely encapsulated by the molding material 330. The top die 311 of the die stack 310 has notches at two opposite edges, respectively, so the top die 311 assumes a "convex" shape. Both recesses of the top die 311 are filled with a molding material 330. NCF 320 on the side surface of die stack 310 extends to the bottom of the recess of top die 311 and is coplanar with the bottom surface of the recess.

Then, as shown in fig. 3F, the top die 311 and the molding material 330 are thinned by a mechanical grinding process to expose the back side of the top die 311. Finally, the carrier substrate 302 may be removed and the molding material 330 and the substrate 300 may be cut to form individual semiconductor packages (not shown).

The present disclosure helps eliminate the chance of NCFs being exposed after grinding by performing an additional half-cut process on the top die and NCFs on the side surfaces of the top die. The additional half-cut process may ensure that the back surface of the die stack in the semiconductor package does not exhibit voids in the NCF, thereby improving the reliability of the semiconductor package.

The description in this specification is provided to enable any person skilled in the art to make or use the utility model. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the present invention is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (14)

1. A semiconductor package, wherein the semiconductor package comprises:

a substrate having a first surface; and

a die stack disposed on the first surface of the substrate, wherein a top die of the die stack includes a first notch located at an edge of the top die.

2. The semiconductor package of claim 1, further comprising a molding material disposed on the first surface of the substrate and encapsulating the die stack, wherein a portion of the molding material is in the first recess.

3. The semiconductor package of claim 2, wherein the top die comprises a protruding portion and the molding material surrounds a side surface of the protruding portion.

4. The semiconductor package of claim 3, wherein a top surface of the protruding portion is exposed from a top surface of the molding material.

5. The semiconductor package of claim 4, further comprising a non-conductive film disposed between the top die and a die below the top die, wherein the non-conductive film climbs a side surface of the top die.

6. The semiconductor package of claim 5, wherein the non-conductive film climbs a side surface of the die below the top die.

7. The semiconductor package of claim 6, wherein the top die includes a surface connected to the side surface of the top die and the non-conductive film extends to the surface of the top die.

8. The semiconductor package of claim 7, wherein the molding material encapsulates the non-conductive film.

9. The semiconductor package of claim 2, wherein the first recess comprises a bottom surface and a distance between the bottom surface of the first recess to a top surface of the molding material is greater than a maximum particle size of a filler of the molding material.

10. The semiconductor package of claim 5, wherein the non-conductive film comprises at least one void adjacent to the side surface of the top die or a side surface of the die below the top die.

11. The semiconductor package of claim 1, wherein the top die includes a second notch at an opposite edge of the top die.

12. The semiconductor package of claim 5, wherein a thickness of the top die is greater than a thickness of the die below the top die.

13. The semiconductor package of claim 1, wherein the substrate is a logic die.

14. The semiconductor package of claim 13, wherein the die stack is a memory die stack.

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