CN217009178U - Semiconductor packaging structure - Google Patents

Abstract

The embodiment of the application discloses a semiconductor packaging structure, this packaging structure includes: the chip package comprises a substrate, a plurality of supporting bodies, a main chip and a plastic package body; wherein, a plurality of support position one-to-one bonds of predetermineeing on a plurality of supporters and the main chip for a plurality of supporters can play good supporting role to the main chip, and avoid the main chip has most suspension region, helps improving semiconductor package structure's reliability, and a plurality of supporters can also support the main chip at the plastic envelope in-process, improves semiconductor package structure's reliability. In addition, the height and the width of the metal micro-bumps can be controlled, so that the height and the width of the supporting body can be controlled according to the structure and the actual requirement of the main chip, the supporting of the main chip by the supporting body is favorably ensured, the width of the metal micro-bumps is smaller than that of the supporting chip, and the packaging density of the semiconductor packaging structure is favorably improved.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure.

Background

With the increasing demand for large capacity, miniaturization, thinning and high integration of electronic devices, higher requirements are also put forward on the packaging density of electronic devices to reduce the size of the electronic device packaging structure, and further reduce the volume occupied by the electronic device package during assembly.

At present, a commonly used semiconductor package structure includes a substrate, a supporting chip and a plurality of components on the surface of the substrate, and further includes a main chip stacked on the supporting chip, wherein the main chip is fixed on the supporting chip to improve the packaging density of the package structure, thereby reducing the size of the package structure. However, in general, when the main chip is fixed on the supporting chip, the main chip has a large suspension area, that is, a supporting surface of the main chip has a large area that is not supported by the supporting chip, so that the main chip is deformed or bent in a process of wire bonding between the main chip and the substrate, and in severe cases, the main chip may crack to damage the main chip, which affects normal operation of the main chip, and thus affects normal operation of the semiconductor package structure. Therefore, it is important for those skilled in the art to provide a semiconductor package structure that can contribute to suppressing the deformation, bending, and cracking of the main chip.

SUMMERY OF THE UTILITY MODEL

In order to solve the above technical problem, embodiments of the present application provide a semiconductor package structure, which can help to suppress deformation, bending, and cracking of a main chip, and further help to improve reliability of the semiconductor package structure.

In order to solve the above problem, the embodiment of the present application provides the following technical solutions:

a semiconductor package structure, comprising:

a substrate;

the plurality of supporting bodies are positioned on the surface of the substrate and comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;

the main chip is connected with the substrate, one side of the main chip, facing the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip;

and the plastic package body is positioned on the surface of the substrate, extends to one side back to the surface of the substrate and covers the surface of the substrate, the support body and the main chip.

Optionally, the height of the metal micro-bump ranges from 20um to 50um, and the width of the metal micro-bump ranges from 30um to 100 um;

the width of the metal micro-bump is the radial length of the metal micro-bump along a first direction, the height of the metal micro-bump is the radial length of the metal micro-bump along a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

Optionally, the main chip includes a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the plurality of sub-chips except the first sub-chip has a suspension region, and a part of the plurality of preset support positions is located in the first sub-chip, and another part of the plurality of preset support positions is located in the suspension region;

one part of the plurality of supporting bodies is adhered to a preset supporting position on the first sub-chip, and the other part of the plurality of supporting bodies is adhered to a preset supporting position on the suspension area;

the first sub-chip is the sub-chip closest to the surface of the substrate among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded on one side facing the surface of the substrate.

Optionally, the method further includes: the support body is fixed on one side, deviating from the surface of the substrate, of the first bonding pad;

and one side of the main chip, which is far away from the surface of the substrate, is provided with a third bonding pad, the third bonding pad is connected with an internal circuit of the main chip, and the third bonding pad is connected with the second bonding pad.

Optionally, the method further includes: the control chip and the fourth bonding pad are positioned on the surface of the substrate, a fifth bonding pad is arranged on one side, away from the surface of the substrate, of the control chip, and the fourth bonding pad is connected with the fifth bonding pad;

the fourth bonding pad is connected with the internal circuit of the substrate, and the fifth bonding pad is connected with the internal circuit of the control chip.

Optionally, the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are made of the same material and are all one of gold, silver, copper and aluminum.

Optionally, the method further includes:

and a plurality of solder balls are arranged on one side of the substrate, which is far away from the main chip, and the solder balls are I/O interfaces of the semiconductor packaging structure.

Compared with the prior art, the technical scheme has the following advantages:

the technical scheme provided by the application comprises the following steps: the chip comprises a substrate, a plurality of supporting bodies, a main chip and a plastic package body; the plurality of supporting bodies are positioned on the surface of the substrate, and the supporting bodies comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate; the main chip is connected with the internal circuit of the substrate to ensure the normal work of the semiconductor packaging structure, one side of the main chip, which faces the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip. It should be noted that the preset support positions on the side of the main chip facing the substrate surface are obtained through mechanical analysis according to the structure of the main chip, and the support bodies are bonded to the preset support positions in a one-to-one correspondence manner, so that the support bodies can well support the main chip, most of the suspended areas of the main chip are avoided, the main chip can be prevented from being deformed, bent or even cracked, and the reliability of the semiconductor package structure can be improved. And the supporting body comprises a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate, and the height and the width of each metal micro-bump can be controlled, so that the height and the width of the supporting body can be controlled according to the structure and the actual requirement of a main chip, and the supporting of the main chip by the supporting body is favorably ensured. Meanwhile, the width of the metal micro-bump is smaller than that of a supporting chip in the conventional semiconductor packaging structure, so that the supporting body can have a larger height-width ratio relative to the supporting chip, and the packaging density of the semiconductor packaging structure is improved.

The semiconductor packaging structure comprises a plastic packaging body, wherein the plastic packaging body covers the surface of the substrate, the supporting body and the main chip so as to improve the mechanical strength of the semiconductor packaging structure and prevent water vapor in the external environment from entering the inside of the semiconductor packaging structure, and meanwhile, the supporting body can also support the main chip in the plastic packaging process so as to prevent the main chip from being bent, deformed or even cracked in the plastic packaging process, so that the reliability of the semiconductor packaging structure is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a conventional semiconductor package structure;

FIG. 2 is a schematic structural diagram of a semiconductor package structure proposed in patent CN100424871C

Fig. 3 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a process for fabricating a metal micro bump;

FIG. 5 is a top view of a wafer after being diced to produce chips;

fig. 6 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;

FIG. 8 is a schematic illustration of the dimensions of the microprotrusions;

fig. 9 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of another semiconductor package structure according to an embodiment of the present disclosure;

fig. 7 and fig. 11 are structural diagrams in a manufacturing process of a semiconductor package structure according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

As described in the background section, it is important for those skilled in the art to provide a semiconductor package structure that can help suppress deformation, warpage and cracking of a main chip.

Currently, in order to reduce the size of a semiconductor package structure and further reduce the space occupied by the semiconductor package structure during assembly, a common technical solution is to suspend a stacked main chip in the same semiconductor package structure. As shown in fig. 1, the conventional semiconductor package structure includes a substrate 60, and a plurality of components and supporting chips 61 located on a surface of the substrate, and further includes a main chip 62 stacked on the substrate, where the main chip 62 is connected to the substrate 60, and the main chip 62 is fixed to a side of the supporting chip 61 facing away from the surface of the substrate 60, that is, the main chip 62 is fixed at a position away from the surface of the substrate 10, so that the semiconductor package structure can extend longitudinally, thereby improving the packaging density of the semiconductor package structure.

In general, in order to make the supporting chips not occupy the space on the surface of the substrate for disposing components, so as to ensure the packaging density of the semiconductor packaging structure, the size of the supporting chip is smaller than that of the main chip, and one main chip corresponds to one supporting chip, so that when the main chip is fixed on the supporting chip, a larger suspension area exists on the side surface of the main chip supported by the supporting chip, that is, a large part of the area of the side surface of the main chip supported by the supporting chip does not exist on the side surface of the main chip not supported by the supporting chip.

It should be noted that the main chip has a chip pad connected to the internal circuit of the main chip, the substrate has a substrate pad connected to the internal circuit of the substrate, and the chip pad and the substrate pad are connected by a Wire Bonding (WB) process, so that the main chip is connected to the substrate. The process that the chip bonding pad is connected with the substrate bonding pad through the lead bonding comprises the following steps: welding spots are respectively formed on the surface of the chip welding pad and the surface of the substrate welding pad, and then the welding spots on the surface of the chip welding pad and the surface of the substrate welding pad are connected through welding wires. However, in the process of connecting the die pad and the substrate pad through a wire bonding process, the main chip is subjected to a large stress, so that when a large suspension area exists on the surface of one side of the main chip supported by the supporting chip, the main chip is deformed or bent, and the pad on the surface of the main chip is not connected well with the corresponding welding point. Because the surface of the main chip bonding pad connected with the welding spot is a plane, when the main chip is deformed or bent, the condition that the bonding pad on the surface of the main chip is in poor connection with the corresponding welding spot can occur, and the work of the semiconductor packaging structure is influenced.

In addition, in the process of connecting the main chip and the substrate, the main chip is sometimes connected with the substrate through a plurality of lead bonding processes, so that the main chip is repeatedly bent and deformed, and the welding spots on the surface of the main chip bonding pad are connected with the welding wires connected with the main chip bonding pad in a fatigue manner, so that the main chip bonding pad is easily damaged, and the service life and the reliability of the semiconductor packaging structure are affected. Meanwhile, as the semiconductor technology is developed, the thickness of the chip is gradually reduced, and the thinnest chip thickness has reached 25 um. Because the pressure born by the chip is in direct proportion to the thickness of the chip, when the thickness of the main chip is smaller, the pressure born by the chip is also gradually reduced, so that the possibility of bending and deformation of the main chip is also gradually increased in the process of connecting the main chip and the substrate through a wire bonding process, and the reliability of the semiconductor packaging structure is seriously influenced.

In order to solve the above problems, as shown in fig. 2, patent CN100424871C proposes that after a main chip and a supporting chip are disposed on a surface of a substrate and before wire bonding is performed, an adhesive layer made of non-conductor microspheres is added in a suspended area of the main chip to solve the problem of stress bending deformation of the suspended area of the main chip, but in the process of solving the problem in the patent, new materials and new processes are added, so that the cost and process complexity of a semiconductor package structure are increased, and the problem that the sizes of the microspheres are difficult to unify also exists, which affects the supporting effect on the suspended area of the main chip.

In addition, the process of forming the known semiconductor packaging structure also includes a plastic packaging process, and the plastic packaging process can generate large stress on the main chip, so that the main chip is bent or deformed, and the reliability of the semiconductor packaging structure is influenced. And before plastic packaging, the main chip is deformed or bent due to stress generated in the lead bonding process, so that the main chip is further deformed or bent in the plastic packaging process, even cracks are generated in the main chip, the main chip is damaged, the normal work of the main chip is influenced, and the normal work of the semiconductor packaging structure is further influenced.

Based on the above research, an embodiment of the present application provides a semiconductor package structure, as shown in fig. 3, the semiconductor package structure includes:

a substrate 10; it should be noted that the substrate is a thin circuit board for carrying a chip in the field of semiconductor packaging, but this is not limited in this application, and is determined as the case may be;

the plurality of supporting bodies 20 are positioned on the surface of the substrate 10, and the plurality of supporting bodies 20 comprise a plurality of metal micro-bumps 21 which are sequentially arranged along the side departing from the surface of the substrate 10;

the main chip 30 is connected with the substrate 10, one side of the main chip 30, which faces the surface of the substrate 10, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies 20 are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip 30; the side of the main chip bonded to the support body has an adhesive layer formed of an adhesive, so that the support body is bonded to the main chip; the preset support positions are used for performing mechanical approval on the main chip, and the obtained positions of the main chip needing to be supported are not embodied by the entity part on the main chip;

and the plastic package body 40 is positioned on the surface of the substrate 10, extends towards one side away from the surface of the substrate 10, and covers the surface of the substrate 10, the support body 20 and the main chip 30.

As shown in fig. 4, the process of forming the metal micro-bump includes: 1. the method comprises the following steps of (1) burning a ball by a cleaver and moving downwards, (2) continuing to move downwards by the cleaver to form a metal micro-bump main body on the surface of a substrate, (3) moving upwards by the cleaver to reach a Separation height, (4) moving downwards by the cleaver to finish a tangent line, and (5) moving upwards by the cleaver to finish the tangent line to form a metal micro-bump, wherein when a plurality of metal micro-bumps are formed on the surface of the substrate, the process is repeated to form the plurality of metal micro-bumps, and the process used for forming the metal micro-bumps is a process commonly used in the semiconductor field, and the details of the process are not described too much. It should be further noted that, as shown in fig. 5, the process of forming the main chip includes: providing a wafer 100, grinding the wafer 100 to a specified thickness, and then dividing the wafer 100 into a plurality of crystal grains to form the main chip 30.

Specifically, in the embodiment of the present application, the semiconductor package structure has a plurality of supporting bodies, the main chip has a plurality of predetermined supporting positions on a side facing the substrate surface, the positions of the plurality of preset supporting positions on the main chip are according to the shape of the main chip, the plurality of support positions are respectively bonded with the plurality of preset support positions in a one-to-one correspondence manner through mechanical analysis, so that the support body can support each position of the main chip to be supported, thereby enabling the support body to realize good support for the main chip, and the plurality of support positions are respectively bonded with the plurality of preset support positions in a one-to-one correspondence manner, so that the main chip can be prevented from having most of the suspended area, therefore, the main chip is prevented from bending, deforming and even cracking, and the semiconductor packaging structure has high reliability. Meanwhile, the support body can support each position of the main chip, which needs to be supported, so that the support body can also well support the main chip even under the condition that the thickness of the main chip is thinner, and the influence of the gradual thinning of the chip thickness on the reliability of the semiconductor packaging structure is favorably improved. It should be noted that, depending on the form of the object, it is a common technical means to perform mechanical analysis on each part of the object, and the description thereof is not repeated here.

And the supporting body in the semiconductor packaging structure comprises a plurality of micro-convex bodies which are sequentially arranged along one side departing from the surface of the substrate, the forming process of the micro-convex bodies comprises ball burning, ball pressing and tangent line, the difference with the process of lead bonding is only that after the ball pressing process, the tangent line is carried out, the metal bonding wire is cut off to form the micro-convex bodies, and the metal micro-convex points can be formed by a lead bonding process method. The process parameters of the known wire bonding process can be controlled to control the height and width of a product, so that the height and width of the micro-convex body can be controlled through the process parameters, the height and width of the supporting body can be controlled according to the shape and size of the main chip and the practical application environment, and the supporting body can be ensured to support the main chip well. It should be noted that, in order to reduce the influence of the wire tail left after the wire cutting on the stacking of the plurality of metal micro bumps, in the embodiment of the present application, a smooth micro bump (smooth bump) technology is used, which is helpful for reducing the wire tail left after the wire cutting, making the wire tail left smooth and uniform, and is helpful for stacking the plurality of metal micro bumps to form a supporting body.

In addition, it is known that the conventional semiconductor package structure includes supporting chips, and the main chips are located on the supporting chips and supported by the supporting chips, and since the width of the supporting chips is difficult to be small and difficult to achieve a large aspect ratio, in order to ensure the packaging density of the conventional semiconductor package structure, one main chip corresponds to one supporting chip. And the main chip among the semiconductor package structure that this application embodiment provided is supported by the supporter, the supporter includes a plurality of little bumps, little bump is the little bump of metal, the width of little convex body can be done for a short time, makes great aspect ratio can be accomplished to the supporter, and then makes the supporter can be right when the main chip supports, can also reduce the supporter as far as and be in the space that substrate surface occupied guarantees semiconductor package structure's packaging density.

Meanwhile, the semiconductor packaging structure comprises a plastic packaging body, and the plastic packaging body covers the substrate surface, the supporting body and the main chip so as to improve the mechanical strength of the semiconductor packaging structure and prevent water vapor in the external environment from entering the inside of the semiconductor packaging structure. The semiconductor packaging structure is known to generate large stress to the main chip in the plastic packaging process, so that the main chip is bent or deformed or even cracked, and the support body in the semiconductor packaging structure can well support the main chip, so that the main chip is prevented from being bent, deformed or even cracked in the plastic packaging process, and the semiconductor packaging structure has high reliability.

It should be noted that, in an embodiment of the present application, the main chip may be completely supported by the plurality of supporting bodies, so as to reduce the space of the semiconductor package structure occupied by supporting the main chip as much as possible, increase the available space of the semiconductor package structure, and improve the packaging density of the semiconductor package structure as much as possible; in another embodiment of the present application, as shown in fig. 6, the semiconductor package structure may also include a supporting chip 18, and the supporting chip 18 and the supporting body 20 jointly support the main chip 30, as the case may be. It should be noted that, in the embodiments of the present application, specific numbers of the plurality of supporting bodies are not limited, and are determined as the case may be. When the semiconductor package structure includes a supporting chip, as shown in fig. 7, before the main chip is supported, a supporting chip 18 is provided, and the supporting chip 18 is disposed on the surface of the substrate 10, so that the supporting chip can support the main chip.

Optionally, in an embodiment of the present application, as shown in fig. 8, a value range of a height h of the metal micro bump is 20um to 50um, a value range of a width d of the metal micro bump is 30um to 100um, wherein a width of the metal micro bump is a radial length of the metal micro bump along a first direction, a height of the metal micro bump is a radial length of the metal micro bump along a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction. However, this is not limited in this embodiment, and in other embodiments of the present application, the value range of the height of the metal micro bump and the value range of the width of the metal micro bump may also be other values, as the case may be. It should be noted that, in an embodiment of the present application, the height and the width of the metal micro bump may be adjusted according to a distance between a chip to be supported and a surface of a substrate, where the widths and the heights of the plurality of metal micro bumps in different supporting bodies may be consistent or inconsistent, and the widths and the heights of the metal micro bumps in the same supporting body may be consistent or inconsistent, which is not limited in this application embodiment, and in other embodiments of the present application, the widths and the heights of the plurality of metal micro bumps may also be inconsistent, depending on a situation.

It should be noted that, in order to increase the packing density of the semiconductor package structure, the stacked main chips are usually disposed in the package structure. Therefore, on the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 9, the main chip 30 includes a plurality of sub-chips 32 sequentially arranged along a side away from the surface of the substrate 10, at least one sub-chip 32 of the plurality of sub-chips 32 except a first sub-chip 33 has an overhang region 34, a part of the plurality of preset support locations is located on the first sub-chip 33, and another part of the plurality of preset support locations is located in the overhang region 34; one part of the plurality of supporting bodies 20 is adhered to a preset supporting position on the first sub-chip 33, and the other part is adhered to a preset supporting position in the suspending area 34, so that when the main chip comprises a plurality of sub-chips, the main chip is supported, and the main chip is prevented from being bent, deformed or even deformed. The first sub-chip is a sub-chip closest to the substrate surface among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not blocked from facing the substrate surface, that is, the suspension area is an area directly opposite to the substrate surface facing the substrate surface except the first sub-chip. It should be further noted that the number of the preset supporting positions on the first sub-chip and the position distribution on the first sub-chip are obtained through mechanical analysis, and the number of the preset supporting positions on the suspending area and the position distribution on the suspending area are also obtained through mechanical analysis. Meanwhile, when the main chip comprises a plurality of sub-chips, one side of each of the plurality of sub-chips, which faces the surface of the substrate, is provided with an adhesive layer, so that the plurality of sub-chips are fixedly adhered to each other through the adhesive layer, and the internal circuits of the plurality of sub-chips are sequentially connected through a wire bonding process, so that the plurality of sub-chips are sequentially connected.

On the basis of the above embodiments, in an embodiment of the present application, in order to fix the supporting body on the surface of the substrate and connect the main chip and the substrate, as shown in fig. 9, the semiconductor package structure further includes: a first pad 11 and a second pad 12 located on the surface of the substrate 10, where the first pad 11 is not connected to the internal circuit of the substrate 10, the second pad 12 is connected to the internal circuit of the substrate 10, and the support 20 is fixed to a side of the first pad 11 away from the surface of the substrate 10, so as to fix the support 20 on the surface of the substrate 10, so that the support 20 supports the main chip 30; the main chip 30 deviates from the substrate 10, a third bonding pad 13 is arranged on one side of the surface, the third bonding pad 13 is connected with an internal circuit of the main chip 30, the third bonding pad 13 is connected with the second bonding pad 12 through lead bonding, and the second bonding pad 12 is known to be connected with the internal circuit of the substrate 10, so that the main chip can be connected with the substrate, and the normal work of the semiconductor packaging structure is guaranteed.

And, discover when the number of the little bump of metal is not more than 5 according to the experiment, the little bump of metal can form stable supporter, and first pad also can be right the supporter carries out the stabilizing support, and is known the value range of the little bump height of metal is 20um ~ 50um, the value range of the little bump width of metal is 30um ~ 100um, thereby makes the height of supporter can reach 250um, and the thickness of general support chip is about 100um, promptly the height of supporter is greater than the thickness of supporting the chip, makes the vertical extension height of semiconductor package structure is higher, makes semiconductor package structure's packaging space is bigger, helps improving semiconductor package structure's packaging density.

In addition, the surface of the main chip is provided with a third bonding pad, the surface of the substrate is provided with a second bonding pad, and the third bonding pad is connected with the second bonding pad through wire bonding so that the main chip is connected with the substrate through wire bonding. Meanwhile, even if the manufacturing process of the semiconductor packaging structure does not comprise a lead bonding process, the lead bonding process is a process method frequently used in the semiconductor manufacturing process, and only the existing lead bonding process is used for manufacturing the metal micro-bumps, so that the difficulty of the manufacturing process is not increased. It should be noted that, the formation of the metal micro-bump and the connection between the main chip and the substrate may be completed in the same process step or different process steps, which is not limited in this application and is determined as the case may be.

On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 10, the semiconductor package structure further includes: the control chip 50 and the fourth bonding pad 14 are located on the surface of the substrate 10, the fifth bonding pad 15 is arranged on one side, away from the surface of the substrate 10, of the control chip 50, the fourth bonding pad 14 is connected with the fifth bonding pad 15, the fourth bonding pad 14 is connected with a circuit inside the substrate 10, the fifth bonding pad 15 is connected with a circuit inside the control chip 50, so that the control chip 50 is connected with the substrate, and the work of the semiconductor packaging structure is controlled through the control chip 50. The control chip is fixed to the surface of the substrate by an adhesive layer made of an adhesive. It should be further noted that, when the semiconductor package structure includes a control chip, as shown in fig. 11, the manufacturing of the semiconductor package structure includes: providing a control chip 50, arranging the control chip 50 on the surface of the substrate 10, wherein one side, departing from the surface of the substrate 10, of the control chip 50 is provided with a fifth bonding pad 15, the fifth bonding pad 15 is connected with the fourth bonding pad 14 through wire bonding, and the fifth bonding pad 15 is connected with an internal circuit of the control chip 50.

Optionally, in an embodiment of the present application, the first pad, the second pad, the third pad, the fourth pad, and the fifth pad are made of the same material, and are made of one of gold, silver, copper, and aluminum. However, this is not limited in this embodiment of the present application, and in other embodiments of the present application, the material of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad may also be other materials, as the case may be.

On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 12, a side of the substrate 10 away from the main chip 30 is provided with a plurality of solder balls 16, and the solder balls 16 are I/O interfaces of the semiconductor package structure, so that the semiconductor package structure can be connected to an external circuit to perform corresponding operations.

On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 12, the surface of the substrate 10 further has a plurality of passive elements 17, such as inductors, resistors, inductors, and the like, so that the semiconductor package structure can perform corresponding functions. The plurality of passive elements are fixed to the surface of the substrate by an adhesive layer made of an adhesive.

In summary, the embodiment of the present application provides a semiconductor package structure, which includes: the chip package comprises a substrate, a plurality of supporting bodies, a main chip and a plastic package body; the supporting bodies are bonded with the preset supporting positions on the main chip in a one-to-one correspondence manner, and it should be noted that the preset supporting positions on one side, facing the substrate surface, of the main chip are obtained through mechanical analysis according to the structure of the main chip, so that the supporting bodies can well support the main chip, most of suspended areas of the main chip are avoided, the main chip can be prevented from deforming, bending and even cracking, and the reliability of the semiconductor packaging structure is improved. Moreover, the height and the width of the plurality of metal micro-bumps can be controlled, so that the height and the width of the support body can be controlled according to the structure of the main chip and the actual requirement, and the support of the support body on the main chip is ensured. Meanwhile, the width of the metal micro-bump is smaller than that of a supporting chip in the conventional semiconductor packaging structure, so that the supporting body can have a larger height-width ratio relative to the supporting chip, and the packaging density of the semiconductor packaging structure is improved.

In addition, the support body can also support the main chip in the plastic package process, so that the main chip is prevented from being bent, deformed and even cracked in the plastic package process, and the reliability of the semiconductor packaging structure is improved.

All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.

In the above description of the disclosed embodiments, features described in various embodiments in this specification can be substituted for or combined with each other to enable those skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. A semiconductor package structure, comprising:

a substrate;

the plurality of supporting bodies are positioned on the surface of the substrate and comprise a plurality of metal micro-bumps which are sequentially arranged along one side departing from the surface of the substrate;

the main chip is connected with the substrate, one side of the main chip, facing the surface of the substrate, is provided with a plurality of preset supporting positions, and the plurality of supporting bodies are respectively bonded with the plurality of preset supporting positions in a one-to-one correspondence manner, so that the supporting bodies support the main chip;

and the plastic package body is positioned on the surface of the substrate, extends to one side back to the surface of the substrate and covers the surface of the substrate, the support body and the main chip.

2. The semiconductor package structure of claim 1, wherein the height of the metal microbumps ranges from 20um to 50um, and the width of the metal microbumps ranges from 30um to 100 um;

the width of the metal micro-bump is the radial length of the metal micro-bump along a first direction, the height of the metal micro-bump is the radial length of the metal micro-bump along a second direction, the first direction is parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

3. The semiconductor package structure according to claim 1, wherein the main chip comprises a plurality of sub-chips sequentially arranged along a side away from the substrate surface, at least one of the sub-chips except a first sub-chip has a suspending area, and a part of the plurality of preset supporting bits is located in the first sub-chip and another part is located in the suspending area;

one part of the plurality of supporting bodies is adhered to a preset supporting phase positioned on the first sub-chip, and the other part of the plurality of supporting bodies is adhered to a preset supporting phase positioned in the suspension area;

the first sub-chip is the sub-chip closest to the surface of the substrate among the plurality of sub-chips, and the suspension area is an area where the other sub-chips except the first sub-chip are not shielded on one side facing the surface of the substrate.

4. The semiconductor package structure of claim 1, further comprising: the first bonding pad and the second bonding pad are positioned on the surface of the substrate, the first bonding pad is not connected with the internal circuit of the substrate, the second bonding pad is connected with the internal circuit of the substrate, and the support body is fixed on one side of the first bonding pad, which is far away from the surface of the substrate;

and one side of the main chip, which is far away from the surface of the substrate, is provided with a third bonding pad, the third bonding pad is connected with the internal circuit of the main chip, and the third bonding pad is connected with the second bonding pad.

5. The semiconductor package structure of claim 4, further comprising: the control chip and the fourth bonding pad are positioned on the surface of the substrate, a fifth bonding pad is arranged on one side, away from the surface of the substrate, of the control chip, and the fourth bonding pad is connected with the fifth bonding pad;

the fourth bonding pad is connected with the internal circuit of the substrate, and the fifth bonding pad is connected with the internal circuit of the control chip.

6. The semiconductor package structure according to claim 5, wherein the first bonding pad, the second bonding pad, the third bonding pad, the fourth bonding pad and the fifth bonding pad are made of the same material and are made of one of gold, silver, copper and aluminum.

7. The semiconductor package structure of claim 1, further comprising:

and a plurality of solder balls are arranged on one side of the substrate, which is far away from the main chip, and the solder balls are I/O interfaces of the semiconductor packaging structure.

Images