CN216981915U - 5G optical module circuit, device and system - Google Patents
5G optical module circuit, device and system Download PDFInfo
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- CN216981915U CN216981915U CN202220684008.4U CN202220684008U CN216981915U CN 216981915 U CN216981915 U CN 216981915U CN 202220684008 U CN202220684008 U CN 202220684008U CN 216981915 U CN216981915 U CN 216981915U
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Abstract
The utility model provides a 5G optical module circuit, a device and a system, wherein the optical module circuit comprises: the circuit comprises a driving circuit, a light receiving circuit and a time delay circuit; the circuit converts a first trigger signal output by the light receiving circuit into a voltage signal, and performs charge and discharge according to the voltage signal to obtain a variable voltage; the circuit compares the variable voltage with a reference voltage to obtain a second trigger signal, and outputs the second trigger signal to the driving circuit so that the driving circuit outputs a reset signal to the light receiving circuit. The second trigger signal in the 5G optical module circuit widens the falling edge of the first trigger signal, so that the second trigger signal remains unchanged before the reset signal disappears, thereby ensuring that the second trigger signal is not affected by the reset signal, improving the stability of the second trigger signal, and further improving the stability of a system where the 5G optical module circuit is located.
Description
Technical Field
The utility model relates to the field of 5G optical modules, in particular to a 5G optical module circuit, a device and a system.
Background
The optical network is the infrastructure of the whole information communication network, and the rapid development and application of the optoelectronic science and the technical research greatly drives the development of the information communication industry. Passive optical networks in high-speed optical fiber transmission technology play an increasingly important role in current access networks. The passive optical fiber network system consists of an optical line terminal, an optical distribution network and an optical network unit. The optical line terminal has the functions of centralized bandwidth allocation, optical network unit control, real-time monitoring, operation and maintenance of the passive optical network system.
In the prior art, when an optical line terminal and an optical network unit are registered, the optical network unit inputs a high-frequency optical pulse signal to an optical receiving end, the optical pulse signal triggers the optical receiving end to output a trigger signal SD, the SD outputs a high level when light exists, and the SD outputs a low level when no light exists. When the trigger signal SD rises from low to high, the driving circuit is triggered to send a Reset signal Reset to the optical receiving end, and the Reset signal Reset discharges to a coupling circuit between an optical detection unit of the optical receiving end and the limiting amplifier LA, so that the electrical signal input to the LA by the optical detection unit can be quickly recovered, but the Reset signal Reset also triggers the SD to change from high level to low level, so that the trigger signal SD is unstable, and even normal registration of the optical line terminal and the optical network unit is affected.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a 5G optical module circuit, a device and a system, and aims to solve the problem that a trigger signal SD output by an optical receiving end of an optical module in the prior art is easily influenced by a Reset signal Reset sent by a driving circuit and is unstable.
In order to achieve the above object, the present invention provides a 5G optical module circuit, including: the circuit comprises a driving circuit, a light receiving circuit and a time delay circuit;
one end of the delay circuit is connected with one end of the light receiving circuit, the other end of the delay circuit is connected with one end of the driving circuit, and the other end of the driving circuit is connected with the other end of the light receiving circuit;
the delay circuit is used for converting the first trigger signal output by the light receiving circuit into a voltage signal, and charging and discharging according to the voltage signal to obtain a variable voltage;
the delay circuit is further configured to compare the variable voltage with a reference voltage to obtain a second trigger signal, and output the second trigger signal to the driving circuit, so that the driving circuit outputs a reset signal to the light receiving circuit.
Optionally, the delay circuit comprises: a voltage regulating circuit and a voltage comparing circuit;
the input end of the voltage regulating circuit is connected with the light receiving circuit, the output end of the voltage regulating circuit is connected with the input end of the voltage comparison circuit, and the output end of the comparison circuit is connected with the driving circuit;
the voltage regulating circuit is used for converting the first trigger signal output by the light receiving circuit into a voltage signal, and carrying out charging and discharging according to the voltage signal to obtain a variable voltage;
the voltage comparison circuit is used for comparing the variable voltage with a reference voltage to obtain a second trigger signal, and outputting the second trigger signal to the driving circuit so that the driving circuit outputs a reset signal to the light receiving circuit.
Optionally, the delay circuit further includes: a voltage dividing circuit;
one end of the voltage division circuit is connected with a power supply, the other end of the voltage division circuit is grounded, and the other end of the voltage division circuit is connected with the voltage comparison circuit;
the voltage division circuit is used for dividing the power voltage to obtain a reference voltage and outputting the reference voltage to the voltage comparison circuit.
Optionally, the voltage divider circuit includes: a first resistor and a second resistor;
one end of the first resistor is connected with a power supply, the other end of the first resistor is connected with one end of the second resistor and the voltage comparison circuit, and the other end of the second resistor is grounded.
Optionally, the voltage regulating circuit comprises: a signal conversion circuit and a voltage processing circuit;
the input end of the signal conversion circuit is connected with the light receiving circuit, the output end of the signal conversion circuit is connected with the input end of the voltage processing circuit, and the output end of the voltage processing circuit is connected with the voltage comparison circuit;
the signal conversion circuit is used for converting the first trigger signal sent by the light receiving circuit into a voltage signal and outputting the voltage signal to the voltage processing circuit;
and the voltage processing circuit is used for charging and discharging according to the voltage signal to obtain variable voltage and outputting the variable voltage to the voltage comparison circuit.
Optionally, the signal conversion circuit comprises: an NMOS tube and a third resistor;
the grid electrode of the NMOS tube is connected with the light receiving circuit, the drain electrode of the NMOS tube is connected with one end of a third resistor, the source electrode of the NMOS tube is connected with the voltage processing circuit, and the other end of the third resistor is grounded.
Optionally, the voltage processing circuit comprises: a first capacitor and a fourth resistor;
one end of the first capacitor is connected with the output end of the voltage regulating circuit, the input end of the voltage comparison circuit and one end of the fourth resistor respectively, and the other end of the first capacitor is connected with the other end of the fourth resistor.
Optionally, the voltage comparison circuit comprises: a voltage comparator;
the positive input end of the voltage comparator is connected with the voltage processing circuit, the negative input end of the voltage comparator is connected with the voltage dividing circuit, and the output end of the voltage comparator is connected with the driving circuit.
In order to achieve the above object, the present invention further provides a 5G optical module apparatus, where the 5G optical module apparatus includes the above 5G optical module circuit.
In order to achieve the above object, the present invention further provides a 5G communication system, where the 5G communication system includes the above 5G optical module apparatus.
The utility model provides a 5G optical module circuit, a device and a system, wherein the optical module circuit comprises: the circuit comprises a driving circuit, a light receiving circuit and a time delay circuit; the circuit converts a first trigger signal output by the light receiving circuit into a voltage signal, and performs charge and discharge according to the voltage signal to obtain variable voltage; the circuit compares the variable voltage with a reference voltage to obtain a second trigger signal, and outputs the second trigger signal to the driving circuit, so that the driving circuit outputs a Reset signal Reset to the light receiving circuit. In the scheme, the second trigger signal widens the falling edge of the first trigger signal, so that the second trigger signal is kept unchanged before the Reset signal Reset disappears, the second trigger signal is not influenced by the Reset signal Reset, the stability of the second trigger signal is improved, and the stability of the whole system is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a 5G optical module circuit according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a light receiving circuit according to a first embodiment of the present invention;
fig. 3 is a delay circuit diagram of a first embodiment of a 5G optical module circuit according to an embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) | |
| 10 | |
22 | |
|
| 20 | |
23 | |
|
| 30 | Time delay circuit | R1～R4 | First to |
|
| 31 | Voltage regulating circuit | | Voltage comparator | |
| 32 | Voltage comparison circuit | SD | A |
|
| 33 | Voltage divider circuit | OLT_SD | Second trigger messageNumber (C) | |
| 34 | Signal conversion circuit | C1 | |
|
| 35 | Voltage processing circuit | | NMOS transistor | |
| 21 | Light detection unit |
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the utility model and do not limit the utility model.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of a 5G optical module circuit according to an embodiment of the present invention. Based on fig. 1, a first embodiment of the 5G optical module circuit of the present invention is proposed.
In this embodiment, the 5G optical module circuit includes: a drive circuit 10, a light receiving circuit 20, and a delay circuit 30.
One end of the delay circuit 30 is connected to one end of the light receiving circuit 20, the other end of the delay circuit 30 is connected to one end of the driving circuit 10, and the other end of the driving circuit 10 is connected to the other end of the light receiving circuit 20.
It should be noted that the 5G optical module circuit provided in this embodiment can be applied to a data center, and implement 5G data communication between a server and a switch. The driving circuit 10 is configured to receive the second trigger signal OLT _ SD sent by the delay circuit 30, and then output a Reset signal Reset to the light receiving circuit 20, so that the light receiving circuit 20 can quickly resume operating. The light receiving circuit 20 is configured to receive a light signal, convert the light signal into an electrical signal, generate a first trigger signal SD, and output the first trigger signal SD to the delay circuit 30.
The driving circuit 10 may be a system MAC chip, and the system MAC chip may drive the light receiving circuit 20 to return to normal operation by the Reset signal Reset input to the light receiving circuit 20, and may also drive the level of the first trigger signal SD output by the light receiving circuit 20 to change.
Referring to fig. 2, the above-described light receiving circuit 20 may be composed of a photoelectric conversion unit 21, a slice control unit 23, a logic switch 22, and the like. The optical-to-electrical conversion unit 21 is used to convert the optical signal into an electrical signal, the amplitude limiting control unit 23 is used to amplify and amplitude limit this signal, and the logic switch 22 is used to input a Reset signal Reset to the amplitude limiting control unit.
The photoelectric conversion unit 21 may be composed of an avalanche photodiode APD and a transimpedance amplifier TIA, where the avalanche photodiode APD receives a burst optical signal, converts the optical signal into a photocurrent and transmits the photocurrent to the transimpedance amplifier TIA, and the transimpedance amplifier TIA converts the photocurrent into an optical signal and outputs the optical signal to the amplitude limiting control unit 23. The clipping control unit 23 may be a burst mode clipping amplifier.
It should be understood that the above-mentioned optical receiving circuit 20 outputs the first trigger signal SD of a high level when receiving the burst optical signal, and outputs the first trigger signal SD of a low level when the optical receiving circuit 20 does not receive the burst optical signal, that is, the first trigger signal SD is a fast follow indication signal for the arrival and the disappearance of the received burst optical signal.
In this embodiment, when the light receiving circuit 20 receives the high frequency burst light signal, the first trigger signal SD at a high level is output, and if the first trigger signal is directly output to the driving circuit 10, the driving circuit 10 will be triggered to send a Reset signal to the light receiving circuit 20, and the Reset signal Reset will change the first trigger signal SD output by the light receiving circuit 20 from the high level to a low level, thereby affecting the stability of the first trigger signal SD.
In this embodiment, the delay circuit 30 is configured to convert the first trigger signal SD output by the light receiving circuit 20 into a voltage signal, and perform charging and discharging according to the voltage signal to obtain a variable voltage; the variable voltage is compared with a reference voltage to obtain a second trigger signal OLT _ SD, and the second trigger signal OLT _ SD is output to the driving circuit 10, so that the driving circuit 10 outputs a Reset signal Reset to the light receiving circuit 20.
It should be noted that the first trigger signal SD is a voltage signal, a high level can be understood as a preset voltage value, and a low level can be understood as no voltage output; the first trigger signal SD is unstable due to the Reset signal Reset, but is converted by the delay circuit 30 to obtain a stable second trigger signal OLT _ SD, which is also a voltage signal outputting a high level and a low level. The reference voltage is obtained by dividing the power supply voltage by the delay circuit 30.
Referring to fig. 3, fig. 3 is a delay circuit diagram of a first embodiment of a 5G optical module circuit according to an embodiment of the present invention, where the delay circuit 30 includes: a voltage adjusting circuit 31 and a voltage comparing circuit 32;
wherein, the input end of the voltage adjusting circuit 31 is connected with the light receiving circuit 20, the output end of the voltage adjusting circuit 31 is connected with the input end of the voltage comparing circuit 32, and the output end of the voltage comparing circuit 32 is connected with the driving circuit.
The voltage adjusting circuit 31 is configured to convert the first trigger signal SD output by the light receiving circuit 20 into a voltage signal, and perform charging and discharging according to the voltage signal to obtain a variable voltage; the voltage comparison circuit 32 is configured to compare the variable voltage with a reference voltage to obtain a second trigger signal OLT _ SD, and output the second trigger signal OLT _ SD to the driving circuit 10, so that the driving circuit 10 outputs a Reset signal Reset to the light receiving circuit 20.
It should be understood that the voltage regulating circuit 31 described above includes: a signal conversion circuit 34 and a voltage processing circuit 35.
The input end of the signal conversion circuit 34 is connected to the light receiving circuit 20, the output end of the signal conversion circuit 34 is connected to the input end of the voltage processing circuit 35, and the output end of the voltage processing circuit 35 is connected to the voltage comparison circuit 33.
The signal conversion circuit 34 converts the first trigger signal SD transmitted by the light receiving circuit 20 into a voltage signal, and transmits the voltage signal to the voltage processing circuit 35; the voltage processing circuit 35 obtains a variable voltage by charging and discharging, and outputs the variable voltage to the voltage comparison circuit 32.
It is understood that the signal conversion circuit 34 can be implemented by an NMOS transistor and a resistor, and can also be implemented by other diode circuits, which is not limited by the present invention.
In a specific implementation, the gate of the NMOS transistor is connected to the light receiving circuit, the drain of the NMOS transistor is connected to one end of the third resistor R3, the source of the NMOS transistor is connected to the voltage processing circuit 35, and the other end of the third resistor R3 is grounded.
It should be understood that the first trigger signal SD is output to the gate of the NMOS transistor, when the first trigger signal SD is at a low level, the NMOS transistor is not turned on, and no current flows out from the source thereof, i.e. no voltage is output; when the first trigger signal SD is at a high level, the NMOS transistor is turned on, and a voltage is output to the voltage processing circuit 35 from the source. The resistor is arranged between the NMOS tube and the power supply and mainly plays a role in limiting current.
In this embodiment, the voltage processing circuit 35 is composed of a first capacitor C1 and a fourth resistor R4. One end of the first capacitor C1 is connected to the output end of the signal conversion circuit 34, the input end of the voltage comparison circuit 32, and one end of the fourth resistor R4, respectively, and the other end of the first capacitor C1 is connected to the other end of the fourth resistor R4.
It can be understood that when the signal conversion circuit 34 has a voltage output to the first capacitor C1, the first capacitor C1 starts to charge, and the voltage at the end connected to the voltage comparison circuit 32 increases. When no voltage is output to the first capacitor C1 by the signal conversion circuit 34, the first capacitor C1 starts to discharge slowly through the fourth resistor R4, and the voltage of the end of the first capacitor C1 connected to the voltage comparison circuit 32 drops slowly. The voltage processing circuit 35 obtains a variable voltage in the above-described manner, and outputs the variable voltage to the voltage comparison circuit 32.
It should be noted that, in the present embodiment, the voltage comparison circuit 32 is implemented by one voltage comparator OP 1. The positive input terminal of the voltage comparator OP1 is connected to the voltage processing circuit 35, the negative input terminal of the voltage comparator OP1 is connected to the voltage dividing circuit 33, and the output terminal of the voltage comparator OP1 is connected to the driving circuit 10.
It can be understood that the positive input terminal of the voltage comparator OP1 inputs the variable voltage output by the voltage processing circuit 35, and the negative input terminal of the voltage comparator OP1 inputs the reference voltage output by the voltage dividing circuit 33; the voltage comparator OP1 compares the variable voltage with a reference voltage, and then outputs a second trigger signal OLT _ SD to the driving circuit 10. When the variable voltage is greater than the reference voltage, the second trigger signal OLT _ SD is at a high level, and triggers the driving circuit 10 to send a Reset signal Reset to the light receiving circuit 20; when the variable voltage is lower than the reference voltage, the second trigger signal OLT _ SD is at a low level, and the driving circuit 10 is not triggered.
Further, in order to obtain the reference voltage, the delay circuit 30 further includes: a voltage dividing circuit 33; the voltage divider circuit 33 is configured to divide the power voltage to obtain a reference voltage, and output the reference voltage to the voltage comparator circuit 32.
In this embodiment, the voltage divider circuit 33 includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 is connected to a power supply, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the voltage comparison circuit 32, and the other end of the second resistor R2 is grounded.
It should be understood that when the light receiving circuit 20 receives the burst light signal, the output first trigger signal is at a high level, so that the variable voltage output by the voltage regulating circuit 31 to the voltage comparing circuit 32 rapidly rises and is greater than the reference voltage, so that the voltage comparing circuit 32 outputs the second trigger signal OLT _ SD at a high level, which triggers the driving circuit 10 to send the Reset signal Reset to the light receiving circuit 20. In this way, the Reset signal Reset again causes the first trigger signal SD to become low level, so that no voltage is input to the voltage processing circuit 35 by the signal conversion circuit 34, the first capacitor C1 of the voltage processing circuit 35 starts to discharge, and the variable voltage output to the voltage comparison circuit 32 by the voltage processing circuit 35 starts to decrease. In order to make the second trigger signal OLT _ SD unaffected by the Reset signal Reset, the reference voltage should be less than the variable voltage until the Reset signal Reset disappears, so that the second trigger signal OLT _ SD will remain high. Therefore, the reference voltage should be calculated by combining the time from appearance to disappearance of the Reset signal Reset and the change curve of the variable voltage, and then selecting the appropriate first resistor R1 and second resistor R2 to realize the voltage dividing circuit.
In order to achieve the above object, the present invention further provides a 5G optical module device, where the 5G optical module device includes the 5G optical module circuit. The specific structure of the 5G optical module circuit refers to the above embodiments, and since the 5G optical module device adopts all technical solutions of all the above embodiments, at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
In order to achieve the above object, the present invention further provides a 5G communication system, wherein the 5G communication system comprises the 5G optical module apparatus as described above. The specific structure of the 5G optical module apparatus refers to the above embodiments, and since the 5G communication system adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and details are not repeated here.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields will be covered by the present invention.
Claims (10)
1. A5G optical module circuit, the 5G optical module circuit comprising: the circuit comprises a driving circuit, a light receiving circuit and a time delay circuit;
one end of the delay circuit is connected with one end of the light receiving circuit, the other end of the delay circuit is connected with one end of the driving circuit, and the other end of the driving circuit is connected with the other end of the light receiving circuit;
the delay circuit is used for converting the first trigger signal output by the light receiving circuit into a voltage signal, and performing charge and discharge according to the voltage signal to obtain a variable voltage;
the delay circuit is further configured to compare the variable voltage with a reference voltage to obtain a second trigger signal, and output the second trigger signal to the driving circuit, so that the driving circuit outputs a reset signal to the light receiving circuit.
2. The 5G optical module circuit of claim 1, wherein the delay circuit comprises: a voltage regulating circuit and a voltage comparing circuit;
the input end of the voltage regulating circuit is connected with the light receiving circuit, the output end of the voltage regulating circuit is connected with the input end of the voltage comparison circuit, and the output end of the voltage comparison circuit is connected with the driving circuit;
the voltage regulating circuit is used for converting the first trigger signal output by the light receiving circuit into a voltage signal, and carrying out charging and discharging according to the voltage signal to obtain a variable voltage;
the voltage comparison circuit is used for comparing the variable voltage with a reference voltage to obtain a second trigger signal, and outputting the second trigger signal to the driving circuit so that the driving circuit outputs a reset signal to the light receiving circuit.
3. The 5G optical module circuit of claim 2, wherein the delay circuit further comprises: a voltage dividing circuit;
one end of the voltage division circuit is connected with a power supply, the other end of the voltage division circuit is grounded, and the other end of the voltage division circuit is connected with the voltage comparison circuit;
the voltage division circuit is used for dividing the power voltage to obtain a reference voltage and outputting the reference voltage to the voltage comparison circuit.
4. The 5G light module circuit of claim 3, wherein the voltage divider circuit comprises: a first resistor and a second resistor;
one end of the first resistor is connected with a power supply, the other end of the first resistor is connected with one end of the second resistor and the voltage comparison circuit, and the other end of the second resistor is grounded.
5. The 5G light module circuit of claim 4, wherein the voltage regulation circuit comprises: a signal conversion circuit and a voltage processing circuit;
the input end of the signal conversion circuit is connected with the light receiving circuit, the output end of the signal conversion circuit is connected with the input end of the voltage processing circuit, and the output end of the voltage processing circuit is connected with the voltage comparison circuit;
the signal conversion circuit is used for converting the first trigger signal sent by the light receiving circuit into a voltage signal and outputting the voltage signal to the voltage processing circuit;
and the voltage processing circuit is used for charging and discharging according to the voltage signal to obtain variable voltage and outputting the variable voltage to the voltage comparison circuit.
6. The 5G light module circuit of claim 5 wherein the signal conversion circuit comprises: an NMOS tube and a third resistor;
the grid electrode of the NMOS tube is connected with the light receiving circuit, the drain electrode of the NMOS tube is connected with one end of a third resistor, the source electrode of the NMOS tube is connected with the voltage processing circuit, and the other end of the third resistor is grounded.
7. The 5G light module circuit of claim 6 wherein the voltage processing circuit comprises: a first capacitor and a fourth resistor;
one end of the first capacitor is connected with the output end of the voltage regulating circuit, the input end of the voltage comparison circuit and one end of the fourth resistor respectively, and the other end of the first capacitor is connected with the other end of the fourth resistor.
8. The 5G light module circuit of claim 7 wherein the voltage comparison circuit comprises: a voltage comparator;
the positive input end of the voltage comparator is connected with the voltage processing circuit, the negative input end of the voltage comparator is connected with the voltage dividing circuit, and the output end of the voltage comparator is connected with the driving circuit.
9. A 5G optical module apparatus, characterized in that the 5G optical module apparatus comprises the 5G optical module circuit of any one of claims 1-8.
10. A 5G communication system, wherein the 5G communication system comprises the 5G optical module apparatus of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220684008.4U CN216981915U (en) | 2022-03-28 | 2022-03-28 | 5G optical module circuit, device and system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220684008.4U CN216981915U (en) | 2022-03-28 | 2022-03-28 | 5G optical module circuit, device and system |
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| CN216981915U true CN216981915U (en) | 2022-07-15 |
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| CN202220684008.4U Active CN216981915U (en) | 2022-03-28 | 2022-03-28 | 5G optical module circuit, device and system |
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| CN (1) | CN216981915U (en) |
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